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"Altera-SoCFPGA-HardwareLib-GPIO-CV-GNU" problem

January 5, 2015, 5:28 pm
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Hi,

First, sorry for my bad english.

I m a student new in Soc boards. I am using DE1-SOC and DS 5 (free version). I m working on a bare metal project. I am trying to use cygwin gcc toolchain but i have errors when i build the project " Altera-SoCFPGA-HardwareLib-GPIO-CV-GNU ". Before talking about the problems ;I read that we can't use the debug mode without the subscription edition. Does this mean that i can't communicate with the arm processor in free version?

Waiting for your responses. Thank you
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how to legally assign global clock?

January 5, 2015, 9:16 pm
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When I place and route my entity to Actel A3PE3000 board, I got this error report.
what is the problem? How to fix it?

This is developing environment.
Software: Libero SoC v11.3(not SP1)
Hardware: A3PE3000 pqg484
Language: VHDL

Error report:
Running I/O Bank Assigner.
I/O Bank Assigner completed successfully.

Planning global net placement...
Error: PLC004: No legal global assignment could be found. Some global nets have shared
instances, requiring them to be assigned to overlapping global regions.
Global Nets Whose Drivers Are Limited to Quadrants or Which Have No Valid Locations:
|--------------------------------------------|
|Global Net |Valid Driver Locations |
|--------------------------------------------|
|CLK_c |(None)
|--------------------------------------------|
|RST_c |(None)
|--------------------------------------------|
Info: Consider relaxing the constraints for these nets by removing region constraints,
unassigning fixed cells and I/Os, relaxing I/O bank assignments, or using input
buffers without hardwired pad connections.
Error: PLC003: No legal global assignment could be found because of complex region and/or IO
technology constraints.
Error: PLC005: Automatic global net placement failed.
INFO: See the GlobalNet Report from the Reports option of the Tools menu for information about
the global assignment.
The Layout command failed ( 00:00:01 )
The Layout command failed ( 00:00:02 )
Error: Failure when executing Tcl script. [ Line 18 ]
The Execute Script command failed ( 00:00:05 )
Warning: The database was closed without a save, modifications are lost
Design closed.
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FLASH CFI table Reading problem

January 5, 2015, 9:31 pm
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hii,

my design contains nios2 prosessor i have used generic tristate controller with tristate cudit bridge to interface with flash.
my desigh system clock is 50 Mhz. i am trying to read CFI table through NIOS2 console window. I can able to read CFI table after power on reset only, but if i read again then in nios2 console window its showing NO CFI table found. but after evet board reset if i read CFI table its coming. but it should come contiuously without board reset.

Flash Device : Micron M29w128GH70Z86E
timing parameters which i am using while configuring "generic tristate controller" : setup time : 75 ns, hold time : 0ns, Read wait time : 200ns, write wait time 200 ns;


thanks
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Register interrupt return -22 error

January 6, 2015, 12:22 am
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I have a problem, return to the -22 error in the request_irq function call.
Register interrupt device is the FPGA side PushButton, offset address is 0x000100c0
The following is the content of the button_pio device tree.
The priority of button_pio is FPGA_IRQ5,Find in Handbook,The 77 is the corresponding interrupt number(#define FPGA_BUTTON_DSR_IRQ 77).
button_pio: gpio@0x1000100C0 {
compatible = "ALTR,pio-13.1", "ALTR,pio-1.0", "altr,pio-1.0";
reg = < 0x00000001 0x000100C0 0x00000010 >;
interrupt-parent = < &hps_0_arm_gic_0 >;
interrupts = < 0 45 1 >;
width = < 2 >; /* embeddedsw.dts.params.width type NUMBER */
resetvalue = < 0 >; /* embeddedsw.dts.params.resetvalue type NUMBER */
edge_type = < 1 >; /* embeddedsw.dts.params.edge_type type NUMBER */
level_trigger = < 0 >; /* embeddedsw.dts.params.level_trigger type NUMBER */
#gpio-cells = < 2 >;
gpio-controller;
The following is the driver code.

writel(pst_pio->np_pioedgecapture|0x1, &pst_pio->np_pioedgecapture);
writel(pst_pio->np_piodirection&0xfffffffe, &pst_pio->np_piodirection);
ret = request_irq(FPGA_BUTTON_DSR_IRQ, button_dsr_isr, IRQF_DISABLED, "button_dsr_fpga", (void*)(pst_dev));
if (ret != 0)
{
printk("button_dsr: unable to register interrupt %d\n", ret);
return -1;
}


writel(pst_pio->np_piointerruptmask|1, &pst_pio->np_piointerruptmask);



Comment out "interrupts = < 0 45 1 >;" after successful registration, interrupt can also be normal response.


If you have any ideas on this or info on how to debug it would be greatly appreciated.

Thanks







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CYCLONE V FPGA Thermal Resistances

January 6, 2015, 12:28 am
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I am gonna use the following model of CYCLONE V FPGA (With device number 5CGXFC3B7U15C8N) and as I checked on the website for the values of the 6 thermal resistances (http://www.altera.com/support/device...vice=Cyclone_V), I found the following numbers:

26.5 223.3 20.3 18.6 5.7 11.0


It was really impressive that the 2rd value (θJA (° C/W) at 100 ft./min.) is 10 times bigger than the first one (θJA (° C/W) Still Air) !!! An in comparison with the values of all the other models, I tend to think that there is a typo-mistake there (it is 23.3 and not 223.3). But is it possible to confirm that?

Thank you very much in advance!
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Data from FPGA to host

January 6, 2015, 1:52 am
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Hi,
I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read this and there's instructive information but it's a bit old and maybe there exist other ways.
I thought about a FIFO that would be written by the FPGA then read by the host through the USB link. Is it possible? Have I to use a virtual JTAG component?
Thanks for your help.
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Kernel Launch Overhead

January 6, 2015, 3:17 am
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Hi everyone,


I am currently trying to measure and minimize the kernel launch overhead, because the kernels that I wrote have to be launched repeatedly.


I am wondering which of the following way is the most accurate way of measuring kernel launch overhead:


1. Use the Kernel Execution tab of the profiler report and measure the "blank space" between each kernel launch.


2. Call clGetEventProfilingInfo() in host and calculate CL_PROFILING_COMMAND_START - CL_PROFILING_COMMAND_QUEUED


3. Call clock_gettime() in host to get wall-clock time between enquening kernel launches and clFinish, and then subtract the time of CL_PROFILING_COMMAND_START - CL_PROFILING_COMMAND_END from it.


Also, I am wondering if launch overhead dependents on how the kernel is written? In some case, I applied SIMD during kernel compilation, and profile report seems to indicate that while the kernel execution time is reduced, the launch overhead is also increased, which offsets the increase in performance that I expected to get.
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Send data over USB from Arrow SoCKit

January 6, 2015, 3:49 am
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In the past I've used https://github.com/mzakharo/usb-de2-fpga to send data from a DE2 to a PC over USB (mzakharo, if you ever read this, thanks for all the effort put in writing it!).

How would I do the same (send data from board to PC) with an Arrow SoCKit? Is an implementation available from Altera or is there a similiar project as mzakharo's for the SoCKit?
Preferably using only the FPGA side of the board.
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Constraining multi-phase clock oversampling circuit

January 6, 2015, 4:35 am
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Hi all,

I am implementing an oversampling circuit using multi-phase clocks. For each
clock the input signal passes through a 2-FF synchronizer, than the sampled
value is pushed into a FIFO of depth 2. The FIFOs are read with the base clock
(phase 0) and all further processing is done with this clock. What is the
proper way of constraining such circuit? Treat the clocks as unrelated or
use multicycle paths? I feel multicycle may be better, since I need to also
implement and constrain the reset/enable synchronization.

Thanks for your help.
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write data with IOWR();

January 6, 2015, 5:22 am
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here is my components slave interface :

port ( clk : in std_logic;
resetn : in std_logic;
read : in std_logic;
write : in std_logic;
chipselect : in std_logic;
writedata : in std_logic_vector(15 downto 0);
byteenable : in std_logic_vector(1 downto 0);
address : in std_logic_vector(1 downto 0);
readdata : out std_logic_vector(15 downto 0);
SIG_EXT : out std_logic_vector(1 downto 0)
);

How do I write some data to the ""writedata"" pin ???

should i write : IOWR( BASE , 0x0 , DATA);
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How to determine if I need custom components in Qsys/SOPC or not?

January 6, 2015, 6:00 am
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Hi all,

Please forgive me if my question does not make sense to u, I am a newbie to this.


I am going to use BOTH the Nios II processor AND the FPGA on the development board, meaning I need to program Nios II using C language AND also program those logic elements using VHDL.


Basically, the task distribution is as follows:


FPGA: receive signals from Nios ii and pass outputs to the external circuit


Nios ii: receive signals from FPGA's ADC, do all the processing tasks such as arithmetic operation, sort ascending/descending, comparison if-else etc, pass outputs to the FPGA


What I don't know: My question is, in my case, how do I know if I need custom components in the Qsys/sopc tool? What are the criteria if we need to create custom components?


Does it mean that if the FPGA is not doing any processing (just passing inputs and outputs), there is no need to have custom components?

If I do not create the custom component, how can I set those signals readdata, writedata, read, write, address, chipselect as we did in custom component? For instance, when readdata is activated, data will be read from slave, with nios ii as the master etc.


Thank you in advance.
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Trouble adding two TSE MACs to a single design

January 6, 2015, 6:25 am
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Hi All,

I have been working on a design using a Cyclone V board and I have encountered a problem in adding two TSE Macs to my design. The TSE Macs are such that one is a 100Mbps Small Mac and the other one is a 1000Mbps Small Mac. Both the Macs work perfectly when in seperate designs; connecting and pinging. When added to the same design the Nios software connects to both of them but when I try to ping the 1000Mbps Small Mac I get no reply. The interface for the 100Mbps Mac is MII while for the 1000Mbps Mac is RGMII. The MDIO module is included in both of them. I can't seem to find the problem, if anyone has encountered this problem and has already found a solution please it would be great help.

And yeah I encountered the same problem while configuring two 100Mbps Small Macs for a Cyclone IV board.

Regards
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Clock Crossing and FIFOs

January 6, 2015, 6:44 am
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Hello all,

I am having a custom design in handwritten VHDL and a design implemented in DSP Builder and they interface using some 16bit signals BUT running on different clocks.

I was wondering what kind of synchronization I should use for this interface. I suspect I should use the dual clock FIFO IP but I am not sure if this is the suggested way. Also if the difference in the clocks is 100MHz and 150MHz and the sample ratio of the DSP Builder module is in the rate of kHz then how deep should the FIFO be? I am not expecting any overflow and I do not need any real FIFO functionality just the snychronization of the two clock domains for a bulk of data signals.

Regards
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Using LCD on Altera DE2 board

January 6, 2015, 11:22 am
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Hi,

I am wondering how to send / display string data on LCD. Is there any driver available ? or any VHDL module which could display data on LCD ?

Best regards,
Bilal
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Failing to create SD card image of Angstrom Linux for Altera SoCrates (Cyclone V)

January 6, 2015, 10:05 am
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Failing to create SD card image of Angstrom Linux for Altera SoCrates (Cyclone V)


SUMMARY
Using supplied SD card images I can (unsurprisingly) program an SD card which boots happily on the Altera SoCrates dev board.
I have so far failed to build/generate an SD image for Angstrom for Altera SoCrates which successfully boots.


DETAILS
Using supplied images:

Angstrom (2014.06) image has two partitions:
$ sudo udevadm info -q all -n /dev/mmcblk0p1
S: disk/by-id/mmc-SA08G_0x1f6caf0e-part1
E: DEVLINKS=/dev/disk/by-id/mmc-SA08G_0x1f6caf0e-part1
E: DEVNAME=/dev/mmcblk0p1
E: ID_PART_ENTRY_TYPE=0xa2

$ sudo udevadm info -q all -n /dev/mmcblk0p2
S: disk/by-id/mmc-SA08G_0x1f6caf0e-part2
S: disk/by-label/rootfs
E: DEVLINKS=/dev/disk/by-id/mmc-SA08G_0x1f6caf0e-part2 /dev/disk/by-label/rootfs /dev/disk/by-uuid/0727d1df-c249-487a-8ad6-c3d1f5fc01b7
E: DEVNAME=/dev/mmcblk0p2
E: ID_FS_LABEL=rootfs
E: ID_FS_LABEL_ENC=rootfs
E: ID_FS_TYPE=ext3

ELDK image has 3 partitions:
$ sudo udevadm info -q all -n /dev/mmcblk0p1
S: disk/by-id/mmc-SL08G_0x616a0011-part1
E: DEVLINKS=/dev/disk/by-id/mmc-SL08G_0x616a0011-part1
E: DEVNAME=/dev/mmcblk0p1
E: ID_PART_ENTRY_TYPE=0xa2

$ sudo udevadm info -q all -n /dev/mmcblk0p2
S: disk/by-id/mmc-SL08G_0x616a0011-part2
E: DEVLINKS=/dev/disk/by-id/mmc-SL08G_0x616a0011-part2 /dev/disk/by-uuid/A931-6EC1
E: DEVNAME=/dev/mmcblk0p2
E: ID_FS_TYPE=vfat

$ sudo udevadm info -q all -n /dev/mmcblk0p3
S: disk/by-id/mmc-SL08G_0x616a0011-part3
E: DEVLINKS=/dev/disk/by-id/mmc-SL08G_0x616a0011-part3 /dev/disk/by-uuid/fc738dbc-dfec-47c0-af6d-f2cfac7b22b3
E: DEVNAME=/dev/mmcblk0p3
E: ID_FS_TYPE=ext3


I have tried two methods to generate my own SD card image:

(1) Use pre-built binaries
http://www.rocketboards.org/foswiki/.../GSRD141SdCard
$ cd ~/linux-socfpga-gsrd-14.1-cv-bin
$ sudo ~/make_sdimage.py \
-f \
-P preloader-mkpimage.bin,u-boot-socfpga_cyclone5.img,num=3,format=raw,size=10M,typ e=A2 \
-P rootfs/*,num=2,format=ext3,size=1500M \
-P zImage,u-boot.scr,soc_system.rbf,socfpga.dtb,num=1,format=v fat,size=500M \
-s 2G \
-n sd_card_image_cyclone5.bin

(2) Build all from scratch
http://www.rocketboards.org/foswiki/...romOnSoCFPGA_1
Angstrom v2014.06

This appears to complete successfully and the following files are created:
Angstrom-console-image-eglibc-ipk-v2014.06-socfpga_cyclone5.rootfs.cpio
Angstrom-console-image-eglibc-ipk-v2014.06-socfpga_cyclone5.rootfs.ext3
Angstrom-console-image-eglibc-ipk-v2014.06-socfpga_cyclone5.rootfs.manifest
Angstrom-console-image-eglibc-ipk-v2014.06-socfpga_cyclone5.rootfs.tar.xz
console-image-socfpga_cyclone5.cpio
console-image-socfpga_cyclone5.ext3
console-image-socfpga_cyclone5.manifest
console-image-socfpga_cyclone5.tar.xz
file_list.txt
modules--3.10-r1.2-socfpga_cyclone5-20141222135550.tgz
modules--3.15-r1.2-socfpga_cyclone5-20141222105845.tgz
modules-socfpga_cyclone5.tgz
README_-_DO_NOT_DELETE_FILES_IN_THIS_DIRECTORY.txt
socfpga_arria5-20141222135550.dtb
socfpga_arria5.dtb
socfpga_arria5_socdk-20141222105845.dtb
socfpga_arria5_socdk.dtb
socfpga_cyclone5-20141222135550.dtb
socfpga_cyclone5.dtb
socfpga_cyclone5_socdk-20141222105845.dtb
socfpga_cyclone5_socdk.dtb
socfpga_vt-20141222105845.dtb
socfpga_vt-20141222135550.dtb
socfpga_vt.dtb
u-boot-socfpga_cyclone5
u-boot-socfpga_cyclone5-2013.01.01-r0
u-boot-socfpga_cyclone5-2013.01.01-r0.bin
u-boot-socfpga_cyclone5-2013.01.01-r0.img
u-boot-socfpga_cyclone5.bin
u-boot-socfpga_cyclone5.img
u-boot-spl-socfpga_cyclone5
u-boot-spl-socfpga_cyclone5-2013.01.01-r0
u-boot-spl-socfpga_cyclone5-2013.01.01-r0.bin
u-boot-spl-socfpga_cyclone5.bin
vmlinux
vmlinux-3.10-r1-socfpga_cyclone5-20141222135550
vmlinux-3.15-r1-socfpga_cyclone5-20141222105845
zImage
zImage--3.10-r1.2-socfpga_cyclone5-20141222135550.bin
zImage--3.15-r1.2-socfpga_cyclone5-20141222105845.bin
zImage-socfpga_cyclone5.bin


*** PROBLEMS/QUESTIONS ***
(1) Using the pre-built binaries the SD created does not boot correctly on the Altera SoCrates board.
I suspect it is an issue with the dtb or perhaps it wasn't built for the SoCrates (the dtb file is socfpga.dtb not socfpga_socrates.dtb)
Am I missing something?

(2) Using the files built from scratch I can't see which files relate to the ones required for an SD image.
How do I go from this to a SD card?

(3) The working Angstrom and ELDK SD cards have a different number of partitions.
I can't see what is on the 0xA2 Angstrom partition to see what files have been used.
Any ideas on how I might view the contents of the 0xA2 partition?


REFERENCES
http://www.rocketboards.org/foswiki/...romOnSoCFPGA_1
http://www.rocketboards.org/foswiki/.../GSRD141SdCard
http://www.rocketboards.org/foswiki/...41ReleaseNotes
(and the rest of the web through generic search engines to no avail)


THANKS
Apologies in advance for any duplication or failure to adhere to forum rules, but I have tried to be as thorough as possible.
Any help or suggestions will be gratefully received.
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Stratix V Dev Board - Presetting Clocks

January 6, 2015, 3:32 pm
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Hi All... First thanks in advance for the help. We have been working with the dev board for a while but have not had a need to change flash until now. To make remote testing easier we need to put in a user load which is working nicely but we also need to have some clocks preset as well. Upto now we were using Clock Control but saw a post that said you could preload such that CPLD would auto set it. Question is how?? If its in a doc can you please point me to it? Thanks.
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Arrow SoCKit: HSMC_REF_CLK (100MHz) Not Working

January 6, 2015, 3:49 pm
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@moderator: I found one other thread in this former that mentioned the HSMC_REF_CLK on the Arrow SoCKit and managed to post my question there, but (1) that was somewhat rude to hijack this persons thread and (2) my question is not well publicized. Hence the new thread.
Quote:
I have no signal from the HSMC_REF_CLK (100MHz) that should be utilizing Pin 9 (with HCSL I/O Standard). I've tried two Dev Kits, same thing. I even ask a fellow EE next door to try to test the 100MHz clock signal -- he too cannot get a signal from this clock. What Am I missing? If I were to take a simple LED blink module and feed it with the HSMC_REF_CLK (Pin 9 as input), then the module should function? Furthermore, SignalTap is not produce a waveform on this Pin.
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Programming EPCS Devices With a Processor

January 6, 2015, 5:13 pm
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Hi,

First, I've searched the forum for hits on this topic. In the first few dozen of hits, I didn't see anything that fit. So I apologize in advance if the answer is buried deep somewhere that I missed.

I am not an FPGA designer, but an embedded guy. I need to take a file on a PC (probably .sof or .pof???) and send it over USB to the embedded processor and from there program it into the EPCS device. The EPCS commands along with the /cs clock and data are all pretty clear. What I'm missing is how to interpret the .sof or .pof file so I can send the raw binary over USB and then clock it into the EPCS. I searched the web for a description of either .sof or .pof, but all I've found are references to existing software or devices which do this and that doesn't help.

Can someone point me to a document I can study to figure this out?

Thanks for the help!

Dave
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audio input and sampling via altera DE1 kit using SD card

January 6, 2015, 5:56 pm
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Hi,
here are the question i facing when using SD card as input source in altera DE 1 kit

1. How do i able to read a .wav audio file in SD card using FPGA kit via Verilog HDL coding?
2. How do i able to sample the audio's sampling frequency?
3. Are I able to mix 2 audio files together via using FPGA kit or i need to mix it before i insert the audio file into the FPGA kit
4. How to implement megawizard into the coding??
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how to Simulate Nios II with custom component?

January 6, 2015, 8:47 pm
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im new here and my first post, sorry for not being so professional...
I successfully simlated Nios II on modelsim using QSYS and Eclipse (run as "nios ii Modelsim"), but when I add my custom component to Qsys system it cannot generate testbench or simulation model for it.here is the error:

Error: MatrixMul_0: MatrixMul(my Custom Hardware Design) does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis.

I red two tutorial "Altera JTAG-to-Avalon-MM Tutorial" and "how to use Avalon-MM Master BFM" but there was not any sign of Nios processor or custom hardware. Now my question is :
-when we have user defined hardware (in verilog or systemverilog) should we put it inside the qsys system(as a Nios peripheral) or ..!? because last time I put it inside nios and get the result from FPGA DE2 board but not in simulation.
-and how to simulate both hardware and software?

regards.
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