Timing constraint for 1000Mbps Small Mac in Quartus 14.0

January 7, 2015, 1:37 am

≪ Previous: how to Simulate Nios II with custom component?

Hi All,

Quartus has stopped generating an automatically generated timing constraint file after Quartus 14.0 and I am having problems in constraining the 1000Mbps Small Mac. The design is fully constrained but there are a lot of irregularities relating to the RX Clock of the Mac. If anyone has an example .sdc file to share it would be a great help or just guide me through constraining the Mac.

Thanks in advance

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Cyclone lll LVDS IO

January 7, 2015, 2:17 am

≫ Next: classic timing analyzer wizard

≪ Previous: Timing constraint for 1000Mbps Small Mac in Quartus 14.0

Hi,

Currently, we are using Cyclone lll FPGA for our application. We plan to interface LVDS output signals with sensor chip. We had assigned LVDS related O/P signal in bank 7 and bank 8(top banks). As per the Cyclone lll handbook, top(bank 7 & 8) and bottom(bank 3 & 4) only support for Emulated LVDS signals while others banks supports for both LVDS and as well as Emulated LVDS signals.

For Emulated LVDS signal interface, is it compulsory to put external 3R resistor network? Presently we had not included any external 3R resistor network with emulated LVDS output signal but we had put only 100R resistor between differential signals. So, my concern is that whether FPGA provide proper signal interface with sensor chip or we need to redesign the board again.

Will appreciate comments.

Best Regards,
Mayur Akbari

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classic timing analyzer wizard

January 7, 2015, 2:49 am

≫ Next: How to read pin I/O mode from POF file?

≪ Previous: Cyclone lll LVDS IO

How i choose the right value for the fmax of a project in order to have correct simulation waveforms?

kostas

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How to read pin I/O mode from POF file?

January 7, 2015, 3:00 am

≫ Next: Configuring Cyclone IV E over serial interface - INIT_DONE don't go high

≪ Previous: classic timing analyzer wizard

Hi everyone,

I am trying to figure out how to use the POF file to determine whether a certain pin on my MAX V (1270T144C5N) is set to input or output mode (to prevent damage on a board I have designed that is used by others).
My question is: What part of the POF file tells me the I/O mode of my pin?

Thank you very much
Alexander

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Configuring Cyclone IV E over serial interface - INIT_DONE don't go high

January 7, 2015, 5:13 am

≫ Next: ALtera 14.0 drops support for Nios2 on Cyclone III and Stratix III !?

≪ Previous: How to read pin I/O mode from POF file?

Hello everyone,

I'm configuring a Cyclone IV E over serial interface with a rbf file that I have stored in my MCU's flash memory. It was working fine till I replaced the rbf for a new version (larger). Now the INIT_DONE pin of the fpga won't go high. I have no idea why. It there some sort of a example code how to configure these devices over serial interface? Here's the code that I'm using. It seems to comply with the documentation. Or what could be wrong with it? Thanks for any suggestions.

Code:

void fpgaConfig(void){

    int i;

    int length;

    uint16_t temp;

    spiDAT1_t dataConfig;

    uint32 PC0Backup;





    gioSetBit(spiPORT1, SPI_PIN_SOMI, 0);    // nConfig low

    delay(0xffff);    // wait

    gioSetBit(spiPORT1, SPI_PIN_SOMI, 1);    // nConfig high

    while(gioGetBit(spiPORT1, SPI_PIN_ENA) == 0);    // wait until nStatus is high

    PC0Backup = spiREG1->PC0;

    spiSetFunctional(spiREG1, PC0Backup | (1U << SPI_PIN_SOMI));    // set nCONFIG as SPI pin





    dataConfig.CSNR = 0;

    dataConfig.CS_HOLD = 0;

    dataConfig.DFSEL = SPI_FMT_0;

    dataConfig.WDEL = 0;

    length = sizeof(designData);

    for(i = 0; i < length; i++)

    {

        temp = designData[i];

        spiTransmitData(spiREG1, &dataConfig, 1, &temp);

    }

    delay(0xfffff);    // wait

    while(gioGetBit(spiPORT2, SPI_PIN_CLK) == 0);    // wait until CONF_DONE is high

    while(gioGetBit(gioPORTB, 7) == 0);    // wait until INIT_DONE is high

    spiSetFunctional(spiREG1, PC0Backup);    // put back the original value. This is important to make reconfiguration possible

}

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ALtera 14.0 drops support for Nios2 on Cyclone III and Stratix III !?

January 7, 2015, 8:48 am

≫ Next: Early power Estimation Cyclone V

≪ Previous: Configuring Cyclone IV E over serial interface - INIT_DONE don't go high

Hi,

I notice, based on 14.0 Altera IP release notes, that they appear to be dropping support for the Nios2 on Stratix III and Cyclone III starting with 14.0?!

We were hoping for a patch for rd1127772013_702, a fairly serious bug, but perhaps I shouldn't hold my breath.

Reference attached extract from the IP release notes, or the URLs below.

http://www.altera.com/literature/rn/rn_ip.pdf

http://www.altera.com/support/kdb/solutions/rd11272013_702.html

Jeff

Nios2 IP Release Notes 14.0, June 2014
---------------------------------------------

Fixed issue concerning instruction cache operation with ECC
Added Nios II Gen2 core
Improved Nios II/f core.
ECC support for data cache and TCMs.
Optional 32-bit addressing.
Faster arithmetic instructions.
Optional uncached peripheral memory region.
More flexible debugging options.
Avalon streaming interface for trace.
Includes Nios II/f and Nios II/e. Nios II/s processor core not supported.
Simpler, more flexible parameter editor in Qsys.
Removed support for the following devices:
Stratix III
Cyclone III
Cyclone III LS

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Early power Estimation Cyclone V

January 7, 2015, 9:44 am

≫ Next: Problems with Memory Mapped IO in DE2 Media Computer

≪ Previous: ALtera 14.0 drops support for Nios2 on Cyclone III and Stratix III !?

Hi,
I am trying to use the early power estimation spreadsheet with Cyclone V, but it is extremely slow and does not work with open office.
Are there some tricks to use it?

Regards.

Stefano

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Problems with Memory Mapped IO in DE2 Media Computer

January 7, 2015, 10:38 am

≫ Next: Modular SGDMA - Streaming to Memory Mapped Random first write.

≪ Previous: Early power Estimation Cyclone V

I created a custom component in Qsys for the DE2 Media Computer. But when I try to access the component in Altera Monitor Program it doesn't seem to exist. In fact the space is filled with garbage data. Also values entered into one memory address appear in several other locations....for example if I enter a value in 0x800000 it appears in 0x000000 and 0x2f800000 as well. Any suggestions as to what the problem may be? Or has anyone encountered this problem as well and found a solution?
Also the component works fine in the DE2 Basic Computer, but the problem is I need the graphics buffer provided by the Media Computer.

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Modular SGDMA - Streaming to Memory Mapped Random first write.

January 7, 2015, 10:45 am

≫ Next: FPGA or CPLD?

≪ Previous: Problems with Memory Mapped IO in DE2 Media Computer

Hi,

I am using the Modular SGDMA to write memory into DDR3 memory, and then a second one to read it back out again. The reading is all working fine and writing into the memory works as well, except there is one minor glitch.

Basically when I issue a descriptor to write a given number of symbols to, say, address 0 (the burst length is 16 and I'm using a 512bit wide data bus).
Then, Symbol 0 arrives via Avalon-ST. It immediately gets written by the SGDMA to address 0xFFFFFFFF.
The next arrives and it gets queued up in the FIFO. Once symbol 16 arrives, there is a burst write of 16 symbols to address 0x0.

Essentially this means the first symbol to arrive for any descriptor appears to get written to 0xFFFFFFFF, and then the remaining symbols get written to memory one address earlier than they should, thus the first symbol is lost and the rest are shifted from where they should be.

Any thoughts on why this is happenning?

Thanks.

EDIT:
I'm using a Stratix V DSP board and Quartus 14 Subscription Edition, have SignalTap set up to look at important parts of the SGDMA controller and data input. Also the design meets timing comfortably.

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FPGA or CPLD?

January 7, 2015, 11:08 am

≫ Next: Splitter

≪ Previous: Modular SGDMA - Streaming to Memory Mapped Random first write.

We have a design that we would like to fit in a CPLD or FPGA, we have extremely limited experience with both technologies, and need help to determine which technology and which part in the particular technology would be suitable. I have attached block diagrams to accompany the following description, the block diagram show two possible ways of implementing what we need.

What we need to implement in the CPLD or FPGA is:

16 counters of 18 bits each that can count at a rate of 1 MHz.
Logic to provide a serial bus to read the 16 counters.
The ability to read the previous counter results while new counting is occurring, (i.e. latches).
We need a very small package (footprint)
And as low power as is possible.
The attached pdf will give more insight to the requirement.

Your assistance is appreciated.:confused:

Attached Files

Radcompass Counters.pdf (134.2 KB)

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Splitter

January 7, 2015, 11:58 am

≫ Next: Issue of multiprocessor boot from EPCS16N

≪ Previous: FPGA or CPLD?

Hello,

I am looking to design a splitter and I don't have much experience with FPGA's. I want to be able to take a VGA signal in at a resolution i.e. 1440x1800 and split that signal to 2 outputs but splitting the signal into 1440x900 with a upper and lower image.
Which FPGA would you recommend and are there any evaluation kits that would be helpful?

Thank you in advance!
Brian

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Issue of multiprocessor boot from EPCS16N

January 7, 2015, 5:55 pm

≫ Next: look for suggestions for Opencl & FPGA

≪ Previous: Splitter

Issue of multiprocessor boot from EPCS16N

Hi all

I have create a dual processor in Nios with separate on-chip memory, two processor share a same epcs16N. Two .elf file work fine when using JTAG download and debug.

How can I program 2 elf files into EPCS16N?

Can anyone help me?

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look for suggestions for Opencl & FPGA

January 7, 2015, 9:56 pm

≫ Next: CFI table reading problem

≪ Previous: Issue of multiprocessor boot from EPCS16N

Hi
recently,I want to test the performance of opencl in FPGA, but I have no experience on FPGA.
due to limited capital, I want to buy soc board.
Can you recommend board to me , I just notcie two boards in altera web,one is cyclone V SoC Development kit and SoC Embedded Design Suitehttp://www.altera.com/products/devkits/altera/kit-cyclone-v-soc.html.
another is DE1-SoC Board provided by Terasic http://www.terasic.com.tw/cgi-bin/pa...=Taiwan&No=927. but these two boards don't include altera SDK for OpenCl. How to get licenses of opencl SDK and quartus ? I should choose which board? or other one.
ps. To develop Opencl If I need these tools, quartus, altera sdk for opencl, EDS?

Thanks

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CFI table reading problem

January 7, 2015, 10:50 pm

≫ Next: system verilog system functions in quartus integrated Synthesis

≪ Previous: look for suggestions for Opencl & FPGA

After reading CFI query table from FLASH using NIOSII command shell my flash is going in CFI query mode and i unable to read CFI table again unless i press board reset.How to go back normal mode and read CFI table continuously without board reset.

Board: DE2-115.
Altera: 14.0.
IP controller using: Generic Tri state Controller.

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system verilog system functions in quartus integrated Synthesis

January 8, 2015, 12:18 am

≫ Next: Video over IP Reference Design without Nios! Is it possible?

≪ Previous: CFI table reading problem

Is there ability to use sv system function such as $ceil, $pow etc to caluculate module parameters (localparmeters)?
For example something like that

Code:

parameter integer N_COEFF_ACCUM =($ceil(( SUMM1 + SUMM2 - SUMM3) * CLK_FREQUENCY));

SUMM1, SUMM2, SUMM3 are real parameter

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Video over IP Reference Design without Nios! Is it possible?

January 8, 2015, 12:56 am

≫ Next: flash_boot and CFI table Read Problem

≪ Previous: system verilog system functions in quartus integrated Synthesis

Hi
The "Video over IP" reference design (AN-374) accepts IP packets and outputs Transport Streams (TS). It targets a board with External SDRAM for packet storage, External SRAM & Flash for Nios code & data storage. Design targets Stratix II & Stratix IV, despite its out-of-date user manual which claims Stratix II & Cyclone II.
The reference design includes:

Nios II
Ethernet MAC
UDP/IP
RTP Receiver
RTP Transmitter
RTP to TS
TS to RTP
SOPC System which integrates IPs

What we changed:
My PCB has no external SDRAM or Flash for Nios code & data. Furthermore I don't have enough space available in the FPGA for Nios. Since I only need TSoIP receiver, and I have no external SRAM & Flash for Nios code & data, and because I don't have much space inside FPGA, I removed the Nios, RTP transmitter & TS to RTP. I also made some changes to design, so that I could get output TS sync lock in simulation. For now FEC is disabled to make debugging simpler.

Observations:
After synthesis on Cyclone III, design works for a few minutes (different for different configs, sometimes a few seconds!) and we have TS sync lock at the output. Then it loses TS sync and hangs for ever. State machines are stuck at some states, waiting for some vents that never occur. Unfortunately different behaviors are observed. Some state machines stick to some states in some situations, where some others stay in some others in other situations. Tracing such events goes through SOPC generated files which are not understandable. It is not easy to understand what this component input or that output mean, to trace to the problem root. It seems that an arbitartor (not the arbiter in the user guide, an SOPC generated arbitrator) stalls writing to a buffer & reading from another buffer; but it never changes back for operation to continue. simulating the design for several minutes (for TS sync lock and then TS sync loss) is not possible, since it probably takes months long.

My Question:
Since we removed Nios, we are suspicious that Nios is mandatory in this design. Documentation is not so detailed. As far as we understood, Nios issues IP, Port Number and Subnet Mask. It also has avalon interface to UDP/IP for some software debug commands (Am I right? Just debug???). We replaced IP, etc with constants. Since there is no Nios now, no command is sent to anywhere.
Is it correct to remove Nios as we did or it is a mandatory component of this design?

Sorry for my long post
Thanks

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flash_boot and CFI table Read Problem

January 8, 2015, 12:57 am

≫ Next: De1 board IP?

≪ Previous: Video over IP Reference Design without Nios! Is it possible?

hii,

my design contains nios2 prosessor i have used generic tristate controller with tristate cudit bridge to interface with flash.
my desigh system clock is 50 Mhz. i am trying to read CFI table through NIOS2 console window. I can able to read CFI table after power on reset only, but if i read again then in nios2 console window its showing NO CFI table found. but after evet board reset if i read CFI table its coming. but it should come contiuously without board reset.

Flash Device : Micron M29w128GH70Z86E
timing parameters which i am using while configuring "generic tristate controller" : setup time : 75 ns, hold time : 0ns, Read wait time : 200ns, write wait time 200 ns;

thanks in advance

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De1 board IP?

January 8, 2015, 1:18 am

≫ Next: cycloneive boot from sd card

≪ Previous: flash_boot and CFI table Read Problem

Hello,

which of the IPcomponents/files can I export to another board using an Altera FPGA, "legally" selling the derivate cicuit.
And which ones are free to use, using the web edition software?

For the De1 board I have the following files.. The code graycounter is my own file, the rest is standard for the board.

Attached Images

components.jpg (20.4 KB)

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cycloneive boot from sd card

January 8, 2015, 3:47 am

≫ Next: WM8731 slave mode BCLK signal always low

≪ Previous: De1 board IP?

Hello to all!
I'm working with a cycloneive board.

I use the program university avalon sd card interface, and i can read and write a file (fat16) from/to a 2GB sd card.
I would copy a .bin file to sd card, generated with "nios2-elf-objcopy -O binary file.elf output_file.hex" command, and store it in in sdram memory for execute it:

int mem=0;
int* pt_sdram=(SDRAM_0_BASE +0x00100000);
unsigned char midata[4];

for(i=2020;i>0;i--){
mem=0;
midata[0]= alt_up_sd_card_read(sd_fileh);
midata[1]= alt_up_sd_card_read(sd_fileh);
midata[2]= alt_up_sd_card_read(sd_fileh);
midata[3]= alt_up_sd_card_read(sd_fileh);

/*
*/

mem=midata[0];
mem<<=8;
mem|=midata[1];
mem<<=8;
mem|=midata[2];
mem<<=8;
mem|=midata[3];
IOWR(pt_sdram,0,mem);
++pt_sdram;

}

//andrun it with:

asm (
"call (SDRAM_0_BASE +0x00100000);"

);

Is it possible?

TNX, Luca

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WM8731 slave mode BCLK signal always low

January 8, 2015, 4:23 am

≫ Next: How to do read operation using opencore i2c ip drivers?

≪ Previous: cycloneive boot from sd card

I am using the audio codec shield made for arduino (https://www.sparkfun.com/products/11290) with a DE0-NANO development board.

I am measuring the signals with a usbee AX pro

In the attached picture you can see that the I2C communication is working and ADDA_LCR signal is 44.1 KHz

The chip is configured to run in slave mode so the signals need to come from the FPGA.

I also attached the code i am using now

Attached Images

logicanalyzer.jpg (20.5 KB)

Attached Files

ADDA.vhd (10.7 KB)

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