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How to do read operation using opencore i2c ip drivers?

January 8, 2015, 6:50 am
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In my design, I use opencore i2c ip for my i2c interface. This core provides the drivers which includes I2C_init, I2C_start, I2C_read, I2C_write.

The writing operation is straightforward but sometimes i2c reading operation is confused. In this case, the I2C_read function is :


/************************************************** **************
int I2C_read
assumes that any addressing and start
has already been done.
reads one byte of data from the slave. on the last read
we don't acknowldge and set the stop bit.
inputs
base = the base address of the component
last = on the last read there must not be a ack


return value
byte read back.
15-OCT-07 initial release
************************************************** ***************/
alt_u32 I2C_read(alt_u32 base,alt_u32 last)


so this read function doesn't have an argument for the i2c slave address. So my understanding is I need a writing operation before read to write to the i2c slave for the initial inner address. Since before the read or write, it requests a start, what I think the general procedure is :

i2c_start(); // configure for write
i2c_write(base, slave_inner_address, last);
i2c_start(); // configure for read
i2c_read();


Currently I don't have a hardware for testing, if anyone has experience about opencore i2c ip driver, I would appreciate if you can have a look to see whether my understanding about reading operation is correct.

Thanks in advance.
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FPGA and HPS freeze when programming FPGA

January 8, 2015, 6:21 pm
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Our custom board's FPGA and HPS will freeze whenever we programming the FPGA. Our design is heavily based on Helio board.
We have tried to program it by using JTAG, U-Boot and Linux, all led to same result. Our MSEL setting is 00000. We have disabled the 3 bridges before program the FPGA.


We observed that whenever we program the FPGA, the 1.1V core voltage will drop to 0.9xxV and hence freeze the FPGA and HPS. Even if we try to manually pump in higher voltage like 1.2V or 1.3V the voltage still drop to 0.9xxV. Anybody has any idea who is drawing the current causing the voltage drop?


On a separate note, we also have this kind of strange issue where different project/compilation will give us different result where some will freeze them but some would not. Anyone know how could this happen?
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Why Altera MPL (Minimal Preloader) build error with ARMCC ?

January 8, 2015, 9:51 pm
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Follow the instruction of C:\altera\14.1\embedded\examples\software\Altera-SoCFPGA-HardwareLib-MPL\README.txt.

I am using Cyclone V SoC Dev Kit, in comfig.mk, I modified content as below:
BOOT_SOURCE := QSPI
DEVICE := C5
COMPILER := GNU

I am using DS-5 to import this example (C:\altera\14.1\embedded\examples\software\Altera-SoCFPGA-HardwareLib-MPL)
Build project is successful.

But when I set
COMPILER := ARM

then get compile error as below:

armcc -o bin/sequencer.o -c -g -O3 -I. -I./core/ -I./core/altera_ip -IC:/altera/14.1/embedded/ip/altera/hps/altera_hps/hwlib/include -IC:/altera/14.1/embedded/ip/altera/hps/altera_hps/hwlib/include/socal -IC:/altera/14.1/embedded/examples/hardware/cv_soc_devkit_ghrd/software/preloader/generated -IC:/altera/14.1/embedded/examples/hardware/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0 -DARMCC -DQSPI_BOOT -DCONFIG_SOCFPGA_CYCLONE5 -DPRINTF_UART --diag_suppress=9931 --cpu=Cortex-A9.no_neon.no_vfp --split_sections --c99 --no_unaligned_access -DARMCOMPILER --diag_suppress=68 --diag_suppress=177 --diag_suppress=550 C:/altera/14.1/embedded/examples/hardware/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0/sequencer.c
"C:/altera/14.1/embedded/examples/hardware/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0/sequencer.c", line 76: Error: #79: expected a type specifier
asm(".global __alt_stack_pointer");
^
"C:/altera/14.1/embedded/examples/hardware/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0/sequencer.c", line 76: Error: #260-D: explicit type is missing ("int" assumed)
asm(".global __alt_stack_pointer");
^
"C:/altera/14.1/embedded/examples/hardware/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0/sequencer.c", line 77: Error: #79: expected a type specifier
asm("__alt_stack_pointer = " STRINGIFY(STACK_POINTER));
^
"C:/altera/14.1/embedded/examples/hardware/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0/sequencer.c", line 77: Error: #260-D: explicit type is missing ("int" assumed)
asm("__alt_stack_pointer = " STRINGIFY(STACK_POINTER));
^
C:/altera/14.1/embedded/examples/hardware/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0/sequencer.c: 0 warnings, 4 errors
make: *** [bin/sequencer.o] Error 1
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USB Blaster II locks up after non-volatile key programming

January 8, 2015, 10:31 pm
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Hi all,

I am programming non-volatile design security key to Cyclone V using USB Blaster II. I am using Quartus 14.1 on Windows 7 64bit and USB Blaster II driver that comes with 14.1.

I know two different methods of programming the key from command line. These are:

quartus_jli.exe -c1 keyfile.jam -aKEY_PROGRAM
and
quartus_pgm -c1 -k -m JTAG -oP';keyfile.ekp'

But after programming the key, the USB Blaster II goes into a state that it no longer can program a .sof for example. It seems that it gets really slow. If following command is used:
quartus_pgm -c1 -m JTAG -oP';fpga.sof'
It starts programmer operation, green led on USB Blaster II is flashing. After about 30 seconds, errors 'Can't access JTAG chain' and 'CONF_DONE pin failed to go high in device 1' are given.

The USB Blaster can be remedied from this state by unplugging and replugging. It can also be remedied by disabling and enabling it from device manager.

Does anyone know of a command that could be used to reset the USB Blaster II, which preferably could be run without administrator privileges?

The only solution I have found so far is to use devcon.exe (it is basically a command line version of windows device manager):
devcon.exe disable "USB\VID_09FB&PID_6010&MI_00*"
devcon.exe enable "USB\VID_09FB&PID_6010&MI_00*"
but it requires administrator privileges, which is not nice when running a Labview / Teststand script.


Note; Quartus 14.1 is actually the first version which supports programming of the non-volatile key with USB Blaster II. If using Quartus 14.0 it gives message "Programming status: Current hardware doesn't support security key programming" or "Error: This hardware does not support frequency control", depending on used tool. Also, if driver from earlier Quartus than 14.1 has been installed on USB Blaster II, it can be really painful to get it working on that computer with the new driver.
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how to use ip core in www.opencore.org

January 9, 2015, 12:46 am
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how to use ip core in www.opencore.org

In my recent work , i found a very useful website :www.opencores.org ;
But ,how to use these ip core ? the most cores there are based on WISHBONE .

The only thing i know is that we can translate the wishbone to AVALON ,then add in sopc self component ;

Then , the big problem is how to write drivers and main function ?

can some one give me some suggestions ?

thanks

Tommei
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could i use Cyclone IV to implement PCIe controller

January 9, 2015, 1:02 am
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just as the titles ,can you tell me ?Must i buy a higher class FPGA such as stratix？
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signal as loop termination condition

January 9, 2015, 5:00 am
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Hi all ;
I am writing vhdl at quartus ii 32 bit v. 13.1.0 web edition for terasic d0 board.

I am trying to write a time delay procedure but getting "VHDL Loop Statement error at <location>: loop must terminate within 10,000 iterations" (ID: 10536).

This is my main code.
Code:
library ieee;use ieee.std_logic_1164.all;
use work.time_issues.all;


entity DD is
    port (clk:in std_logic);
end entity DD;
   
architecture behav of DD is
    constant step_count  : integer := 2500000; --#step's for 10ms at 50Mhz clk
    begin
    time_delay(clk,step_count);
end architecture behav;
And this is the package code.
Code:
library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


PACKAGE time_issues IS
    PROCEDURE time_delay (signal t_clk:in std_logic; step_count: in integer);
END time_issues;
   
PACKAGE BODY time_issues IS
    PROCEDURE time_delay(signal t_clk:in std_logic; step_count: in integer) IS
   
        variable count : integer;
        variable count_out : integer;
    BEGIN


        count:=0;
        loop
            if (t_clk) then
                count := count + 1;
            else
                count := count + 0;
            end if;
            exit when (count = step_count);
        end loop;
       
       
    END PROCEDURE time_delay;
END PACKAGE BODY time_issues;
At the definition of error (ID: 10536) it is written that if i use a signal for loop termination conditon this may happen. But then if i want to synchronise my procedure with clk signal how would i do it.
I tried to use "wait until clk;" but appears to be i cannot use wait statement in a procedure.

Any help ? Thanks
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eMMC OS bring-up: Best method to write SoC HPS image to embedded MMC memory

January 9, 2015, 6:18 am
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Hello!

I'm sure this question was asked before, hence I'm sure someone can help me.

I would like to know how to write a existing SoC HPS image (containing the OS, preloader, U-Boot and applications) to an empty embedded SD/MMC memory (which is soldered/fixed and can't be removed).
Or in other words - I would like to know how to bring-up a Altera SoC HPS system with a soldered embedded SD/MMC memory.
All descriptions I've found are based on SD cards which can be simply disconnected from the Altera board and plugged into a PC to write the image (by using winimager or dd linux command).
Obviously, this solutions can not be used if no Linux is running on the SoC and if the SD/MMC memory can be unplugged.

Is there a method to do this with Quartus II and JTAG (USB blaster) or the EDS?
Or do I have to write a FPGA code to configure partitions on the SD memory manually (via the F2H bridge and the DMA) and to transfer all files and everything else manually?

Thank's for your help.
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veilog code for demux unwanted latch at demux output problem

January 9, 2015, 6:49 am
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hey guys!! here is my code for 1:16 demux in verilog (quartus 2)

Code:
module demux(sel, din , dout0 , dout1 ,dout2 , dout3 , dout4 , dout5 ,dout6 ,dout7 ,
                dout8 ,dout9 , dout10 , dout1 , dout12 , dout13 , dout14 , dout15);
input  din;
input[3:0] sel;
output dout0 ,dout1 ,dout2 ,dout3 ,dout4 ,dout5 ,dout6 ,dout7,
        dout8, dout9, dout10, dout11 ,dout12 ,dout13 , dout14 ,dout15;
       
reg    dout0 ,dout1,dout2 ,dout3 ,dout4 ,dout5 ,dout6 ,dout7,
        dout8 ,dout9 ,dout10 ,dout11 ,dout12 ,dout13 ,dout14 ,dout15 ;
       
always @(sel or din) begin
 case(sel)
    4'b0000: dout0 = din ;
      4'b0001: dout1 = din ;
      4'b0010: dout2 = din ;
      4'b0011: dout3 = din ;
      4'b0100: dout4 = din ;
      4'b0101: dout5 = din ;
      4'b0110: dout6 = din ;
      4'b0111: dout7 = din ;
      4'b1000: dout8 = din ;
      4'b1001: dout9 = din ;
      4'b1010: dout10 = din ;
      4'b1011: dout11 = din ;
      4'b1100: dout12 = din ;
      4'b1101: dout13 = din;
      4'b1110: dout14 = din;
      4'b1111: dout15 = din;
      endcase
end
endmodule
after compilation i get this warning :
Verilog HDL Always Construct warning at <location>: inferring latch(es) for variable "<name>", which holds its previous value in one or more paths through the always construct

how can i write this code without getting this warning because i do not want any latches there...
any help is welcome.
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Altera monitor program terminal device problem

January 9, 2015, 7:30 am
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Hi guys,


I have some troubles with the Altera Monitor Program.
As I write in the title, when I create a new project, I select all the needed parameters and then,
when I am on the "Specify system parameters" table, the Terminal device drop-down menu can't see the device
and it show me " <none> " and I can't select any other things... Someone can help me ?

I use the DE2 board with the latest version that support Cyclone II (Quartus 13.0sp1 and Altera Monitor Program 13.0) on a windows 7 64Bits machine.

Thank you,


Regards.
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Upgrading from QII 9.1 SP2 to QII 14.1

January 9, 2015, 9:35 am
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Hi there,

Most of our projects are still on QII 9.1 SP2 (with some on QII 11.0), we have been thinking about upgrading them to a newer version of Quartus II. But a few things concerns us:

1. SOPC to Qsys flow

I noticed that a lot of things has changed significantly in the project directory and function files. We use SVN to track the changes of projects, all the projects can be reconstructed by script files in the old QII flow. Now if we migrate to newer QII, we will need to rewrite these script files. The first thing is to know those new key function files (.qsf, .tcl, .dcf, .sopcinfo, etc.) and where to find them. Does Altera has a document describing these things?

2. Resource usage

About 2 years ago, we looked at the possibility to go this direction, and found the QII 12.x seemed to be less capably in optimizing the resource usage comparing to QII 9.1 SP2, and was unable to fit one of our projects. Has Altera improved this on its newer versions?

3. Nios development flow

Is the embedded system development flow kept backward compatible from QII 9.1 to QII 14.1? We understand that there may be some adjustments need to be made to get thing compiled again in QII 14.1, but is it going to be lots of surprises?

I would appreciate if anyone with similar experience could shed some light on these topics, or anything related to this.

Thanks!
Hua
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make: Interrupt/Exception

January 9, 2015, 10:35 am
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Whenever I build my project in Nios II IDE I get this error :


make: Interrupt/Exception caught (code = 0xc0000005, addr = 0x403a39)


I think it has something to do with the PATH? how can I fix that ?
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make: Interrupt/Exception

January 9, 2015, 10:45 am
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Whenever I build my project in Nios II IDE I get this error :


make: Interrupt/Exception caught (code = 0xc0000005, addr = 0x403a39)


I think it has something to do with the PATH? how can I fix that ?
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Error with command env CL_CONTEXT_EMULATOR_DEVICE_ALTERA

January 9, 2015, 11:56 am
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I'm using emulation on Linux and run the application with the command "env = CL_CONTEXT_EMULATOR_DEVICE_ALTERA s5_ref vector_add" I get the following message:
"env: CL_CONTEXT_EMULATOR_DEVICE_ALTERA: File or directory not found"

Could anyone help me?
grateful!
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Altera monitor program error: Programming hardware cable not detected

January 9, 2015, 11:58 am
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I'm using Quartus 13.0 on a windowa 8.1 system.

I tried to compile a known working program In Altera Monitor Program and the error below is what I got:


Error: Programming hardware cable not detected. Make sure the hardware cable is properly connected to your device from the host computer.


Under Device manager it states the USB blaster is working properly. Is the issue software/file related?

Does anyone have any insight on this error? Please help soon.
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USB setup for Linux on Arrow Sockit

January 9, 2015, 1:22 pm
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I've installed the GSRD 14, I've built my FPGA core and I've got them communicating.

Next I need to get some keyboard input. So I bought a USB OTG to USB adaptor. I've plugged in the keyboard but Linux does not appear to recognise it. I see these in dmesg:
usbcore: registered new interface driver usbfsusbcore: registered new interface driver hub
usbcore: registered new device driver usb
usbcore: registered new interface driver usb-storage
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver

However the rest does not seem to be set up:
>lsusb
unable to initialize libusb: -99

>ls /dev/bus/usb
ls: /dev/bus/usb: No such file or directory



>ls /proc/bus/usb
ls: /proc/bus/usb: No such file or directory

I also see nothing in dmesg when connecting/disconnecting devices.

Should this work with the default kernel? Or do I need to build my own to get this working?

I saw other distributions with USB mouse/keyboard etc, though these seem to also need the FPGA side configured for video. I have my own FPGA side configuration.

Any tips greatly appreciated! I might go any try one of the 'full computer' style distributions to at least check my board/cable works in the meantime...
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need 32-bit patch for ModelSim-Altera Starter edition v14.1

January 9, 2015, 8:59 pm
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I just installed ModelSim-Altera Starter edition v14.1 on a 32-bit Windows platform. When I try to run it, it says that it can't find a license. I understand the the Starter edition is supposed to run without a license. The Download Center page refers to a patch, ModelSimSetup-14.1.0.186-windows.exe, which it says is supposed to fix this issue. I downloaded the patch but when I try to run it it says:
"The Altera software you are installing is 64-bit software and will not work on the 32-bit platform on which it is being installed."

Is there a 32-bit version of this patch?
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Adding two uint4

January 10, 2015, 1:48 am
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Hi, I'm struggling with adding int4 data. I want to be able to add two 96b numbers (what implies adding with carry) in my kernel and I came up with this code:
Code:
uint4 Add(uint4 a, uint4 b){
    ulong c[3] = {0};
   
    c[0] = (ulong)a[0]+(ulong)b[0];
   
    for(int i=1; i<3; i++){
        c[i] = (ulong)a[i]+(ulong)b[i] + (c[i-1]>>32);
    }
    return (uint4)(c[0],c[1],c[2],0);
}
However, I noticed that typecasting significantly increases my resource usage. I'd appreciate if anyone could help me with finding a better solution.
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Help with making an osciloscope on NIOS II

January 11, 2015, 2:52 pm
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Good day every one!
I would like to make a simple 6 channel, 250 kSa oscilloscope using NIOS II/f.
I am using DE0-NANO (Cyclone IV, 32 MB SDRAM) and I already have device built (6 channel ADC connected to SDRAM, pushbuttons, graphical LCD, some batteries).

Now main problem:
I wrote driver for my ADC and DATA is extracted by parallel ports.
My first attempt was to write data from 6 PIO to SDRAM using CPU (but as you can guess, this task was killing any other IRQ).
Later I was trying using DMA, SGDMA and mSGDMA to copy data from PIO to SDRAM, but without any success (I have spend so many hours on this... :evil: I hate myself).

What I would like to ask you is to help me find best way getting this data (10 000 samples per channel) into SDRAM.

Please help me with this matter, any guide will do.

Best Regards

Michael
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How to use Serial flash loader in Quartus II, (if already known please ignore it).

January 11, 2015, 10:40 am
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Hi All..
This is for beginner (like me), who are all interested to program serial(or) config devices via JATG.
I was searching for last couple of days.. difficult to found it, finally I was found that the step by step process..
I would like to share all the members to searching such a option. (I was found this procedure in the web link:http://quartushelp.altera.com/14.1/m...o_plf_file.htm)

The procedure is:
To program erasable programmable configurable serial (EPCS) devices with the Serial Flash Loader:
  1. Use the Assembler to generate an SRAM Object File (.sof) containing the FPGA configuration data.
  2. On the File menu, click Convert Programming Files.
  3. Under Output programming file, select JTAG Indirect Configuration File (.jic) in the list.
  4. In the Configuration device list, select the target configuration device you want to program.
  5. In the File name box, type the file name for the JTAG Indirect Configuration File you want to create.
  6. To specify an existing SRAM Object File for conversion to a JTAG Indirect Configuration File, select the SOF Data item under Input files to convert and click Add File.
  7. To specify the target FPGA device that will program the configuration device, select the Flash Loader item under Input files to convert and click Add Device.
  8. To generate the JTAG Indirect Configuration File containing configuration device programming data, click OK.
  9. On the Tools menu, click Programmer.
  10. If necessary, in the Mode list, select JTAG.
  11. To add the newly created JTAG Indirect Configuration File to the programming list, click Add File in the Programmer window and select the JTAG Indirect Configuration File.
  12. In the same row as the FPGA device in the programming list, turn on the Program/Configure option.
  13. In the same row as the configuration device in the programming list, turn on the Program/Configure option.
  14. To configure the FPGA device with the Serial Flash Loader IP and then program the configuration device, click Start in the Programmer.
  15. To reconfigure the FPGA device with configuration data from the configuration device, turn the power to the FPGA device off and on.

    Enjoy..

    thanks and regards..
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