Slack issue in dual clock FIFO

February 27, 2015, 2:09 pm

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Hi.
I have dual clk fifo in my project for Stratix V. Write clk - 250 MHz, read clk - 100 MHz. Fifo has aclr signal that is equal to wr_rst OR rd_rst. wr_rst is synchronous to 250 MHz, rd_rst is synchronous to 100 MHz. Fifo has following parameters:
.rdsync_delaypipe (4),
.wrsync_delaypipe (4)

.write_aclr_synch ("ON"),
.read_aclr_synch ("ON")
Adding them, I try to synchronize aclr with both clocks.
But TimeQuest reports about slack problems. It tolds that some fifo internal registers (rdptr, counters, etc.), clocked by 100 MHz, are violated with reset, clocked by 250 MHz. What can I do or can I ignore that slack?

Thanks.

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Multi-jtag server configuration

February 27, 2015, 5:33 pm

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We are starting to ramp up and deploy several development systems in our lab. The current count is now at 24 FPGA based systems, with an expected growth of 30 more by Q2/Q3 timeframe, and over 100 by EOY'15. To support this deployment, we need to move beyond 1 host (Quartus)<>1 Target (FPGA). We are using the USB Blaster cables currently (may switch to USB Blaster II if mechanical issues are resolved). In our current testing, we have deployed 4-5 target systems per jtag server. This works ok for automated programming of an FPGA and exiting, but falls flat when remote quartus A is programming FPGA 1, and remote quartus B is running a SignalTap debug session on FPGA 2 (we do not plan on having multiple quartus instances looking at 1 FPGA - not a very good support model anyways). Unfortunately, (from what we have experienced to date), jtagd (Linux) only supports 1 Quartus connection at a time (seeing and reporting multiple Blasters is not a problem).

One solution we were told about is to have the server run as a VM server, with each blaster controlled by an independent VM (USB pass-through). This is not desireable as it takes more IP addresses to support. Most of our quartus hosts are running in a VM, but we want to be able to dynamically allocate an FPGA target, and each user can own their own VM, requesting a target from the pool.

We need to get this functional ASAP. Any suggestions? We are willing to help with the development/testing of jtagd to support this functionality (which shouldn't be too difficult - it already exists in printer and scanner servers).

Tobin Davis
Lab Manager
Cloud Platform Technologies - Intel Corp.

Attached Images

• jtag-server.jpg (60.4 KB)

How to observe internal signals with ModelSim

February 27, 2015, 6:16 pm

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I’m using Quartus II. In FPGA design simulation, input and output signals can be observed. Sometimes, we do need to observe some internal signals. Please let me know how to do that.

Thanks,
xxlnm

FIR MegaCore Parameter Question

February 28, 2015, 1:50 am

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Hi,
I am trying to implement FIR MegaCore in my design, but I got confused about a parameter in the Mega Wizard.
If I am using the interpolation feature, with a factor of 8, does that mean the input sample rate (in the next pane)
is the original data input rate * interpolation factor? or I just input the original data rate?
For example: My original input rate is 175 Kbps, and I want to upsample the input by 8 then filter it, do I enter
175 Kbps as input sample rate? or I enter 175 Kbps * 8 = 1.4 Mbps?

Simulate FIR MegaCore IP with Verilog in ModelSim

February 28, 2015, 2:34 am

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I am trying to simulate the FIR MegaCore IP with Verilog test bench in ModelSim Altera Starter Edition.
I have generated the IP with Verilog as chosen language.
Generated simulation files and scripts include a VHDL test bench, the script works just fine when it comes to
the included VHDL test bench. However when I try to alter the script (msim_setup.tcl) to simulate my design with
my Verilog test bench, ModelSim says that it is unable to instantiate the IP and ALTERA version supports only one HDL.

Can you please tell me how to simulate this IP with my custom Verilog test bench?

Alternative to DE1 control panel?

February 28, 2015, 3:56 am

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As a lot of users here I have problems with the DE1 control panel. It exits with the error message "Please make sure Quartus is installed". The DE1 manual states that it has to be Quartus 12.0 or newer. I have 13.0sp1 on a 64Bit Windows 7. Sysinternals process monitor tells me that it can find the quartus bin directory and it loads the jtag_client.dll.
Before looking any further is there any other way to write the (external?) 4mb flash and/or the SRAM (quartus_pgm or with Quartus)?
Any examples would be highly appreciated.

Thanks,
Winni

having problem when Simulating Nios II with Program Memory on External Flash & SSRAM

February 28, 2015, 7:54 am

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I was following the tutorial on

HTML Code:

---

http://www.alterawiki.com/wiki/Simulating_Nios_II_Designs_with_Program_Memory_on_External_Flash_and_SSRAM

---

for Simulating Nios II with Program Memory on External Flash & SSRAM.
Eventually Modelsim shows folloing Error while trying to load the simulation files:

Quote:

---

# ** Note: (vsim-3812) Design is being optimized...
# ** Error: (vopt-7) Failed to open info file "work/_info" in read mode.
# No such file or directory. (errno = ENOENT)
# ** Error: ./..//niosii_system_tb/simulation/niosii_system_tb.v(103): Module 'niosii_system_tb_niosii_system_inst' is not defined.
# ** Error: (vopt-7) Failed to open info file "work/_info" in read mode.
# No such file or directory. (errno = ENOENT)
# ** Error: ./..//niosii_system_tb/simulation/niosii_system_tb.v(121): Module 'niosii_system_tb_niosii_system_inst_led_pio_exter nal_connection_bfm' is not defined.
# ** Error: (vopt-7) Failed to open info file "work/_info" in read mode.
# No such file or directory. (errno = ENOENT)
# ** Error: ./..//niosii_system_tb/simulation/niosii_system_tb.v(125): Module 'niosii_system_tb_niosii_system_inst_button_pio_ex ternal_connection_bfm' is not defined.
# ** Error: (vopt-7) Failed to open info file "work/_info" in read mode.
# No such file or directory. (errno = ENOENT)
# ** Error: ./..//niosii_system_tb/simulation/niosii_system_tb.v(150): Module 'niosii_system_tb_flash_ssram_tristate_bridge_brid ge_0_tcb_translator' is not defined.
# ** Error: (vopt-7) Failed to open info file "work/_info" in read mode.
# No such file or directory. (errno = ENOENT)
# ** Error: ./..//niosii_system_tb/simulation/niosii_system_tb.v(177): Module 'niosii_system_tb_flash_ssram_tristate_bridge_pinS harer_0_pin_divider' is not defined.
# Optimization failed
# Error loading design

---

and then I tried not to use optimization in IDE for ECLIPSE and then tried again I got verbosity_pkg Error:

Quote:

---

# Top level modules:# altera_tristate_conduit_bridge_translator
# Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013
# -- Compiling module altera_conduit_bfm_0002
# ** Fatal: Unexpected signal: 11.
# ** Error: C:/Users/Administrator/Desktop/Nios2_External_Memory/niosii_system/testbench/niosii_system_tb/simulation/submodules/verbosity_pkg.sv(48): Verilog Compiler exiting
# C:/altera/14.0/modelsim_ase/win32aloem/vlog failed.

---

I added this line to my Modelsim TCL but didnt work again:
vlog -sv niosii_system_tb.v -L altera_common_sv_packages
Anyone had the same problem befor?
Thanks in advance.

NAND Flash Booting

February 28, 2015, 9:50 am

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hello,

Am facing problem with NAND Flash booting. Am able to boot the preloader successfully using nand.
Am using S34ML01G1 NAND flash.
What i have done is:
1) I have placed preloader-mkpimage.bin file at 0x0 address of NAND.
2) then u-boot.bin file at 0xC0000 (which is the next boot address as in bsp settings).

Preloader is running fine, then the control is going to next boot address also, but u-boot is not executing fully. Its stopping inthe middle. Here is the snapshot of terminal window.



How can i solve the problem?

Can any of the following things solve my problem:
1) Enabling ECC for NAND, if yes, How to enable this.
2) Editing the values in socfpga_common.h file, what are the values for my NAND device?
3) By making "bootstrap_inhibit_init" to 0 in "boot strap settings" register. How can i do this?

Please help me out of this...

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ModelSim on data displayed for internal signals

February 28, 2015, 11:47 am

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In order to observe internal signals, I added internal signals in Modelsim, and then Run-All. But no data displayed in wave panel as attached image. Please let me know how to show the signals.

Thanks,
xxlnm

Attached Images

• Modelsim No data.jpg (106.5 KB)

About Parallel flash loader and CPLD

March 1, 2015, 5:15 am

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Hi,
I have a question about the Altera Parallel flash loader IP.
I have an Altera DE1 board and i have tested this IP with the embedded Flash memory in the DE1.
All works great, thanks for the AN386 docs.

I want to start a low cost project with juste one CPLD ( MAX II EPM 240 ) and a Spansion 8Mo Flash memory ( S29GL064).
According to the docs this memory is compatible.

Is it possible to use PFL for programming the Flash memory with JTAG connection over this low cost CPDL instead an FPGA ?

Thanks in advance

Quartus 12. --Analysis and Synthesis Failed- Help Needed

March 1, 2015, 5:15 am

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Hello here is a small program that I wrote in VHDL(please see attachment). Synthesis fails in Quartus with the following error.
Error[10028]: can&#39;t resolve multiple constant drivers for net wr_data[]...
Can someone help me with solve it?

Thanks.
Manoj

Attached Files

• New_1.vhd (4.2 KB)

Modelsim - Error loading design - vsim-3170 - could not find

March 1, 2015, 2:30 pm

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Hi there,

when i try to simulate my design, i receive the following msg:

vsim -gui "+altera" -l msim_transcript -do "FILENAME_run_msim_rtl_vhdl.do"
# Start time: 23:18:28 on Mar 01,2015
# ** Error: (vsim-3170) Could not find 'D:/####/simulation/modelsim/rtl_work.TOPLEVELMODULETESTBENCH'.
#
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./FILENAME_run_msim_rtl_vhdl.do PAUSED at line 19


I`m not sure, where exactly the problem is. I also checked the .do file, but didn`t recognize smth special. So anybody knows about this failure and could help?

Thanks a lot

regards

For Cyclone , hoe do I employ CB_P2A_AVALON_ADDR_B0 to get the BAR size == IP span

March 1, 2015, 5:36 pm

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Team,

I have seen documentation describing CB_P2A_AVALON_ADDR_B0 as an offset I believe do the BAR size will reflect the actual span and not the number of bits to reach the Avalon MM address range.

I tried editing that parameter in the RTL but it caught an error checker indicating it had to be set to zer.

Best Regards, Bob.

Onchip RAM Corrupted by Reset

March 1, 2015, 7:17 pm

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Hi,

I currently have a large system that I have been developing for the last year or so. Until now I have been uploading a sof file to the FPGA, and then using eclipse to upload Nios code to an instruction RAM. This has all been working fine.
It has now got to the point where I have embedded the Nios code in the sof file and converted it to a flash file for my Stratix V DSP Development board (5SGSMD5K2F40C2 FPGA). The trouble is, I am now having problems with the processors instruction RAM.

Essentially the system consists of two subsystems, a PCIe Application layer using the Av-ST Altera Hard IP for PCIe, and a User system which contains DDR3 RAM, a Nios Processor, some On-Chip RAM for data an instructions (one for each), and then a whole lot of other stuff. The DDR memory supplies the clock for the Nios processor and user system, and the PCIe core provides the clock for that subsystem.

When I cold boot the PC, the FPGA configures from the flash and DDR initialises. The PCIe core provides the soft reset signal to the DDR memory controller (UniPHY in Qsys). In this scenario, the user system comes out of reset once the PCIe core is ready.
This is all working fine. PC boots up and Nios processor starts blinking an LED (there is another LED that blinks when the DDR controller is out of reset). Everything is good.

If I then restart the computer, the PCIe core is reset by the PC which in turn soft resets the DDR controller and hence the User system. As soon as this happens, the Nios processor stops blinking its LED. I know that everything is out of reset as the LED showing a the system is out of reset resumes blinking.

If I use System Console from eclipse and download the contents of the instruction RAM, I can see that the first few bytes of it, which also happens to be the reset vector, and a few bytes in other places near the end of the RAM, have all been corrupted. It's no wonder the processor doesnt boot.

I saw on the Altera support website that there is a knowledge base article on this type of thing, saying asynchronous resets can corrupt M20K contents, but that article related to Quartus 13.1, and said it would be fixed in 13.1sp1. But I am using Quartus 14.0. I also made sure to select the option in Qsys to enable the reset_request option on the on-chip RAM.


Is there any way to avoid this corruption? I don't want to set the instruction RAM to be a ROM as I will still need to be able to reprogram it from eclipse without recompiling.

Inferacing of fpga and atom processor

March 1, 2015, 9:41 pm

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I am using DE2i-150 board.I want to use the atom processor only. I don't want to use the fpga processor(Nios-II). Is onchip_mem.hex file required for that case? Do I need to incorporate a clock(altpll/altgx/altgx-reconfig)? Please help.

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.elf file in NIOS II SBT tool

March 1, 2015, 9:44 pm

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Hi, in our college we planned to purchase Quartus II software . So we were doing a project in designing a Nios II soft core processor with Quartus II 14.1 version.
After creating Qsys we have done complete compilation in Quartus II with no errors.But we stucked at using SBT tool since it showing error as project does not have an ELF file.

DS-5 Baremetal:Failed to load image

March 2, 2015, 2:51 am

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Hi,

I'm running a baremetal application to write and read a byte of data into the DDR memory. The attached image shows the configuration of the DS-5 debugger being used.

The error log is as shown:
Stopping running target Altera - Cyclone V SoC (Dual Core) on TCP:localhost on connection
Connected to running target Altera - Cyclone V SoC (Dual Core) on TCP:localhost
Execution stopped at: S:0x3FF84E5C
source /v "D:\Altera\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check .py"
S:0x3FF84E5C LDR r3,[pc,#188] ; [0x3FF84F20] = 0xFF706FFF


No SYSID registers could be found. Has a peripheral description file been supplied?


source /v "D:\Altera\projects\system\software\spl_bsp\preloa der.ds"
+stop
WARNING(CMD315): Target is not running
+wait 5s
+reset system
+wait 5s
+set semihosting enabled 0
+loadfile "$sdir/uboot-socfpga/spl/u-boot-spl" 0x0
Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF7AE3 (size 0x7AE4)
Loaded section .rodata: S:0xFFFF7AE4 ~ S:0xFFFF9D7B (size 0x2298)
Loaded section .data: S:0xFFFF9D80 ~ S:0xFFFFAC53 (size 0xED4)
Entry point S:0xFFFF0000
Target has been reset
Execution stopped due to a breakpoint or watchpoint: S:0x00000000
S:0x00000000 LDR pc,[pc,#24] ; [0x20] = 0xA8
+set debug-from *$entrypoint # Set start-at setting to address of $entrypoint
+start
Reloading program
Starting target with image D:\Altera\projects\system\software\spl_bsp\uboot-socfpga\spl\u-boot-spl
Running from entry point
Execution stopped at: S:0xFFFF0000
In start.S
S:0xFFFF0000 39,0 _start: b reset
+delete
All user breakpoints deleted
+tbreak spl_boot_device
Breakpoint 2 at S:0xFFFF2084
on file spl.c, line 71
on file spl.c, line 81
+cont
+wait 60s
ERROR(CMD360):
# in D:\Altera\projects\system\software\spl_bsp\preload er.ds:46 while executing: wait 60s
! Wait for stopped timed out
ERROR(CMD656): The script D:\Altera\projects\system\software\spl_bsp\preload er.ds failed to complete due to an error during execution of the script
loadfile "C:\Users\Administrator\Documents\DS-5 Workspace\app_test\Debug\app_test.axf"
ERROR(CMD16-TAD11-NAL33):
! Failed to load "app_test.axf"
! Failed to write 8 bytes to address N:0x00117748
! Target is running, cannot access.
cd "C:\Users\Administrator\Documents\DS-5 Workspace"
Working directory "C:\Users\Administrator\Documents\DS-5 Workspace"
set debug-from main
start

Sometimes upon reload, I get this warning(s):
WARNING(CMD399-COR168):
! Failed to start the target
! No function named "main" could be found
WARNING(CMD407): Trying the entry point instead



WARNING(CMD452-COR167): ! Breakpoint 3 has been pended! No compilation unit matching "C:/Users/Administrator/Documents/DS-5 Workspace/app_test/Debug/test.c" was found

Am I missing anything in the configuration? Is there any specific jumper settings? I suspect the problem is initialization of the memory but not completely sure on it.
Please advice on this issue. Thanks in advance.

Best Regards,
Nitin.

Attached Images

• debug_config.jpg (221.6 KB)

DS-5 Baremetal:Failed to load image

March 2, 2015, 2:53 am

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Hi,

I'm running a baremetal application to write and read a byte of data into the DDR memory. The attached image shows the configuration of the DS-5 debugger being used.

The error log is as shown:
Stopping running target Altera - Cyclone V SoC (Dual Core) on TCP:localhost on connection
Connected to running target Altera - Cyclone V SoC (Dual Core) on TCP:localhost
Execution stopped at: S:0x3FF84E5C
source /v "D:\Altera\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check .py"
S:0x3FF84E5C LDR r3,[pc,#188] ; [0x3FF84F20] = 0xFF706FFF


No SYSID registers could be found. Has a peripheral description file been supplied?


source /v "D:\Altera\projects\system\software\spl_bsp\preloa der.ds"
+stop
WARNING(CMD315): Target is not running
+wait 5s
+reset system
+wait 5s
+set semihosting enabled 0
+loadfile "$sdir/uboot-socfpga/spl/u-boot-spl" 0x0
Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF7AE3 (size 0x7AE4)
Loaded section .rodata: S:0xFFFF7AE4 ~ S:0xFFFF9D7B (size 0x2298)
Loaded section .data: S:0xFFFF9D80 ~ S:0xFFFFAC53 (size 0xED4)
Entry point S:0xFFFF0000
Target has been reset
Execution stopped due to a breakpoint or watchpoint: S:0x00000000
S:0x00000000 LDR pc,[pc,#24] ; [0x20] = 0xA8
+set debug-from *$entrypoint # Set start-at setting to address of $entrypoint
+start
Reloading program
Starting target with image D:\Altera\projects\system\software\spl_bsp\uboot-socfpga\spl\u-boot-spl
Running from entry point
Execution stopped at: S:0xFFFF0000
In start.S
S:0xFFFF0000 39,0 _start: b reset
+delete
All user breakpoints deleted
+tbreak spl_boot_device
Breakpoint 2 at S:0xFFFF2084
on file spl.c, line 71
on file spl.c, line 81
+cont
+wait 60s
ERROR(CMD360):
# in D:\Altera\projects\system\software\spl_bsp\preload er.ds:46 while executing: wait 60s
! Wait for stopped timed out
ERROR(CMD656): The script D:\Altera\projects\system\software\spl_bsp\preload er.ds failed to complete due to an error during execution of the script
loadfile "C:\Users\Administrator\Documents\DS-5 Workspace\app_test\Debug\app_test.axf"
ERROR(CMD16-TAD11-NAL33):
! Failed to load "app_test.axf"
! Failed to write 8 bytes to address N:0x00117748
! Target is running, cannot access.
cd "C:\Users\Administrator\Documents\DS-5 Workspace"
Working directory "C:\Users\Administrator\Documents\DS-5 Workspace"
set debug-from main
start

Sometimes upon reload, I get this warning(s):
WARNING(CMD399-COR168):
! Failed to start the target
! No function named "main" could be found
WARNING(CMD407): Trying the entry point instead



WARNING(CMD452-COR167): ! Breakpoint 3 has been pended! No compilation unit matching "C:/Users/Administrator/Documents/DS-5 Workspace/app_test/Debug/test.c" was found

Am I missing anything in the configuration? Is there any specific jumper settings? I suspect the problem is initialization of the memory but not completely sure on it.
Please advice on this issue. Thanks in advance.

I am using a Cyclone V Arrow SocKit with Quartus 14.1 edition. The preloader and uboot were generated through the bsp-editor after the system was generated through Qsys.

Best Regards,
Nitin.

Attached Images

• debug_config.jpg (221.6 KB)

Problem with fifo API (How to use fifo correctly)

March 2, 2015, 3:03 am

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Good day! I collect my system using: nios nco, fir and cic filters. In my case I use dsp-processor for control nco. NCO require AvST bridge, so I decided to use fifo between nios and nco.
First, I decided to make such system: NIOS, which store code frequency for nco (32 bits word), when fifo (I use it like a bridge AvMM-AvST) and second fifo (as bridge AvST-AvMM). In this system I want to write one word to fifo and read it, but have some problems and also simulate it in Modelsim.
But I have some problem - you can see my word didn't read/write via fifo. I suggest there are some problem in the code - may be I didn't adjust fifo correctly.
I use fifo's API:
1) altera_avalon_fifo_init – init fifo
2) altera_avalon_fifo_write_fifo – write to fifo
3) altera_avalon_fifo_read_fifo – read from fifo

My code:

Code:

---


/*
 * main.c
 *
 *  Created on: 26.02.2015
 *      Author: Roman
 */
//Includes
#include "io.h"
#include "altera_avalon_fifo_regs.h"
#include "altera_avalon_fifo_util.h"
#include "system.h"
#include "sys/alt_irq.h"
#include <stdio.h>
#include <stdlib.h>
#define ALMOST_EMPTY 2
#define ALMOST_FULL FIFO_0_IN_CSR_FIFO_DEPTH-3




int main(){
    //reset the fifo's irq history register
    altera_avalon_fifo_clear_event(FIFO_0_IN_CSR_BASE,
                                  ALTERA_AVALON_FIFO_EVENT_ALL);








    //First FIFO (AvMM - AvST)
    int b = 0xab;
    //initializes the FIFO wr
    altera_avalon_fifo_init(FIFO_0_IN_CSR_BASE,            //the base address of the FIFO control slave
                            0,                            //the value to write to the interruptenable register
                            ALMOST_EMPTY,                //the value for the almost empty threshold (порог) level
                            ALMOST_FULL);                //the value for the most full threshold  level


    //write a, b into fifo


    altera_avalon_fifo_write_fifo(FIFO_0_IN_BASE,            //the base address of the fifo write slave
                                FIFO_0_IN_CSR_BASE,        //the base address of the fifo control slave
                                b);                        //value to write to address


    //read a,b from fifo
    altera_avalon_fifo_read_fifo(FIFO_0_IN_BASE,            //the base address of the fifo read slave
                                FIFO_0_IN_CSR_BASE);        //the base address of the fifo control slave


//Second FIFO (AvST - AvMM)


        //initializes the FIFO
        e = altera_avalon_fifo_init(FIFO_1_IN_CSR_BASE,            //the base address of the FIFO control slave
                                0,                            //the value to write to the interruptenable register
                                ALMOST_EMPTY,                //the value for the almost empty threshold (порог) level
                                ALMOST_FULL);                //the value for the most full threshold  level


        //write d into fifo


        g = altera_avalon_fifo_write_fifo(FIFO_1_OUT_BASE,            //the base address of the fifo write slave
                                    FIFO_1_IN_CSR_BASE,        //the base address of the fifo control slave
                                    d);                        //value to write to address


        //read e,f from fifo
        h = altera_avalon_fifo_read_fifo(FIFO_1_OUT_BASE,            //the base address of the fifo read slave
                                        FIFO_1_IN_CSR_BASE);        //the base address of the fifo control slave





    return 0;
}




---

I will glad to hear all your advices.

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• qsys.jpg (387.0 KB)

Loan IO in Qsys/Quartus 2

March 2, 2015, 4:57 am

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Hello everybody,

I am currently building a soft processor system on Altera DE1-SoC Cyclone V board. For my system to work as intended it must have access to the SD card slot and to the external uart-usb port, but seeing those two elements are situated on the HPS part of the chip, as opposed to the FPGA part where my processor is, I have encountered some problems.

I would like to know what exactly are the steps to access this pins. I suppose the way to go is through "loan IO" in QSYS but I do not fully understand what I am to do to make it work as intented (I am a begginer with DE1,Quartus II and QSys ).(I am using Quartus II 14.1)

I got from http://www.alteraforum.com/forum/showthread.php?t=44486 the basics of it but it still does not work.

-Is the memory conduit in the hps block in qsys needed and if so, how must it be connected seeing I do not really have use for it.

-For example if I want to access UART-usb pins (by bypassing everything in HPS , because my uart controller is on the FPGA part) is the correct procedure in QSys to add a HPS block(set all controllers to unused), create the correct loan IO lines and export hps_io, h2f_loan_io and memory conduits. When you get the HDL you put it in your block design file and connect it. Is this it or am I missing something? Must I maybe add an UART block in Qsys or is that only if I want to use the integrated(hard logic) uart controller?

-After I generate a HDL in QSys I must run a bunch of TCL scripts which automatically connect my outputs and inputs to correct pins. Is this correct? Otherwise there is no way I could connect my LOAN IO pins, as pin planner will not let me.

-Clock. I have a global clock running my FPGA system. Is the correct procedure to connect the same clock to the created Qsys HDL symbol?


Anyhow my goal is simply to grab the wires that connect directly to SD and Uart-usb, and completely nothing inbetween, no controllers, no buffers, no nothing.

Thanks in advance. Any kind of help will be appreciated.

Best regards