Hi I am looking for some help achieving timing closure in a design.
I am using a TI ADS4149 EVM Board and connecting it to a Terasic C5 SoC Dev Board.
The ADC outputs Source Synchronous DDR LVDS Centre Aligned data. I am capturing data from the ADC using a DDIO register in the FPGA. I take the clock output from the ADC and using a pll in source synchronous mode connect it to clock the ddio register. The sampling frequency for the ADC is currently at 160MHz but I am looking to push this up to as near to 250MHz as I can.
I have constrained my design using:
Code:
#create virtual clock latching data @ source
create_clock -name vir_clk_adc -period 6.250
#create clock that is received @ pin (90 degree shift)
create_clock -name clk_adc -period 6.250 -waveform {1.563 4.688} [get_ports {HSMC_CLKIN}]
#create generated clock output from pll
create_generated_clock -name clk_adc_pll -source [get_pins {adc_lvds_pll|pll_lvds_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[*]}] [get_pins {adc_lvds_pll|pll_lvds_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
derive_clock_uncertainty
# set input constraint using setup and hold wrt virtual clock
# max = Tperiod/4 - Tsu
# min = Th - Tperiod/4
set_input_delay -clock vir_clk_adc -max 0.463 [get_ports {HSMC_RX[*]*}]
set_input_delay -clock vir_clk_adc -min -1.163 [get_ports {HSMC_RX[*]*}]
set_input_delay -clock vir_clk_adc -max 0.463 [get_ports {HSMC_RX[*]*}] -clock_fall -add_delay
set_input_delay -clock vir_clk_adc -min -1.163 [get_ports {HSMC_RX[*]*}] -clock_fall -add_delay
#false path double data rate edges
set_false_path -setup -rise_from {vir_clk_adc} -fall_to {clk_adc_pll}
set_false_path -setup -fall_from {vir_clk_adc} -rise_to {clk_adc_pll}
set_false_path -hold -rise_from {vir_clk_adc} -rise_to {clk_adc_pll}
set_false_path -hold -fall_from {vir_clk_adc} -fall_to {clk_adc_pll}
When I perform timing analysis I am getting setup and hold violations on paths from the RX Pins to the DDIO register. (please see attached jpegs)
I am looking to close timing and am stuck as to what to do next.
Analysing the waveforms they look to have the correct relationship. There are no large interconnect delays, the DDIO has a large cell delay but I dont believe I can change this?
Analysing the data arrival path for the setup of the top failing path, the data is received at the pin, goes through an IO buffer into the DDIO cell, I cant affect this path as far as i am aware. looking at the data required path the clock is received at the pin, goes to the PLL onto a global clock and then to the DDIO pins. Looking at the hold path (it is for a different pin but they are all essentially the same) the data arrival and data required paths are the same as the setup.
I dont know what I can do to achieve timing closure. Assuming my constraints are valid (please let me know if not) and as far as I can tell my design is about as simple as it can get, what would be the next step? The only option that I have is to remove the PLL which I am going to test next.
Help would be appreciated
Thanks
James