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real time object tracking (need your help)

March 3, 2015, 3:50 pm
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hello EVERYONE,
so I'm A BEGINNER TO THE EMBEDDED SYSTEM FIELD AND I'll be working on a big project which is similar to the project in these links https://www.youtube.com/watch?v=QReo_zKjbL8 and https://www.youtube.com/watch?v=EuOeBHqmt5M
but the difference is that i want to use a touch screen so i can pick the object to be tracked among other objects.
so there will objects with different colors moving and i want the camera to track the object that i choose by touching its place on the screen.

I know this project is gonna be difficult to do (due to my lack of knowledge in the field and its complexity) but i'm very enthusiastic to do it.
please answer any of my questions here.
1- what is the best suitable fpga board for such a project?
2- what touch screen can use and how to interface to the fpga board?
3- do I need a microcontroller to run the servos or can I just use the fpga to do that?
4- what other hardware and interfaces you think will be needed for this project? what i know so far is that ill need
a high speed camera, camera link, fpga board, 2 servos and a touch screen
5- how can power the entire system?

and please refer me to any research or website that would help me in this project and throw any piece of info that may help writing the code
your help is very appreciated.
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IP Catalog can't be open

March 3, 2015, 7:19 pm
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I have installed Quartus II 14.1.1 build 190 for WINDOWS version. After installation, "IP Catalog" can not be opened.
Anybody know the possible reasons for this?
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Slow response when debugging software

March 3, 2015, 8:57 pm
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I use a cyclone IV custom board and use the NIOS ii soft processor. My question is when I step over a variable operation, i have to wait for 1 to 2 seconds, when I step over a function, I have to wait for 3 to 6 seconds to wait the run cursor to move to the next line. and sometimes when I step over a variable, it jumps to near by code line and then jump back. Is that normal?

my computer is a thinkpad x230(i7-3520M, 8G RAM 256g SSD), I think it is fast enough for debugging software, and the software is windows 7 64bit + quartus 14.1. the NIOS II soft processor run at 100MHz. and I use on-chip memory. I use the "Nios II 14.1 Software Build Tools for Eclipse" to debug software. I have tried DE0-nano kit, and DE1-SOC kit, the demonstrations project. It is the same, very slow response, have to spend a lot of time on debugging software. Is this normal? Can I easily do something to improve debug speed?
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Please help. Basic problem: Assigning pins

March 3, 2015, 9:43 pm
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Hi,

I'm trying to assign pins to my DE0. I want to use sw[0] for an input, which is supposedly Pin_J6. Only when I go on assignment editor and try to assign one of my inputs as Pin_J6, that is not one of the choices under "location" in pin planner. In fact it seems like I can't use any of the switches/buttons. I'm using Quartus 13.1. The design compiled okay and I programmed it on my board but now I want to assign the input. Please help. Thank you.
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DE2-115 USB example problems

March 4, 2015, 8:42 am
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I'm trying to run the DE2_115_NIOS_HOST_MOUSE_VGA example but in the c code from the nios II there is an error, in the line


IOWR(CY7C67200_BASE,HPI_MAILBOX,0xCE01);

Symbol 'CY7C67200_IF_0_BASE' could not be resolved
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implementation of don't care

March 4, 2015, 12:30 pm
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Say I was given a function for four variables
f= product of maxterms(3,11,14)+ D(0,2,10,12)

The function's least cost implementation is x1+x2'+x3'
However, this does not take into don't care signals; is there any way to specify those signals?
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assignment_group usage in SDC

March 4, 2015, 1:41 pm
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I am trying to use assignment groups to simplify my SDC file. But I am having problems getting them to work.

I have SDC code as follows (simplified obviously, the group will eventually add additional wildcard patterns in):
Code:
assignment_group "test" -remove ;# need this to avoid iterative workflow continually appending to the group
assignment_group "test" -add_member data_out\[*\]
set_multicycle_path -setup    -from "test" -to $main_clk 2
However when I load the SDC file, Timequest throws the following warning:
Warning: Ignored assignment set_multicycle_path
Warning: Argument -from with value test could not match any element of the following types: ( clk kpr reg port pin cell partition )

From what I can tell I am following Altera's example, but it is being ignored. An example from Altera's documentation is as follows:
Code:
assignment_group  "src_group" -add_member reg1
assignment_group  "src_group" -add_member reg2
set_multicycle_assignment 2 -setup -from "src_group"
for reference, the following code works correctly as I would expect:
Code:
set_multicycle_path -setup -from [get_keepers data_out\[*\]] -to $main_clk 2
I have several wildcard patterns that I want to apply this same constraint to and I really don't want to have to copy/paste this line every time due to the potential for errors it has. Additionally this group will have some other constraints applied and again I want to have the list present in a single location and then reference that list in all the various constraints that need it.

Thank You.
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linux kernel coredump...

March 4, 2015, 6:10 pm
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Mr Kazu:
Hi.
I'm sorry that issue of nios2-download command is not clear.
The methord of making​ nios2-download command run well is to use the 1 core instead of 4 cores. The proj 'DE2_115_NIOS_HOST_MOUSE_VGA' was modeled on 'NiosII_Quad_Core' with the same components & their addresses. so the nios2-download command works fine. When the linux kernel Image was downloaded, I program the NiosII_Quad_Core.sof to the DE2-115 board.4 cores with mmu +adaptor could read the kernel from the flash and work well.
I forget that I have changed the reset vector of the boot cpu in the proj 'NiosII_Quad_Core' to boot cpu from the flash instead of memory_monitor according to your web site. Is it right?
So the core dumped contents are the same for both 'nios2-terminal < linux.initramfs.srec' and 'nios2-download -g zImage'. Could you give some clue ?Thank you.
Code:
  │ │        NiosII FPGA configuration (CUSTOM_FPGA)  --->                │ │ 
  │ │    [*] HW mul support                                              │ │ 
  │ │    [*] HW mulx support                                              │ │ 
  │ │    [*] HW div support                                              │ │ 
  │ │    (0x10000000) Offset address for uImage.flash                    │ │ 
  │ │    [*] Passed kernel command line from u-boot                      │ │ 
  │ │    (0x00500000) Link address offset for booting                    │ │ 
  │ │    [ ] GPIO interface                                              │ │ 
  │ │    < > Enable NiosII PIO driver                                    │ │ 
  │ │    [*] Symmetric multi-processing support                          │ │ 
  │ │    (4)  Maximum number of CPUs (2-32)                              │ │ 
  │ │    [*] Use Multicore Adapter for SMP support
Code:
r1:  c026ec90 r2:  c0354000 r3:  c0354000 r4:  c0354000
r5:  00000001 r6:  00000000 r7:  00000000 r8:  00000000
r9:  00000008 r10: 00000171 r11: c035aacc r12: c0356a3c
r13: c0356a40 r14: ffffffe4 r15: c020d81c
ra:  c026f520 fp:  deadbeef sp:  c025ef9c gp:  deadbeef
ea:  c026f614 estatus:  00000000
Unaligned access from kernel mode, this might be a hardware
problem, dump registers and restart the instruction
  BADADDR 0xdeadbf0f
  cause  7
  op-code 0xb800283a
kindly regards
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Need help making Merging Unit.

March 4, 2015, 7:31 pm
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Can any one help me with Faraday law, need to make circuit to detect and calculate phase deflection of light signal send through fiber optical.
My main focus is on Faraday's laws of electromagnetic induction.

Any one with suggestions........
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Which nios version to use with mSGDMA

March 4, 2015, 8:19 pm
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I am trying to use the economy nios with the mSGDMA to save streaming data to SDRAM on the DE0-Nano board. Should I be using the standard or fast nios instead. I am not able to get data to even begin saving to SDRAM.

The code writes descriptors to the dispatcher, and then the dispatcher fifo fills up and no new descriptors can be written. To me it seems that the descriptors are not being executed. I tried using the standard and extended versions of the dispatcher. Neither writes the streaming data to SDRAM. I've tried using Burst and Stride options in the extended dispatcher, they don't work either.

Let me know what I am doing wrong or if this is related to the nios set up (i am using /e). It seems I'm missing something fundamental but I can figure out what...

Thanks.

My qsys set up is as follows:

Transfer mode: streaming to memory
Descriptor fifo: 32

Data width: 32
Length width: 20
FIFO depth: 64
Burst Enable: on
Maximum Burst Count: 16
Force Burst Alignment: on
Full Word Access Only

Here is a snippet of my code:

alt_ic_isr_register (MODULAR_SGDMA_DISPATCHER_CSR_IRQ_INTERRUPT_CONTRO LLER_ID, MODULAR_SGDMA_DISPATCHER_CSR_IRQ, sgdma_complete_isr, NULL, NULL); // register the ISR
enable_global_interrupt_mask(MODULAR_SGDMA_DISPATC HER_CSR_BASE);
reset_dispatcher(MODULAR_SGDMA_DISPATCHER_CSR_BASE );
start_dispatcher(MODULAR_SGDMA_DISPATCHER_CSR_BASE );
write_address = DATA_DESTINATION_BASE;

//This sets up the dispatcher.

//next in a do while loop...

alt_dcache_flush_all();


while ((RD_CSR_STATUS(MODULAR_SGDMA_DISPATCHER_CSR_BASE) & CSR_DESCRIPTOR_BUFFER_FULL_MASK) != 0)
{
printf("fifo full");
} // spin until there is room for another descriptor to be written to the SGDMA


control_bits = (sequence_field == test_end - 1) ? DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK : (DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_MASK | DESCRIPTOR_CONTROL_ERROR_IRQ_MASK);
construct_standard_st_to_mm_descriptor(a_descripto r_ptr,(alt_u32 *)write_address,0xFFFFFFFF,control_bits);


printf("0x%lx\n",sequence_field);
//increment 16kB address:
write_address = write_address + MAXIMUM_BUFFER_SIZE;
sequence_field++;


if (write_address > RAM_SPAN + RAM_BASE_ADDRESS){
write_address = DATA_DESTINATION_BASE;
}




if(write_standard_descriptor(MODULAR_SGDMA_DISPATC HER_CSR_BASE, MODULAR_SGDMA_DISPATCHER_DESCRIPTOR_SLAVE_BASE, a_descriptor_ptr) != 0)
{
printf("Failed to write descriptor 0x%lx to the descriptor SGDMA port.", sequence_field);
return 1;
}
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How to work with the 1080i50 incoming video cyclone III + BITEC

March 4, 2015, 8:35 pm
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how to use wildcard character in Node name of Pin-Planner

March 4, 2015, 10:46 pm
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In Pin-Planner, I want to use wildcard to represent the node names listed below. How should I do?
dp1_rx_dp[0],dp1_rx_dn[0],
dp1_rx_dp[1],dp1_rx_dn[1],
dp2_rx_dp[0],dp2_rx_dn[0],
dp2_rx_dp[1],dp2_rx_dn[1],

Should it be "dp*_rx_d*[*]" ?

Where can I find a complete document for how to use wildcard character in Quartus II?
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I/O pins located in a block

March 5, 2015, 2:48 am
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Hello,

I have a very simple problem :
I would like to map some of the I/O pins of the FPGA, which are connected to a wide external bus (hsma_d[75..0]) on a commercial board, to an internal bus (AD_A[13..0], AD_B[13..0], ...)

thus, for an example, I connected just by maping inside a .brd file, the data coming from and tha ADC bus on the HSMA connector to the DAC bus on the same HSMA connector (but other pins obviously). the project compilation is fine and I am able with a generator and a scope, to compare the signal sent to the ADC with the one obtained from the DAC.
thus the principle is OK.

then, I would like to hide this I/O pins maping inside blocks to avoid to show all these pins at the top level, which is not a very interesting information.
then I create a block in which I make exactly the same maping and I connect this block at the top level.
the advantage is, from the top level, one sees only boxes (ADC, DAC, ...) with a "clean" bus (only one wire) and not plenty of pins.
BUT in this case, quartus is not able to properly connect the I/O pins declared inside the blocks despite the fact that the assignment editor seems happy (all status ar OK).

then my questions are :
is it possible in quartus to use I/O pins of the FPGA directly in blocks ?
and if yes, how to do that properly ?

thank you for your help

best regards

ronic
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Problem simulating transceiver megacore Nativelink

March 5, 2015, 5:12 am
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I am new to Altera Megacores and am having trouble simulating a VHDL project using Altera Megacores in the web edition of Quartus/ Modelsim-Altera. I am trying to use Nativelink so I do not have to get involved with the details of the MegaCore files and libraries for the moment.

I am using Quartus II 64 Bit Version 14.1.0. Build 12/03/2014 SJ Web Edition.

I have connected a Cyclone V Transceiver Native PHY, Transceiver PHY Reset Controller and Transceiver Reconfiguration controller produced from the IP Catalogue together in a schematic then generated an HDL file from the schematic.

I set up the simulation tab in "Settings/EDA Tool Settings" to compile a test bench generated from a template using Quartus.

The design compiles without error but when I run RTL simulation from Quartus the test bench is not bound to the components it uses so all of their signals are undefined.

I realise I am probably making some silly error and would be very grateful for any help.

I attach the archived project.

Resolved - changed the EDA netlist setting from VHDL to Verilog HDL and it seems to be working now.
Attached Files
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FIR and CIC MegaCores Altogether

March 5, 2015, 6:42 am
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Hi,
I have instantiated FIR II MegaCore as a Pulse-Shaping and upsampling by 8 filter, now I want to use CIC MegaCore
after FIR to interpolate the signal... I didn't use Back Pressure feature in FIR.
Simulation shows that signal is not interpolated... almost the same. In the generated test bench of the CIC IP, I noticed that input is allowed only
when "in_ready" signal is high... when it's low the input is kept hold.
I tried to do the same thing using Back Pressure feature in FIR IP, but because ModelSim doesn't allow mixed-HDL simulations
(what a shame!) I couldn't verify. So, I used SignalTap instead... plotting the result on MATLAB shows a completely
distorted signal!

So... How do I use CIC along with FIR MegaCore? Can you please provide an example?
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Sending Data from PC to Nios 2 System

March 5, 2015, 6:50 am
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May I know is there any possible way to send data from PC host to Nios 2 system within FPGA (DE2 board)?
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CycloneV HPS SDRAM MemoryController pipelined variable waitrequest and readdatavalid

March 5, 2015, 7:15 am
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from what i understand, HPS SDRAM Memory Controller can never be non pipelined. simply because your fpga frequency will always be slower than DDR3 IC, this memory controller has to pipeline data to translate it from higher frequency to lower frequency to let the master side(fpga) send and receive data. this takes us to the read data valid and wait request signals; and to the fact that there always will be a variable latency to these signals. so now imagine, that your boss asks you to find out how much data cyclone v transfers to the ddr in every second; if your fpga project has base frequency of 50mhz. what would you answer? you never know when read data valid becomes high. you never know when waitrequest becomes high and how long it stays. these signals always vary in length according to surrounding circumstances... it leaves the impression that pipelined transactions are not designed for strictly timing fixed projects. where, let's say an fpga has to send 2kb every 2us... what if waitrequest stays high for some cycles; then fpga will finish the transfer in 2us + waitrequest cycles. how can it be acceptible to everyone... is there any way to fix waitrequest and readrequest to some fixed number of cycles? i am trying to use cyclone v HPS sdram memory controller
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altera_avalon_dma stuck in BUSY state on transfers larger than 0x7F8 ...

March 5, 2015, 1:32 pm
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1. Transaction length (write from EP to RC) work only up to size of 0x7F8 bytes.
a. When issuing length larger than that, the DMA is “stuck” with “BUSY” on, and length does not decrement.
b. Did you get transfers with length larger than 0x7F8 bytes? If not, can you please try?
c. When examining the *.qar file you’ve sent, seems like maximal length of 8191 bytes should be supported (13 bits),


I have attached the settings and it says something interesting that it may be adjusted to match the size of the target slave.

I know I need to run simulation on this and see what happens when I adjust the length to the failing length but sim may take some time . Else I can scale the problem down to see what occurs. Since the max count is 13 bits ... 8192 ( 0x2000 ).

Since this has to be very mature IP, can someone point me to the Knowledge Database for this IP ?

Thanks, Bob.
Attached Images
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Cyclone V native transceiver IP compile error , please help me,thanks!

March 5, 2015, 6:05 pm
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when i use CycloneV native transceiver IP core, the function simulation is OK.But when i put the IP into my project and compiling the project,there will be some errors. The release of quartus is 13.1,the error message list blow,please help me to see how i fix these?

Error: HSSI PMA TX Buffer node 'xcvr_native_phy_ip cvr_native_phy_ip_inst|altera_xcvr_native_sv
cvr_native_phy_ip_inst|sv_xcvr_native
en_native_inst.xcvr_native_insts[0].gen_bonded_group_native.xcvr_native_inst|sv_pma:i nst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_p ma_ch:tx_pma_insts[0].sv_tx_pma_ch_inst|tx_pma_ch.tx_pma_buf.tx_pma_buf ' is not properly connected on the 'DATAOUT' port. It must be connected to one of the valid ports listed below.

Info: Can be connected to I port of stratixv_io_obuf WYSIWYG
Error: Input port REFIQCLK0 of xcvr_native_phy_ip cvr_native_phy_ip_inst|altera_xcvr_native_sv
cvr_native_phy_ip_inst|sv_xcvr_native
en_native_inst.xcvr_native_insts[0].gen_bonded_group_native.xcvr_native_inst|sv_pma:i nst_sv_pma|sv_rx_pma:rx_pma.sv_rx_pma_inst|rx_pmas[0].rx_pma.cdr_refclk_mux0 atom must be connected when parameter cdr_refclk_select is set to 'ref_iqclk0''
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basic questions

March 5, 2015, 8:41 pm
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Hi everyone,

I'm having trouble with the code I posted below. I'm trying to design an ALU and am having conceptual problems.

Seems like for the case when sel is "1000" I get errors saying I need to use :=

I'm actually very confused about the difference between <= and := . Could someone please explain the difference?

In any case neither <= or := works with my code it seems.

Furthermore could someone explain to me the difference between std_logic_vectors and signed/unsigned numbers?

Also for the case when sel is "0010" is it okay for me to make the following comparison:
unsigned(temp) > (2**WIDTH)-1

Thank you

--------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity alu_ns is


generic (
WIDTH : positive := 16
);


port (
input1 : in std_logic_vector(WIDTH-1 downto 0);
input2 : in std_logic_vector(WIDTH-1 downto 0);
sel : in std_logic_vector(3 downto 0);
output : out std_logic_vector(WIDTH-1 downto 0);
overflow : out std_logic
);


end alu_ns;


architecture alu_arch of alu_ns is
begin


process(input1, input2, sel)
variable temp : std_logic_vector(WIDTH-1 downto 0);
--variable temp_mult: signed(2*WIDTH-1 downto 0);
begin

overflow <= '0';

case sel is

when "0000" =>
temp := std_logic_vector(resize(unsigned(input1), width + 1)+resize(unsigned(input2), width + 1));
output <= temp(width downto 0);
overflow <= temp(WIDTH);

when "0001" =>
temp := std_logic_vector(signed(input1)-signed(input2));

when "0010" =>
temp := std_logic_vector(signed(input1)*signed(input2));
if (unsigned(temp) > (2**WIDTH)-1) then
overflow <= '1';
end if;

when "0011" =>
temp := std_logic_vector(input1 and input2);

when "0100" =>
temp := std_logic_vector(input1 or input2);

when "0101" =>
temp := std_logic_vector(input1 xor input2);

when "0110" =>
temp := std_logic_vector(input1 nor input2);

when "0111" =>
temp := std_logic_vector(not input1);

when "1000" =>
--temp <= input1 sll 1;
temp <= input1(WIDTH-2 downto 0) & "0";

when "1001" =>
temp := '0' & input1(WIDTH-1 downto 0);

when "1010" =>
temp := input1(width/2 downto 0) & input1(width-1 downto 0);

when "1011" =>
for i in 0 to WIDTH-1 loop
temp(i) := input1((width-1)-i);
end loop;

when others =>
temp := (others => '0');

end case;

output <= temp(width-1 downto 0);

end process;

end alu_arch;
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