Quantcast
Channel: Altera Forums
Viewing all 19390 articles
Browse latest View live

Is there an easy way to establish static reconfiguration of transceivers (VOD etc)

$
0
0
Last time I did an FPGA (Stratix IV) you could set transceiver analog properties (VOD, preemphasis etc.) right in the Megawizard. This was convenient if you did not mind re-compiling each time they were to be changed (i.e. you did not need to change them).

Now this does not seem to be possible (I'm using Quartus 13.1 or 14.1 with CycloneV device). I have yet to find any Quartus GUI now that allows clickable selection of analog settings.
I get the impression from the multiple documents that I have read that I need to either:

1 -
Instantiate reconfiguration controller that includes the Avalon interface.
Instantiate a NIOS processor and bridge it to the Avalon interface.
Write C code in the NIOS processor to configure transceivers.

or

2 -
Instantiate reconfiguration controller that includes the Avalon interface.
Somehow get a MIF file configured with the configuration parameters you would like.
Connect MIF to the reconfiguration controller.

Is it really this involved now or am I missing something?

Thanks

[CPLD MAX 10] Connecting the internal oscillator clock to the input of PLL

$
0
0
Hello,

So I wish to utilise the internal oscillator of the CPLD MAX10 as the clock source in my system.
The minimum clock frequency that the oscillator can output is 55MHz (it's a 10M08), which is too high for me (I need a clock that is less than 50MHz), so I let it go through a PLL.

Code:

osc    osc_inst ( // Internal oscillator   
    .oscena ( 1'b1 ),
    .clkout ( in_clk )
    );
   
pll_mod    pll_mod_inst ( // PLL
    .areset ( sys_rst ),
    .inclk0 ( in_clk ),
    .c0 ( clk ),
    .locked ( pll_locked )
    );

And I got an error 15065:

Error (15065): Clock input port inclk[0] of PLL "pll_mod:pll_mod_inst|altpll:altpll_component|pll_ mod_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

I have tried to go through a clock control block (ALTCLKCTRL) before going into PLL too, but still got the same error.

Can anyone help me with this?

Thanks.

EPC8 support discontinued in new version of Quartus

$
0
0
Hi,
In my group we are developing firmware for Altera Stratix II GX fpga. The device is attached to an EPC8 configuration eprom.

Due to the usage of some advanced syntax of SystemVerilog (i.e.: array of interfaces) we use Quartus 13.0sp1. This is the last version of Quartus supporting the Stratix II GX which allows the usage of such syntax.

Unfortunately, we discovered too late that the device support for EPC8 has been discontinued in Quartus 13.0. Just now I realised that I am not able to generate a .pof file while a lot of development and tests were done using .sof only.

I have tried some workarounds already:
1 - syntethise .sof with Quartus 13.0 and generate .pof with quartus 10.1 -> no luck: the tool says that the .sof is corrupted.
2 - export the Quartus version-compatible database -> no luck: it looks like the export is possible only from old to newer versions of Quartus.

Does anybody have a suggestion on how to solve this issue without having to downgrade the full project to a previous version (this would mean reviewing a lot of working code).

Thnaks for your help,
Michele

Do I need USB-to-Serial interface to plot graph real-time from Nios II to Matlab?

$
0
0
Hi,

I am able to read data from FPGA to Nios processor, then transmit this data to Uart component created in Qsys Using direct register method (IORD_ALTERA_AVALON_UART_STATUS (UART_BASE);
IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE, txdata);etc).


I stuck at the point that I want to plot graph to Matlab real time, I found this link (
http://uk.mathworks.com/matlabcentral/fileexchange/28941-real-time-data-plot-from-serial-port), I assume the data that I transmitted to Uart will be available at the serial com port, so I just need Matlab coding to read this data and plot the graph, am I right?


Can I ask one silly question, I still do not understand why do I need USB-to-Serial interface to the board such as FTDI UM245R module?

Without FTDI UM245R module, I thought MATLAB can still talk to serial port, isn't it?? Please correct me if this is wrong.

Thank you

problem printf with de2 basic board

$
0
0
Hi everyone,

I have some trouble with my DE2 basic board. I can't do a printf using Nios II processor, Eclipse always return that the on-chip memory is overflow but with the DE2 basic the maximum space of the Cyclone II EP2C35F672C6N on-chip memory is 64KB (the size I'm using). I haven't find any tutorial for a simple hello world (with the printf function) for the DE2 Basic board.
So someone can help me please ? I'm using Quartus II 13.0sp1, I have created the qsys component (Nios 2 processor, Jtag_uart and 64KB on-chip memory).

Regards,

J.

Access serial port for data sent from Nios II's uart for real time plotting graph in

$
0
0
Hi all,


I am able to read data from FPGA to Nios processor, then transmit this data to Uart component created in Qsys using direct register method (IORD_ALTERA_AVALON_UART_STATUS (UART_BASE);
IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE, txdata);etc).


Then, I was trying to access serial port data sent from uart in Altera Nios II to plot graph real time in Matlab. I was using this code from Matlab central (http://uk.mathworks.com/matlabcentra...om-serial-port) with minor modification as pasted below:


When I run this code I keep getting the following error. What should I do ?


??? In an assignment A(I) = B, the number of elements in B and
I must be the same.


Error in ==> real_time_data_serial at 80
voltage(count) = fscanf(s,'%f');


I found a few solutions on the web, what I have tried:
1. add pause in .m file so that it has enough time to read the data before the next cycle of data


2. add enough delay at C code where I transmit data to uart


3. make sure the uart has the same setting as comport such as comport number, baud rate, parity, flow control






%%real time data plot from a serial port
% This matlab script is for ploting a graph by accessing serial port data in
% real time. Change the com values and all variable values accroding to
% your requirements. Dont forget to add terminator in to your serial device program.
% This script can be modified to be used on any platform by changing the
% serialPort variable.
% Author: Moidu thavot.

%%Clear all variables

clear all;
%%Variables (Edit yourself)

SerialPort='com8'; %serial port
MaxDeviation = 3;%Maximum Allowable Change from one value to next
TimeInterval=0.2;%time interval between each input.0.2
loop=120;%count values
%%Set up the serial port object
s=serial('com8');
set(s,'BaudRate',9600,'DataBits', 8, 'Parity', 'none','StopBits', 1, 'FlowControl', 'none','Terminator','LF');
set(s, 'terminator', 'LF');
set(s, 'timeout', 10);

%%s = serial(SerialPort)
fopen(s);



time =now;
voltage = 0;
%% Set up the figure
figureHandle = figure('NumberTitle','off',...
'Name','Voltage Characteristics',...
'Color',[0 0 0],'Visible','off');

% Set axes
axesHandle = axes('Parent',figureHandle,...
'YGrid','on',...
'YColor',[0.9725 0.9725 0.9725],...
'XGrid','on',...
'XColor',[0.9725 0.9725 0.9725],...
'Color',[0 0 0]);

hold on;

plotHandle = plot(axesHandle,time,voltage,'Marker','.','LineWid th',1,'Color',[0 1 0]);

xlim(axesHandle,[min(time) max(time+0.001)]);

% Create xlabel
xlabel('Time','FontWeight','bold','FontSize',14,'C olor',[1 1 0]);

% Create ylabel
ylabel('Voltage in V','FontWeight','bold','FontSize',14,'Color',[1 1 0]);

% Create title
title('Real Time Data','FontSize',15,'Color',[1 1 0]);




%% Initializing variables

voltage(1)=0;
time(1)=0;
count = 2;
k=1;
while ~isequal(count,loop)

%%Re creating Serial port before timeout

k=k+1;
if k==25
fclose(s);
delete(s);
clear s;
s = serial('com8');
fopen(s)
k=0;
end

%%Serial data accessing
pause(2);
fprintf('here');
voltage(count) = fscanf(s,'%f');

%%For reducing Error Use your own costant

voltage(1)=0;
if (voltage(count)-voltage(count-1)>MaxDeviation)
voltage(count)=voltage(count-1);
end

time(count) = count;
set(plotHandle,'YData',voltage,'XData',time);
set(figureHandle,'Visible','on');
datetick('x','mm/DD HH:MM');

pause(5);
count = count +1;
end



%% Clean up the serial port
fclose(s);
delete(s);
clear s;












When I check the serial port status, I got the following:


Communication Settings
Port: COM8
BaudRate: 9600
Terminator: 'LF'


Communication State
Status: open
RecordStatus: off


Read/Write State
TransferStatus: idle
BytesAvailable: 0
ValuesReceived: 0
ValuesSent: 0




I noticed the serial port is ready (since it is open) but no data is sent or receive. Could you please tell me what is wrong so I could try?


Please , thank you

There is any Qsys component that allows me read and write float values?

$
0
0
Good evening guys, my name is Leonardo Sarraff, i'm a master degree student and i need to know if there is any Qsys component that allows me to read and write float values. I tried to use PIO, but it works only with integer values.
Thanks for the attention.

DE2-115 (Help w/ LED & SWITCH program)

$
0
0
Hello, I'm having trouble understanding a few parameters of my ENTITY statement that seem to play a big role in whether the program executes correctly on my DE2-115 board. This is part of Lab1_Part1 in the SystemsCD I received with my device. The same lab is located here ftp://ftp.altera.com/up/pub/Altera_M.../lab1_VHDL.pdf . Its only part 1 which is on page 1 and 2. It simply links all 18 Red LED's to all 18 Toggle Switches. So by toggling a switch turned its corresponding LED on and vice versa.

When I first wrote this code and uploaded it to my board it didn't work. It compiled fine but it did not execute on the hardware correctly.
I tried doing what they suggested which is import the "DE2-115_pin_assignments" file. I did this through the import assignments button under Assignments in Quartus II. I couldn't find the .csv file that they wanted so I created a .txt file instead and imported that. After uploading the code it automatically turned on two LEDs but that was it and toggling the switches did nothing. I'm attaching the file that I imported as my assignment file just for completeness of this thread. Its titled "DE2-115_pin_assignments.txt".

I troubleshooted this by going through the whole pin assignment process manually
I typed in each port assignment location for each input "that being each switch" and for each output "that being each LED". Uploaded it for the second time and got the exact same results as before.

Here is my code that was not executing correctly on my board

Code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY lab1_part1 IS
PORT ( SIGNAL SW: IN STD_LOGIC_VECTOR(17 DOWNTO 0);
      SIGNAL LEDR: OUT STD_LOGIC_VECTOR(17 DOWNTO 0));     
END lab1_part1;


ARCHITECTURE behavior OF lab1_part1 IS
BEGIN
LEDR <= SW;
END behavior;

Further troubleshooting
The next step I took in troubleshooting this was changing up the ENTITY statement. I declared my two object names "SW and LEDR" as SIGNAL objects. So I erased the "SIGNAL" declaration for each object name and uploaded the new code to my board. It WORKED!!

Here is what my new code looks like

Code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY lab1_part1 IS
PORT ( SW: IN STD_LOGIC_VECTOR(17 DOWNTO 0); --must not use SIGNAL for some reason
          LEDR: OUT STD_LOGIC_VECTOR(17 DOWNTO 0)); --must not use SIGNAL for some reason         
END lab1_part1;


ARCHITECTURE behavior OF lab1_part1 IS
BEGIN
LEDR <= SW;
END behavior;

So my question is
Why don't I declare my object names as a object type "SIGNAL"? According to the definition of SIGNAL it serves as passing values in and out of the circuit as well as between its internal units. Thought that was what SW and LEDR are?!

I looked at the pin_assignment.txt file I imported in as the assignment file thinking that I may find SW and LEDR declared as something different but it doesn't indicate that. It just shows the location assignment for a pin. So really confused on why it worked when I took out SIGNAL and why it didn't work when I had SIGNAL in there. Could someone explain what is going on?
Attached Files

Issues linking library (.lib/.dll) in Nios II Software Tools for Ecplise

$
0
0
Hello all,

I am wondering if anyone out there might be able to help me link a library (Iddk2000.lib/.dll) to my project in Eclipse IDE for C/C++ Developers Version: Indigo Service Release 2 using the MinGW Nios II GCC4 toolchain.

I have been struggling with this for awhile but cannot seem to get any results. Currently, I am including the path to the library and library name in "C/C++ General -> Paths and Symbols" and in "Nios II Application Properties -> Nios II Application Paths" which updates the makefile accordingly but causes error during compilation. The error I have been getting is "ld.exe: cannot find -lIddk2000".

In various attempts to solve this I have tried both 32 bit and 64 bit versions of the library, I have tried local and external file locations and I have tried just linking the .lib, just linking the .dll and linking both. I am curious if anyone has experienced this before and if so how might I fix it? I will include pictures of my linker settings and of the compiler line causing error.

Setting Library Path:


Setting Library Name:


Setting Application Paths:


Compiler Argument / Error:
Attached Images

New Altera Website - fix old links!

$
0
0
First a quick remark about the new Altera website... Thank you very much for breaking what seems like every link to the website in google, this forum, qsys datasheet links, and all my bookmarks.

Is this going to get fixed?

Can you make sure there are redirects to allow links that point to the old website to be forwarded to the corresponding page on the new site. If not then the idea of moving to a new website is probably one of the worst decisions you could have made.

How to change the default name of *.sof file in Quartus

$
0
0
Dear Altera Users,


Where can I change the default *.sof name in the settings of quartus ? I want to create different files (file1.sof, file2.sof, ....) different compilations for the project, so I can avoid to recompile again and again,
I want also to avoid to create different projects for this reason.
thanks for your help
best regards Chahid

connectivity warning of unused output port

$
0
0
if one of port of a module instance do not conneted to a wire /register,quartus will report a warning.

how I can tell quartus this port is un-used eplicitly.

quartus only report connectivity warning that i lost connection.

New website links "Authroization Required"

$
0
0
My orginal post seems to have dissapeared.. at least for me.

I am getting a request for authorization whenever I click on a documentation link after searching on the new altera website, as in this screenshot

http://snag.gy/d3fCs.jpg

What is going on ??

New website download links broken

$
0
0
Well it seem i cant download the software since the new site went up, anybody has a workaround?

.rbf from time limited .sof

$
0
0
I am trying to control a quartus project using an ARM c++ program running on linux. The quartus project includes the Altera FIR compiler 2 IP core. I am unable to convert the .sof file to .rbf in order to configure the FPGA from the micro-sd during boot time. Is it possible to load the linux+frame buffer support from micro-sd and then program the FPGA through J-tag or is there any other solution?

Thank You!

CFI Flash + Stratix V DSP Development Kit

$
0
0
Hi,

I am working with a project which is built around a Stratix V DSP Development Kit. In the system design there is a Nios processor with which I have had problems with the on-chip memory holding its .text section becoming corrupted during reset. As such I am looking at placing the .text section in the CFI flash on the dev board and using the standard bootloader to copy it into the on-chip memory each time it is reset.

I believe this shouldn't be too difficult but I have some concerns about the Flash address map. There is a document that came with the kit which shows the address map (https://www.altera.com/en_US/pdfs/li...sp_dev_kit.pdf) of the CFI flash in the appendix at the end, along with instructions for generating flash programming files for the board update portal.

In the 2012 version of that document, it listed the following commands:
■ For Quartus II .sof files:
sof2flash --input=<yourfile>_hw.sof --output=<yourfile>_hw.flash --offset=0x020A0000
--pfl --optionbit=0x00030000 --programmingmode=PSr
■ For Nios II .elf files:
elf2flash --base=0x0 --end=0x0FFFFFFF --reset=0x071A0000 --input=<yourfile>_sw.elf
--output=<yourfile>_sw.flash
--boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srecr

However these did not match the table showing how the flash is organised, so in 2013 a new version was released which updated the commands to:
■ For Quartus II .sof files:
sof2flash --input=<yourfile>_hw.sof --output=<yourfile>_hw.flash --offset=0x020C0000
--pfl --optionbit=0x00030000 --programmingmode=PSr
■ For Nios II .elf files:
elf2flash --base=0x0 --end=0x0FFFFFFF --reset=0x071C0000 --input=<yourfile>_sw.elf
--output=<yourfile>_sw.flash
--boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srecr

Which does match the flash map.

However, and here is one of the sources of confusion I am having, when I use the latter command for the sof file (haven't got to testing the elf one yet), it the design doesn't get loaded or run properly. If on the other hand I use the command from the original version of the document (with the 'incorrect' address), the design is loaded correctly and runs fine.
So can someone tell me what the *actual* flash map is, because it seems to me that it was not the commands that were wrong in the initial version, but the map itself. Has anyone else had this problem?



Now on to the Nios side of things. Until now I have been using on-chip memory where the elf was converted to a hex file which was in turn embedded in the sof. In this scenario it has been working fine, except when I reset part of the system (I asked about this in another thread but got limited response). So now I want the elf file to be put in the flash and to use a bootloader.

But at this point there isn't any clear information on how to proceed. I've instantiated a generic tristate conduit controller which is connected to the CFI flash pins and mapped into Nios address space. Now I mapped the flash so that it takes address range 0x08000000 to 0x0FFFFFFF in the Nios address space, and have set the reset vector to point to an offset of 0x0 in that memory (i.e. a reset vector of 0x08000000).
But now when I come to try and run the command from the documentation, it says that the reset vector doesn't match the elf, and then sticks all of the code starting at 0x0000000 in the flash which is clearly not correct.

Sould I instead use an offset of 0x071C0000 for the reset vector (i.e. a reset vector of 0x0F1C0000), but then that wouldn't match either.
Or, do I have to move the addresses of all of my other components so that the flash is mapped into the Nios address space at 0x0000000 to 0x07FFFFFF. Then use an offset of 0x071C0000. That would mean the reset vectors do match, but is this actually correct?
There is another region of the flash map called 'user design reset vector' at address 0x0000000, so do I want a reset vector of 0x0000000? If so how do I specify that the application code should be at 0x071C0000, but the reset vector (and bootloader) should be at 0x0000000.
Given that with the sof2Flash commands I noticed that the incorrect address worked fine for the sof, so do I actually want a reset vector of 0x071a0000 like i the original command?

I also notice that the --end in that command is actually pointing to a point far outside the CFI address space - there is only 128MB of flash yet the specified range is 256MB. So why is the command using the --end value it is?

So now I am totally confused as to what numbers to use where.




So, to summarise:

(1) What is the correct address map of the flash on this dev kit? And if what is in the table is correct, why does my design not load when I use those numbers?

(2) How do I connect the flash to the Nios and correctly set up the location of the bootloader and data?

is "for loop" in counter looping according clock cycle?

$
0
0
Hi, all

I would like to create a adjustable delay counter using verilog. I use for loop inside. However, I notice that the for loop does not count base on clock cycle. Any mistake I done?
Below is my coding:

always @(posedge clk or posedge rst_counter)
begin
if (rst_counter)
begin
abc <= 0;

end
else if (en_counter)
begin
for (i=0;i<= receiveSize; i++)
begin
if (i== receiveSize)
abc <= 1;
end


end
end

Verification failed - SDRAM module

$
0
0
Hey<br><br>I'm struggling to overcome a verification errors when attempting to download my .elf onto my Cyclone 4 E. I can get the "hello world" example to download when only using onchip mem but cannot when an sdram module is present. Even if the nios core references only onchip mem, if the sdram module is connected to the data/instruction buses then it isn't able to verify the program I try to download. I believe this to be caused by the base addressing scheme but do not understand it well enough to validate my theory. I've always used the "assign base addresses" tool in Qsys but this has not helped. I've also used the base addressing scheme as assigned when only onchip mem is present and an sdram module added after. Still this has not worked and strangely nios attempts to read from 0x80000000 onward despite onchip mem begining at a smaller address. <br><br>I don't think the memory chip itself is at fault as even when the nios core is meant to be using onchip mem the nios ide reports that 0x8000000 to 0x8000XXXX is being scanned. Not sure really what to do about this as I've spent a couple days trying to debug these problems with no luck. Please help! <br><br><br>Using the base addressing scheme as per the onchip mem config with the nios core referencing onchip mem:<br><img src="http://www.alteraforum.com/forum/attachment.php?attachmentid=10295&amp;stc=1" attachmentid="10295" alt="" id="vbattach_10295" class="previewthumb"><br>&nbsp; <br>Problem itself<br><img src="http://www.alteraforum.com/forum/attachment.php?attachmentid=10296&amp;stc=1" attachmentid="10296" alt="" id="vbattach_10296" class="previewthumb">

Timing driven compilation - appears to not balance setup-hold window

$
0
0
I have a problem meeting timing in a cyclone V design with a source synchronous DDR 500Mbps (250MHz clk) input bus. The inputs are constrained with set_input_delay, set_false_path and the clock is setup as recommended in the various guides for DDR constraining including the command "quartus_sta --ssc <revision name>", AN433 and the excellent TimeQuest User Guide by RYSC. The timing relations looks ok - the right edges are in play when looking at timing analyzer waveforms, except for the balancing of setup-hold margins: Some are slightly negative, but the other margin is positive, so delay adjustments can tighten this up.

I do a multi corner compilation with these special options
Code:

set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA

The result indicates as mentioned, that the different inputs have different su-ho margins. Some inputs would benefit from adding delay in the data path to improve hold time slack at the expense of setup slack, others would benefit from less data delay to improve setup slack at the expense of hold slack.
If I use the "locate in resource property editor" command to see the properties of the different bus inputs, I can see, that they are all assigned the same delay in the D1 and D3 delay blocks. Delays added in the data paths is 606ps(D1) 3998ps(D3). There is both room for increasing the delay and for reducing the delay here.

This is what surprises me: Why does the timing driven complation not adjust these delays individually to better center the su-ho window?
Am I missing an important compile option or do I have to manually adjust these delays to balance su-ho margins?

Thanks

Inferred latch warning

$
0
0
Hi,

When I write the following code:

ENTITY test IS
GENERIC (
DW: INTEGER := 4
);
... clk, rst_n and other ports
END ENTITY;

ARCHITECTURE rtl OF test IS
a: UNSIGNED(31 DOWNTO 0);
BEGIN -- arch

PROCESS (clk, rst_n)
BEGIN
IF rst_n='0' THEN
a <= TO_UNSIGNED(0, a'LENGTH);
ELSIF clk'EVENT AND clk = '1' THEN
a <= a + DW;
END IF;
... other code using a (this is the wrong place to do that, as was pointed out in the discussion)
END PROCESS;
... other code (incl. processes) that use a
END ARCHITECTURE;

When DW is e.g. 2 or 4 (but not 1), the compiler warns (10631) about latches being inferred for a. The warning seems incorrect to me: it is true that a(0) will not be assigned in the synthesized design, but only because the compiler has optimized away my assignment to it. And in effect, it becomes stuck to '0' and won't become a latch, as is expected.

This kind of warning is a nuisance in modular code since the warning is usually indicative of a serious design error, but it is false, and draws my attention away. Sooner or later I look over a genuine warning...

Can I avoid it somehow ?

Thanks,


J.
Viewing all 19390 articles
Browse latest View live


<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>