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Altera Monitor Program not showing "start symbol" Program Options for custom NiosII

March 8, 2015, 7:04 pm
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Hey Everyone,

I'm new to this forum and not quite sure how to start, but recently I've been working on trying to implement an embedded processor, Nios II for my class project. When I use the Altera Monitor Program to create a new project under "Custom System", and after I specified a program type to add my own Assembly source into the project, the Program Options for the start symbol disappears and I can't go move on to the next step, because of the error stating "Invalid start symbol. Must began with an underscore or a letter and can only contain underscores and alphanumeric characters...". If I use anyone of the preconfigured systems, it works and shows the Program Options for the start symbol. I have some images below in regards to what I'm trying to explain.

I'm currently running my system with the specs below:

Windows 7 x64
Quartus II 14.0 (with updates installed)
Altera Monitor Program 14.0
DE2-115 FPGA board


Anyone come across this issue before?

This shows if used DE2-Media Computer


This occurs when using <Custom System> and loading my .sopc and .sof files from Quartus II.
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Do i get the DCC-HSMC or the ADA-HSMC for DSP work?

March 8, 2015, 8:33 pm
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I have a Altera DE2-115 Cyclone IV board and I have a fundamental understanding of Digital Logic as well as VHDL. My core interest is in Signal Processing that being DSP in digital and audio signal processing. I would like to start putting theory to practice using my board but I need an expansion board of some kind that can allow me to do these things. I've researched some options and have come up with two. However, I'm not for sure what the major difference is between them and which one would be more suited to my needs. Could someone lay in on what I would find more accommodating. Having plenty of documentation/examples to refer to is important to me so if one has more documentation/examples over the other I would prefer that one.


My Options:

1.) ADA-HSMC
2.) DCC-HSMC
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NIOS II CustomComponent Programming Problem

March 8, 2015, 10:22 pm
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Hi all,

I have created a LED register in vhdl and created qsys component out of that. Connected it to the nios processor as shown in below images. Created NIOS project and when I am trying to run the code the register is not updated. But if I access with the base address of the memory map generated, it is getting updated. Kindly someone let me know what could be the issue.

I included system.h and written a simple program to edit the led base register. From memory I am able to access and blink led. But from C program I am not able to control it.

#include <stdio.h>
#include "system.h"
int main()
{
unsigned int* ledbaseaddr =(unsigned int *) LEDREG_0_BASE;
// unsigned int i;
while(1)
{
*ledbaseaddr = 0xFF;
//for(i=0;i<100;i++);
*ledbaseaddr = 0x00;
}
}








Regards,
Phaniendra
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S29GL256P90 with qSys

March 9, 2015, 5:21 am
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Hey, I'm trying to interface the `S29GL256P90` which is a Flash device via a NIOS2 system that was created with qSys altera 13.1

here are screen shoots of the configuration:











However when I try to open the Flash with my NIOS 2 code, it returns null.
After an inspection with signal tap, it looks like it's trying to test it but the device does not repone.
any ideas?

the configuration uses Tristate-conduit bridge and generic TriState Controler
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Megafunctions not enabled

March 9, 2015, 7:05 am
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HI, I am new to dsp builder and I need to work on mega-functions part of it on my Simulink but the control is dull hight-lighted and after I instantiated it and compiled it, no output or input came out. what might be responsible?
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Where have the PDF data sheets gone?

March 9, 2015, 7:33 am
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Doing battle with the new website and I can't find PDF copies of the MAX10 data sheets. Clicking on the links takes me to an 'documentation portal' to view them on-line (using an annoyingly small area of my monitor) but that is no good. I need to download the PDFs to view off line and archive with the project.

Help?



HelpDocumentation Porta

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Why I couldn't transmit data to UART using IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE,

March 9, 2015, 8:58 am
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Hi,

I used the following code to access the UART (rs232 serial port) component I created in Qsys, I connected the txdata pin to the oscilloscope and it shows nothing, i am wondering why couldn't I use IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE, txdata); to transmit data to UART?
What I want to do is Nios processor reads data from FPGA, Nios transmits the data to serial port and plot graph real time using Maltab,using de0 nano. I do not need to read data from serial port.

#include "altera_avalon_uart_regs.h"

#define UART_BASE 0x00002000


int main (void)
{alt_u16 status, rxdata=0,aa=0, txdata=0;
while (! (status & 0x0040)) // Wait for transmission completion
status = IORD_ALTERA_AVALON_UART_STATUS (UART_BASE);
printf("status= %.2f V \r\n", (float) status);
rxdata = 5; // assuming I get this data by accessing sdram in Nios
txdata = rxdata;

IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE, txdata);
printf("txdata= %.2f V \r\n", (float) txdata);

return 0;}


Could you please give me some hints? Thanks
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DisplayPort

March 9, 2015, 9:54 am
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Hi all,

Normally the VESA mentions that the DP (with 4lines) is able to send 12-ppc YCbCr 4: 2: 2 (24 dpi) corresponding to 1920x1080p @ 120Hz
I would like to know what will be the DTM (Display Monitor Timing) appropriate for it and the format of the video interface DP_Source (TX_VID_V, TX_VID_H,TX_VID_DE).
The aim is to send a stream video from the Altera IP DisplayPort to the Altera IP HD-SDI.


Thanks
Regards,
Hayder
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memory width modification in NIOS II Eclipse

March 9, 2015, 4:03 pm
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I am using Qaurtus 13.0 and want to make a modification in the build. the memory initialization file that is generated by NIOS II eclipse is 64 bits per row and when I want to integrate this with my RTL build, I see some warnings in Quartus. my NIOS memory is 32 bits. I don't think these warnings cause any problem but I am kind of cleaning up the project and I want to fix this.
As I mentioned, I use NIOS II eclipse for compiling FW. I see there is a script called "create_this_app" that generates a "Makefile". "Makefile" calls a "mem_init.mk" script. as you see here, "mem_init.mk" has some commands for converting elf to hex:

$(HEX_FILES): %.hex: $(ELF)
$(post-process-info)
@$(MKDIR) $(@D)
bash -c '$(ELF2HEX) $< $(mem_start_address) $(mem_end_address) --width=$(mem_width) \
$(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2hex_extra_args) $@'

the mem_width has a default value which is 64 bits. How can I pass a parameter to the "create_this_app" script for changing mem_width to 32 bits automatically? of course one way is changing this manually in "mem_init.mk" but I don't want to do that and ask people to modify their script every time they run their FW. the only place that I want to change and commit into SVN is "create_this_app" script which is top level script.
Any idea?
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how to bypass IO limit to get a utilization summary?

March 9, 2015, 6:31 pm
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Hi,

I wish to get a rough idea of how many registers and ALMs the design takes on Stratix V.
It has passed the Analysis and Synthesis, yet in fitter it stopped with the following error:

Error (169281): There are 3754 IO input pads in the design, but only 968 IO input pad locations available on the device.
Error (169282): There are 4352 IO output pads in the design, but only 968 IO output pad locations available on the device.

It's a design with large number of IOs and I don't want to add the shim at the moment, can anyone suggest a way to bypass the error, just to get a rough number?
Without solving the error, the number of registers yield in fitter summary is unreasonably small.....I assume this has something to do with the IO problem.

Thanks!!!!!!
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long simulation times when simulating UniPHY-based DDR3 in skip calibration mode

March 9, 2015, 9:11 pm
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Hi, all


According to this article at emi_debug.pdf on page 8: Table 1–1. Typical Simulation Times Using UniPHY IP, skip calibration should take only 3 minutes. My DDR3 UniPHY design is very basic with 8 bits read and write operation. I use generated example design for simulation. For my case, I choose skip calibration mode and also disable the EMIF On-Chip Debug Toolkit in Diagnostics tab of the UniPHY-based controller MegaWizard GUI.


Figure below is ModelSim starter 10.3c waveform simulation. To get overall complete simulation (110us), my computer took about more than 30 minutes to complete it.




May I know how to reduce the simulation time as stated in 3 minutes? Any example design file i need to reedit?

Thanks!
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Installing altera 11.1sp2 on ubuntu 14.04LTS

March 9, 2015, 9:25 pm
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Hi, I have been trying to install altera 11.1sp2 for the past few hours and seem to be getting nowhere. I initially had the same problem as outlined in this thread(http://www.alteraforum.com/forum/showthread.php?t=34368) I have tried both simply typing into the console with the bash ./setup as well as editing the setup file to bash instead of sh. My current problem is as follows:

I enter the following into terminal
Code:
~/11.1sp2_259_quartus_free_linux$ ./setup
It outputs
Code:
Welcome to Altera Software Installer
Copyright (c) Altera Corporation 2011

Starting GUI. If nothing shows up, or you don't have an X display, run:
  ./setup --help
for commandline usage.
NOTE: All output has been redirected to /tmp/altera_setup.log.HgItAUK044
Nothing shows up. So I then try

Code:
./setup --help
it returns

Code:
Traceback (most recent call last):
  File "<string>", line 23, in <module>
  File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 436, in importHook
  File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 521, in doimport
  File "/build/swbuild/SJ/nightly/11.1sp2/259/l32/work/installers/linux32/build/pyi.linux2/altera_installer_cmd/outPYZ1.pyz/cli", line 23, in <module>
  File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 436, in importHook
  File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 521, in doimport
  File "/build/swbuild/SJ/nightly/11.1sp2/259/l32/work/installers/linux32/build/pyi.linux2/altera_installer_cmd/outPYZ1.pyz/altera_installer", line 34, in <module>
  File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 436, in importHook
  File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 521, in doimport
  File "/build/swbuild/SJ/nightly/11.1sp2/259/l32/work/installers/linux32/build/pyi.linux2/altera_installer_cmd/outPYZ1.pyz/gui_common", line 18, in <module>
  File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 477, in importHook
  File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 495, in doimport
  File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 297, in getmod
  File "/tools/python/2.6.4/linux32/pyinstaller/archive.py", line 468, in getmod
  File "/tools/python/2.6.4/linux32/pyinstaller/iu.py", line 109, in getmod
ImportError: /usr/lib/i386-linux-gnu/libfreetype.so.6: symbol png_set_expand_gray_1_2_4_to_8, version PNG12_0 not defined in file libpng12.so.0 with link time reference
Sorry if the solution is increadibly obvious im rather bad when it comes to linux I only started using it when I started at uni. Thanks a lot for any assistance you can give me.
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Performance of FPGA vs FPGA with SOC

March 9, 2015, 11:29 pm
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Hi I am deciding on a FPGA for image processing purposes and I would like to know the difference in performance between a FPGA and a FPGA soc.

Will a stand along FPGA be faster than FPGA soc? Or does it depend on the application. Can I achieve the same bandwidth with either FPGA or FPGA soc?

Thank you

Ritesh
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jtag uart reading and parameters

March 10, 2015, 12:16 am
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Hello all,
do you have some experiences with setting Altera logging options, which are meantioned on page 6-11, 6-12 in Nios II Software Developers Handbook ? I mean the ALT_LOG_JTAG_UART_TICKS - default is 10 (ticks per second). Or HW FIFO wspace = 64. Where am i able to set these values ?
When we use in linux terminal some command like this:
\> cat file.hex > nios2-terminal

and i have some design and program which read jtag uart and sending on the leds, i saw on oscilloscope that i am able to read only 64 bytes per 100ms (its determinated i think these parameters ALT_LOG_JTAG_UART_TICKS and HW FIFO wspace = 64) and it is too small for my application.

Thank you for your answer.

Jan Naceradsky, Czech Republic
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State machine fail to hold default value

March 10, 2015, 1:49 am
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Hi, all

Here's example of my state machine coding in verilog:

Quote:
always @(posedge clkADC or posedge RST)
begin
if (RST)
state <= s0;
else
case (state)
s0: if (START) state <= s1; else state <= s0;
s1: ns <=s2;
s2: ns <=s3;
s3: ns <= s0;
endcase
end

always@(state, DataIn)
begin
case (state)
s1:begin
fifo_wreq <= 1;
Data <= DataIn;
end
s2:begin
Data <= DataIn;
end
s3:begin
Data <= DataIn;
fifo_wreq <= 1;
end
default:begin
Data <= 12'b000000000000;
fifo_wreq <= 0;
end
endcase
end
fifo_wreq at s2 suppose to be default value, which is 0. However, I found out that it remain 1 at state machine s2. May I know any mistake i do so far?
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Cyclone-V SOC development kit not working properly

March 10, 2015, 3:36 am
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My Cyclone-V SOC development kit is not working properly:(, can anyone tell me how can I check the device?:confused:
The problem I'm getting is that while downloading the program(.sof File) to the kit, the downloading gets failed, if I give "auto detect" an error message displays as "Unable to scan device chain. Can't scan JTAG chain. Do you want to open the JTAG chain debugger to troubleshoot the JTAG chain?".
Please anybody help me out with this problem.:mellow:
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Quartus 13.1 web edition : No .pof produced

March 10, 2015, 7:36 am
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Hi,
I am using Quartus 13.1 Web edition and I have done a project that seems to work fine with .sof file programer.
And now, I would like to permanent program it, but no .pof file is in output file directory...

Do I have missed something ?
(My english is poor, sorry, french people are not so fluent in other language)

Thank in advance
Benoit
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Communication between arm hps and fpga slave

March 10, 2015, 9:07 am
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Hi everybody,
I need to transfer data from arm to fpga on a Cyclone V 5CSXFC6D6F31C6.
I'm trying with a little test program, I've a simple peripheral in FPGA connected to the 4 leds and mapped in the hps memory space. I finally managed to write and read data from it from a C program running on ARM, using mmap() to map the device in the program virtual space. This is a peaky approach, I've seen several tutorials using hps library and functions, but I cannot figure out how I can use them (which compiler I have to use? which include path? wich... I don't know?!).

Any help would be really appreciate,
Thank you in advance.
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Where er the PDF documents for Cyclone 5

March 10, 2015, 9:15 am
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Folks,

I need to download the Cyclone V Handbook (and other device docs) as one PDF document. (Like the old days before the new website.) How can I do do that?

It also seems like most of the live links in the docs I downloaded before the new website are also broken. Will this be fixed? Will the links in the new docs work?

The document search function doesn't seem to work in many cases. Is that going to be fixed? If so, when?

Some feedback: The new website seems to be badly broken. Making it difficult for your customers to obtain documentation easily hinders progress and impacts our schedules. The roll out of the new website seems to be ill conceived and improperly implemented.

Thanks,

jp
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can not understand the figure of High-Performance controller ?

March 10, 2015, 10:12 am
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I can not understand the figure in "Chapter 3: Using High-Performance DDR, DDR2, and DDR3 SDRAM with SOPC Builder"
what is the signal which the red arrow point to?
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