using hpc ii ,find that the signal wave of modelsim is right,but signal wave on tap ii is not right?
which i should believe ?
which i should believe ?
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using hpc ii ,find that the signal of modelsim is right,but signal tap ii is not?
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Compatibility Q14.1
I have a project I started with Q12 and I always was able to switch back-and forth between Quartus versions.
Recently I started using Q14.1. But since the corresponding Modelsim version behaves strangely I cannot use my scripts there.
So I wanted to go back to 14.0 to simulate. This is however not possible. When I try to open the project in Q14 it tells me
Error (125048): Error reading Quartus II Settings File X.qsf, line 70 Info (125063): set_global_assignment -name QII_AUTO_PACKED_REGISTERS "MINIMIZE AREA"
Should I change the settings, and if so, what do I need to change?
Recently I started using Q14.1. But since the corresponding Modelsim version behaves strangely I cannot use my scripts there.
So I wanted to go back to 14.0 to simulate. This is however not possible. When I try to open the project in Q14 it tells me
Error (125048): Error reading Quartus II Settings File X.qsf, line 70 Info (125063): set_global_assignment -name QII_AUTO_PACKED_REGISTERS "MINIMIZE AREA"
Should I change the settings, and if so, what do I need to change?
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Help!! Beryll board!
I am training FPGA with beryll board. But I don't have doccument and demonstration for it. Can you help me! Thanks all!
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De0 Nano Ethernet communication using the enc28j60 controller
how are you guys. I have a de0 nano board and an enc28j60 Ethernet board. I want to experiment on an embedded web-server using the Nios ii processor and micro C linux. Do anyone have an idea how to go about this. Can anyone provide example projects so that I can follow. My further experiment is to implement industrial Ethernet.
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Cyclone V Baremetal application: Could not Determine Target State
Hi,
I have a built a system using Qsys and loaded the compiled system into the FPGA.
On the software side, I'm able to run the example hello world program on the DS-5.
I built an application, used arm-altera-eabi-gcc compiler and used the cycloneV-dk-ram-hosted.ld linker script to build the program. I have attached the console log.
I'm not sure of what files generated by qsys is to be included for building the program since the application needs to know about the ip's used in the system. Could anyone please advise me on this issue?
I'm using a Cyclone V Arrow SoCkit with Quartus 14.1 and DS-5 Altera edition.
Thanks in advance.
Best Regards,
Nitin.
I have a built a system using Qsys and loaded the compiled system into the FPGA.
On the software side, I'm able to run the example hello world program on the DS-5.
I built an application, used arm-altera-eabi-gcc compiler and used the cycloneV-dk-ram-hosted.ld linker script to build the program. I have attached the console log.
I'm not sure of what files generated by qsys is to be included for building the program since the application needs to know about the ip's used in the system. Could anyone please advise me on this issue?
I'm using a Cyclone V Arrow SoCkit with Quartus 14.1 and DS-5 Altera edition.
Thanks in advance.
Best Regards,
Nitin.
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Altera Cyclone V SoC dev kit-- LED not working
Hi,
I am running my application on the HPS component of Altera Cyclone V Soc dev kit. My application uses a toggling LED and I am not able to output it.
I have configured the
- Reset Manager
-System manager i.e. Pin Mux selection for GPIO
-Clock manager the clk signal
and the
-GPIO1 module (gpio41 to gpio44)
Am I missing anything else..?
Umar.
I am running my application on the HPS component of Altera Cyclone V Soc dev kit. My application uses a toggling LED and I am not able to output it.
I have configured the
- Reset Manager
-System manager i.e. Pin Mux selection for GPIO
-Clock manager the clk signal
and the
-GPIO1 module (gpio41 to gpio44)
Am I missing anything else..?
Umar.
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cross correlation of OFDM
hi i have been trying to implement multiplierless cross correlation of OFDM for IEEE 802.16d and i am stuck on the part as to how should i represent my correlator coeffiients . as they are in complex for such as 16 correlator coeffiecients -1,-1j .... for quantization level 1 and what should be my known preamble as it should also be of 16 samples. i am currently confused about this part i have bee reading various paper on it and none specify how to represent correlator coefficients in binary form and what should it be correlated with can you please help
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Software Update for NIOS without reconfiguring FPGA (Max10)
Hey there,
this is my first post in this forum and I haven't dived deep into the NIOS Softcores yet, but I encountered an architectural problem alreay.
In my final product I want to have the option to update the firmware running inside the Softcore (NIOS) without reconfiguring the complete FPGA that I'm using (goal right now is to use a fairly big Max10 device). It is important that the data is retained after a startup!
Everything I've tried so far has always resulted in getting me just a complete programming file for the FPGA. My idea was along the lines of just putting the Nios into reset (while other parts are still working, not 100% sure right now) and then just reprogram the portion of the memory that holds the Nios firmware.
Is something like this even possible?
best regards, Marc
this is my first post in this forum and I haven't dived deep into the NIOS Softcores yet, but I encountered an architectural problem alreay.
In my final product I want to have the option to update the firmware running inside the Softcore (NIOS) without reconfiguring the complete FPGA that I'm using (goal right now is to use a fairly big Max10 device). It is important that the data is retained after a startup!
Everything I've tried so far has always resulted in getting me just a complete programming file for the FPGA. My idea was along the lines of just putting the Nios into reset (while other parts are still working, not 100% sure right now) and then just reprogram the portion of the memory that holds the Nios firmware.
Is something like this even possible?
best regards, Marc
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How simulate system with NIOS in Quartus?
Hello! I want to simulate my system, consists of spi, nios and pio(I build system in qsys). First I simulate only nios from eclips(using Modelsim), but when I decide to simulate system with nios in quartus.
The task is to write one 32 bits number to spi and when write this word to pio.
Is it possible to simulate system, including nios processor in quartus (because I couldn't set input signals to nios for spi) ?
The task is to write one 32 bits number to spi and when write this word to pio.
Is it possible to simulate system, including nios processor in quartus (because I couldn't set input signals to nios for spi) ?
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making of a 3 bit binary number from three individual 1 bit value.
i have three nos value like a , b and c. and each are 1 bit binary value. how i convert it into a three bit binary value where a is the most significant bit and c is the least significant bit and b is the middle bit. example: if a=1 , b=0 and c=1 then how i make it a three bit binary valu which containing as x[2..0] or x= value of [a b c]
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error,when build the interrupt.c in ds-5
Hi,
Actually I am a beginner in using ds-5 to learn the HPS. Currently I am having some trouble in trying the interrupt code.
This is a simple interrupt code.
...
mian()
{...
socfpga_int_start();
...
alt_int_isr_register(.....);
...
socfpga_int_stop();
...
}
some error show this:
![]()
Actually I am a beginner in using ds-5 to learn the HPS. Currently I am having some trouble in trying the interrupt code.
This is a simple interrupt code.
...
mian()
{...
socfpga_int_start();
...
alt_int_isr_register(.....);
...
socfpga_int_stop();
...
}
some error show this:
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too many instance performance degradation
I am using the Altera custom licensed version of Modelsim.
It is complaining that I have too many instances (5) and there will be a performance degradation.
And there is, it is unbelievably slow.
Too many instance of what??
What can I do about it??
Thanks,
Don
It is complaining that I have too many instances (5) and there will be a performance degradation.
And there is, it is unbelievably slow.
Too many instance of what??
What can I do about it??
Thanks,
Don
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CameraLink with Cyclone IV GX
I'm looking at making a CameraLink transmitter using the GX transmitter blocks in the Cyclone IV. ALTGX won't allow me to select a channel width of 7 which is the serialization factor. Is this an inherent limitation?
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testbench problem
Hello everyone
I need some help,I make testbench on simulation wave form editor but i face this problem when run and generate testbench
What is the solution ?
thank you
![]()
I need some help,I make testbench on simulation wave form editor but i face this problem when run and generate testbench
What is the solution ?
thank you
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Cost of implementation of logic and arithmetic operations
Hello Members,
My question:
What is the cost of implementation, in terms of logic elements, frequency, memories, area ..., of the logic and arithmetic operations (addition, subtraction, multiplication, division ...) in fpga cyclone ii?
for example, to implement a multiplier 2*2 bits, how much we need:
+ Logic elements
+ memory
+ Frequency
+ area
+...
Regards,
My question:
What is the cost of implementation, in terms of logic elements, frequency, memories, area ..., of the logic and arithmetic operations (addition, subtraction, multiplication, division ...) in fpga cyclone ii?
for example, to implement a multiplier 2*2 bits, how much we need:
+ Logic elements
+ memory
+ Frequency
+ area
+...
Regards,
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a question about the effiency of HPC II?
Now I use HPC ii to operate two ddr2 chip(parallel connet to the FPGA,act as a 32 bit data bus ddr2),and the operate mode is full rate,
and I have 10 input ports to write and 10 output ports to read the 32 bit ddr2, each time I will write or read 64bit*8 datas, but I have notice when I simulate the HPC II,that after I assert the local_read_req and local_burst signal ,almost delay about 30 phy_clk,and then the HPC II assert the local_rdata_valid,in the 30 phy_clk,can I do something?
Can I do operate the HPC II to write to or read from the DDR2 in the 30 phy_clk delay ???
In the situation switching to read or write the DDR2,how much is the effiency value of HPC II ??
![]()
and I have 10 input ports to write and 10 output ports to read the 32 bit ddr2, each time I will write or read 64bit*8 datas, but I have notice when I simulate the HPC II,that after I assert the local_read_req and local_burst signal ,almost delay about 30 phy_clk,and then the HPC II assert the local_rdata_valid,in the 30 phy_clk,can I do something?
Can I do operate the HPC II to write to or read from the DDR2 in the 30 phy_clk delay ???
In the situation switching to read or write the DDR2,how much is the effiency value of HPC II ??
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FPGA Development Board
Hello,
I am looking for a Arria V or Stratix FPGA development board with a FMC connector (should have minimum 32 LVDS pairs). Could anyone help get me the right board for my requirement.
Regards,
Senthil
I am looking for a Arria V or Stratix FPGA development board with a FMC connector (should have minimum 32 LVDS pairs). Could anyone help get me the right board for my requirement.
Regards,
Senthil
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Altera UFM for I2C interface protocol
Hi,
I am using Quartus II (v14.0).
Using the IP Parameter Editor i have created a altera_ufm_i2c with settings:
Access mode: read only
Address MSB: 1010
Memory size: 4k
currently initalized blank (all 1's) but will be init from file eventually. (am also a bit unclear what the file should look like (HEX), but that's a different question)
This is then instansiated in my main code block. I am able to do a loop-back test over i2c so am confident the IP is correctly in my code.
My question is: What is the protocol to read the UFM over i2c from a given memory location. On other devices i've used the process is normally:
start bit / device address (1010-000-1[W])/ 16bit off set
start bit / device address (1010-000-0[R])/ ... and the location is read from the offset memory olocation over i2c
I have tried the following links but no luck so far:
https://www.altera.com/en_US/pdfs/li...ug_alt_ufm.pdf
https://www.altera.com/en_US/pdfs/li...e/an/an489.pdf
Any help much appreciated.
I am using Quartus II (v14.0).
Using the IP Parameter Editor i have created a altera_ufm_i2c with settings:
Access mode: read only
Address MSB: 1010
Memory size: 4k
currently initalized blank (all 1's) but will be init from file eventually. (am also a bit unclear what the file should look like (HEX), but that's a different question)
This is then instansiated in my main code block. I am able to do a loop-back test over i2c so am confident the IP is correctly in my code.
My question is: What is the protocol to read the UFM over i2c from a given memory location. On other devices i've used the process is normally:
start bit / device address (1010-000-1[W])/ 16bit off set
start bit / device address (1010-000-0[R])/ ... and the location is read from the offset memory olocation over i2c
I have tried the following links but no luck so far:
https://www.altera.com/en_US/pdfs/li...ug_alt_ufm.pdf
https://www.altera.com/en_US/pdfs/li...e/an/an489.pdf
Any help much appreciated.
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Cyclone V Soc LEDs Issue- Help Required
Hi,
I am using cyclone V Soc HPS. Issue I am facing is I have been able to access GPIOs button and DIP switches but i am unable to access LEDs. I am using lauterbach for debugging. Changes made by the application are reflected in the CPUs registers. Toggling DIP switches toggles corresponding bits in registers but toggling LEDs bits have no effect on LEDs.
(*((int * ) 0xFF709004)) = 0x0000F000; // DDR of GPIO1 module : 1-> LED pins as O/P [bits: 12-15]
(*((int * ) 0xFF709000)) = 0x00000000; // DR of GPIO1 module : 0-> LEDs ON (active low) [bits: 12-15]
Above locations are being used for LEDs. Let me know if I am missing anything.
Thanks in advance.
I am using cyclone V Soc HPS. Issue I am facing is I have been able to access GPIOs button and DIP switches but i am unable to access LEDs. I am using lauterbach for debugging. Changes made by the application are reflected in the CPUs registers. Toggling DIP switches toggles corresponding bits in registers but toggling LEDs bits have no effect on LEDs.
(*((int * ) 0xFF709004)) = 0x0000F000; // DDR of GPIO1 module : 1-> LED pins as O/P [bits: 12-15]
(*((int * ) 0xFF709000)) = 0x00000000; // DR of GPIO1 module : 0-> LEDs ON (active low) [bits: 12-15]
Above locations are being used for LEDs. Let me know if I am missing anything.
Thanks in advance.
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Interval Timer Core Interrupt for Nios II
I have seen many examples of using PIO cores to generate interrupts...say for button presses, and I have a grasp on those, but I am looking for a clear example of generating an interrupt using the timer core. My hardware is setup to generate a 1ms interval clock (see image attached for the setup) to IRQ 1 (high value interrupt) as I want to perform a specific task every millisecond (for example take a reading from an ADC), but I cannot grasp how to properly make this happen in the C code (I'm new to C programming not to hardware design...so it's the programming that I'm having issue with). If someone could help out a bit with a clear and small example of this that would be helpful, or point me in a direction where there is an example. Thanks, Jason
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