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Assigning individual bits

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Hi all,

I'm a complete newbie in Verilog, so I have a question.

I have in my main Verilog file (irrelevant code stripped out):

Code:

//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================

module Lab2(
    //////////// SEG7 //////////
    HEX0,
    HEX1,
    HEX2,
    HEX3,
    HEX4,
    HEX5,
    HEX6,
    HEX7
);

//////////// SEG7 //////////
output            [6:0]        HEX0;
output            [6:0]        HEX1;
output            [6:0]        HEX2;
output            [6:0]        HEX3;
output            [6:0]        HEX4;
output            [6:0]        HEX5;
output            [6:0]        HEX6;
output            [6:0]        HEX7;

    Default u0 (
        .id7seg_display_export        (???)
    );

endmodule

Now, Default.id7seg_display_export is declared as:

Code:

output wire [27:0] id7seg_display_export  // id7seg_display.export
My question is, how do I connect individual bits from id7seg_display_export to the different HEX outputs signals? I just can't figure it out because I don't know the syntax...

Get memory address out from Qsys system

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Hi,

I have a Qsys system with two NiosII processors sharing one memory device, for both instruction and data.
I need to get the data memory addresses produced by the two processors out of the Qsys system, while the system works normally.
Is it possible to do this using a custom component connected to the Qsys avalon interconnect? (Processors see the custom component as the memory device. The custom component forwards the addresses to the actual memory, as well as to the vhdl toplevel outside)?

I appreciate any suggestions on how to do this. I should say I'm new to FPGA based systems.

Many thanks.. Cheers !
-
Isuru

DE4-230 board powered off after .sof load and soft reboot

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Hi all,

I am trying out the PCI Express High Performance reference design using the DE4-230 board. The board is inserted into Dell Precision T3400 machine with Windows xp installed.


I am following the steps described on Page 14 of AN-456-1.5, however, after I loaded the .sof file from another computer to the machine which is in bios mode, exit the bios, and do a ctrl-alt-del, the DE4 board did a power off and everything is refreshed.


If I didn't load anything to the board, and did a ctrl-alt-del after bios setup, it gives a normal soft reboot.


Has anyone have the same problem as well and how do you fix this? Thanks.

DE4 DMA read/write performance via PCIe

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Hi all,

I have modified the design in Using PCI Express on DE4 boards tutorial to test the performance of DMA Reads/Writes. What I did is simply replace the nios II processor and onchip memory to a FIFO with avalon MM slave interface. However, the speed I got is relatively low compared to the one mentioned in the PCIe High performance reference design (only about 100MB/s read/write for gen1 x4 compared to 875MB/s read and 890MB/s write).

I am wondering if anyone has done a similar testing as well and how's your performance? Could I have a look at your design and code if possible? Thanks.

Ting

DE2_115 Board not respond to ping request

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I have run the simple_socket_server example on ALtera De2_115 board , though my code run's without any error but wont respond to my ping request from other PC it says Host unreachable. i have attached the print screen of run time console of Eclips.

please help me out where i am wrong...

regards

kaushal
Attached Images

Ethernet autonegotiation

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I am just wondering what kind of procedures are running during the link establishment in 100Base-T ethernet in case auto negotiation is disabled (i.e. forced mode) at both ends of the ethernet connection (i.e. switch and NIC)?

Thanks,

Send packet or patterns to DE2-115 via Ethernet ?

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Hi all,
I've DE2-115 board, Cyclone IV E.
I want to test the Ethernet/ TSE by sending packets or frames.
this board has two ethernet port so it might be work to send loopback like in "an633: Implementing Loopback in Triple-SpeedEthernet Designs With LVDS I/O and GX Transceivers".
However, there is Packet generator & monitor ip cores for Cyclone IV.
Is there any experiment or tutorial could help with this?

The link below is a tutorial TSE by sending frames between the de2-115 ethernets. all the tutorial works well except the final stage after compilation there is Timequest problem.

ftp://ftp.altera.com/up/pub/Altera_M...rials/DE2-115/

I'm sure there are some of you try to test the ethernet in loopback internal or external or another way may be. could you share with us what you did and also the difficulties.

Thanks in advance to all of you.

DDR2 hard memory interface in ARRIA V

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Hello,
Its the first time I'm using ddr2 hard memory for altera .
can somebody explain the hard memory ddr2 interface?
what signals should I drive in : AFI I/Os ? what do I need it for?
afi_clk
afi_half_clk
afi_reset_n
what signals should I drive in :calibration/command I/Os
mp_cmd_clk_0_clk
mp_cmd_reset_n_0_reset_n
mp_rfifo_clk_0_clk
mp_rfifo_reset_n_0_reset_n
mp_wfifo_clk_0_clk
mp_wfifo_reset_n_0_reset_n
local_init_done
local_cal_success
local_cal_fail
local_refresh_req
local_refresh_chip
local_refresh_ack
oct_rzqin


Many thanks

Cyclon III + EPCS16 programming

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Hello,

I'm quite new to Cyclon FPGAs. Just got my new custom board made and was happy that it JTAGed using TerasicBlaster and FPGA works fine.

The problem is that program is not reloaded after powerup. In quartus programmer I only see one device whic is cyclon. I'm starting to wonder -

Is it actually possible to program EPCS16 using TerasicBlaster? Or is it just Cyclon FPGA thats gets the program.

I can't select EPCS16 as a device in Quartus Programmer, because the project is done for Cyclon and programmer says that sof file is incompatible.

How to get EPCS16 programmed, thats the question.

Any help apreciated, thank you!

Control Panel installation error ("Please make sure Quartus is installed")

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Hello,

I am trying to install the DE2-115 board under Windows 7 professional 32 bits.
While trying to run the Control Panel I get the error
"Please make sure Quartus is installed".

Quartus II is installed, and works very well (I have created and run on the board
2 small examples).
The USB blaster seems to function correctly, as reported by both Windows
and Quartus II (using Tools\Programming correctly lists the device).

The versions of both Quartus and Control Panel are those available for
download at Terasic (I also tried the DVD versions that came with the board,
same problem).

Following advice found on this forum, I have copied the jtag_client.dll and
dinkum_alt.dll to c:\Windows\System32 folder. Since then, I no longer
have the "Cannot load jtag_client.dll" error I had in the beginning.

Also following advice found on the forum, I have added the path to
nios2eds (...\nios2eds\bin and ...\nios2eds\bin\cygpath) to the system path.
(I did not reboot the computer since, but I don't think I should).

Still, I get that error while executing cotrol panel.

Thanks in advance for your help,
dpotop

Why has quartus stopped generating a time-limited sof file?

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My Quartus license expires this month (2013.02) but appears to be valid at the moment. But all of a sudden, today, it will not generate a time-limited sof file because I'm using the Triple Speed Ethernet core, which I haven't purchased yet but as far as I know, that shouldn't prevent the generation and use of the time-limited sof.

Thanks

How to get DE2i (NOT DE2) development board or similar board?

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I see very interesting solution -Terrasic Altera DE2i (NOT DE2)
It have Intel Atom processor and FPGA on one board. How to get it or similar board?

QSYS reference design for hard DDR3 controller for Cyclone V E

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I am looking for a reference design that is for Cyclone V E (not GX)
that shows the embedded hard memory controller connected to DDR3.
I looked through the projects for the Cyclone V dev kit and none of these seemed to fit the bill.

General questions about memories, configuration and FPGA systems.

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Hi,
I have done some research on the forum about the topic, but i have still some questions and want
to verify and sum up everything. In my questions about system configuration i will refer to Cyclone III
device family.

1. Some memories questions:

1a. Regarding SRAM memory for NIOS II code. I have seen people using two chips with 16 buses in
parallel giving 32 bit bus. I haven't verified that, but is NIOS II using 32 bit instructions ? So it would be
most efficent to use it like that. What about using only one chip ? Does it mean that NIOS would have
to read the memory two times - so the code could be executed slower ?
Also on this forum couple of people suggested for that not using A0 of the SRAM chip address.

I was looking for SRAM chips on digikey with 32 bit data bus already - they are quite expensive.

That's why it is better to use two 16 bit chips?

1.b. Is external SRAM memory with 10ns access time really much slower that for example internal
on-chip sram with 100 MHz clock?

1c. Regarding FLASH memory. There are two main types of flash NANDs and NORs. As farest i know
NAND have to be read/written in a page manner, while NORs can be accessed directly at desired
address. Is it always better to use NORs with FPGA? Or is there a purpose for using NANDs?

1d. What about the main difference between SRAM and DRAM ICs. I know that:
- SRAM usually has 6 transistors, and DRAM is one MOSFET + capacitor - so it's cheaper.
- SRAM doesn't have to be constantly refreshed so it consumes less power.
- And last thing that - please correct me if i'm wrong: SRAMs are faster, that's why they used as a
cache memory, but ultimately DRAM synchronous clock, bursts allow for higher bandwidth ?

1e.Is with those other memories the same consideration about NIOS 32 bit bus and instructions?

2. System configuration.
I have found out that EPCS configuration memories are quite expensive, that's why people usually
don't use them, right ?
Let's stick for a while with that memory anyway.

2a. I have read Cyclone III documentation regarding configuration. Active Serial is used with EPCS
chips. I read the remote configuration part, and it seems that i can store as many configuration files in
the epcs as i want. If the time comes i can using NIOS or my custom logic to reconfigure FPGA with
a different code, configuration. The documentation suggested that the address for the memory
configuration to start with is at the beginning of the EPCS.

"When used with configuration memory, remote update mode allows an application
configuration to start at any flash sector boundary."

Is that correct ?

2b. In the same documentation there was also smth about that configuration memory can mean not
only EPCS device but also parallel flash memory.

Does it mean that for example instead of using expensive EPCS i could use cheaper NOR flash or
what kind of flash ? and that i could have the same functionality, with remote configuration etc. using
Active Serial?

Ok just right now i have found here

http://www.altera.com/support/device...g-compare.html
that it can be used, and it's called AP. And that it needs CFI flash.
Any traps here?

2c. Can i in the same CFI Flash memory hold both more conifguration files and the code for NIOS II ?
There are some NIos commands like:
sof2flash, elf2flash, nios2-configure-sof,nios2-flash-programmer. Using those commands i can put
everything that i want in that flash in different address space?
It simply needs the pinout for FLASH and it knows how to use it?
I can use for the connection FPGA GPIO?

2.d In case of having nios code in the same FLASH, i should simply give NIOS the addres of the
beginning of the code for it in FLASH as a Reset Vector.

2.e. I haven't found that out - how is the code then copied to run from SRAM (for faster execution) -
Because i can assume that it could be run directly from that flash.

2.f. Before i started to write this post i was thinking about using some microprocessor to program the
FPGA using PS or FPP. I wanted to use some FLASH memory to store all different configurations for
the FPGA, and mircoprocessor would simply read the FLASH and program the FPGA.
I could use UART, USB or any different protocol i can come up with to upgrade for example the FPGA configuration
automatically.

However FPGA can receive data, reprogram the CFI Flash and reconfigure itself.
So correct me if i'm wrong but there is really no need for external uC?

//////////////////////////////////

Thanks for any answers to my questions, please address them by points and feel free to write some
other stuff that i should consider, read documentation etc.

best regards,
madness

Modelsim addition bug

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It seems that Modelsim truncates additions inappropriately. It appears that it uses the left hand side of an assignment to truncate the result of an additiion, even if that is not the final value. In the code below, the addition gets truncated to the length of the left hand side of the assignment first, and then further right shifted. It should preserve a bit length of the longest term in the addition plus one bit (for the carry). The truncation should only happen at the actual assignment.

module sandbox;
reg [8:0] apple;
reg [7:0] banana;

initial begin
banana = 8'hff;
apple = (banana + 1'b1)>>1;
banana = (banana + 1'b1)>>1;
$display("%x %x", apple, banana);
end
endmodule

The output is
080 00
While I expected
080 80

afi_half_clock of DDR3 SDRAM Controller with UniPHY

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Hi,

While configuring DDR3 controller GUI, I forgot to check "Enable Half Rate Clock option". Still I was able to connect other component's clock with afi_half_clk in Qsys. Qsys did not generate any error for this. The design also went through synthesis and PAR with out any error.

When I tried to download my elf on to the FPGA, I got an error saying could not download elf and not much information about the source of the error. And debugging this took some time.

Had Qsys reported an error, it would have been easy to fix it. Is there any reason why Qsys ignored this error?

Thanks

Viewing RAM configuration in Quartus 12 or 12.1

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Hi,
Suppose I use a 19 K x 32 RAM in true-dual port configuration. The Quartus is providing a summary of the number of M20Ks taken to construct the memory. However, I would like to get the internal detail of how Quartus organizes different M20Ks to construct the designated memory. Quartus may use some M20ks with say 1K x32 configuration and others in different configuration to provide an optimized count.
I think Quartus should be able to provide the internal implementation detail...How to get that from Quartus...? Anyone knows the settings, please share.

Thanks,
AlphaKh

Quartus - assembler not generating sof file

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Hi,
By default Quartus assembler generates sof file, however, it's no more in our case. Any particular settings that is causing this ? The Quartus I am using is not an evaluation copy.

Thanks,

external memory interface toolkit failure

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FWIW, the external memory interface toolkit appears to have an uncaught exception as follows (on Ubuntu 12.04.1 Linux). There are also some Linux processes left behind (see ps output below) which have to be killed before any quartus tool that uses the system console, such as the programmer or the EMIT, can be reused. This problem can become somewhat vexing because it takes the EMIT some time to start, and then one has to start over again whenever experiencing this issue again.

Internal Error: Sub-system: RDB, File: /quartus/db/rdb/rdb_table.cpp, Line: 1797
m_valid_max < m_window_max

Stack Trace:

0x7dc29: RDB_TABLE_DATA_VALID_WINDOW_ELEMENT::get_svg() const + 0x2b3 (db_rdb)
0x58752: RPWQ_TABLE::add_item(RDB_TABLE_OBJECT*, int, QStandardItem*, int) + 0xa42 (resr_rpwq)

0x58b8c: RPWQ_TABLE::add_item(RDB_TABLE_OBJECT*, int, QStandardItem*, int) + 0xe7c (resr_rpwq)

0x58b8c: RPWQ_TABLE::add_item(RDB_TABLE_OBJECT*, int, QStandardItem*, int) + 0xe7c (resr_rpwq)

0x5938b: RPWQ_TABLE::load_rdb_table(RDB_OBJECT*) + 0x54f (resr_rpwq)
0x5a605: RPWQ_PAGE_CONTAINER::open_table_type(RDB_OBJECT*) + 0xa3 (resr_rpwq)
0x6a6a5: RPWQ_PAGE_CONTAINER::open_page(QString const&) + 0x309 (resr_rpwq)
0x6a8d0: RPWQ_PAGE_CONTAINER::qt_metacall(QMetaObject::Call , int, void**) + 0x86 (resr_rpwq)
0x17fd53: QMetaObject::metacall(QObject*, QMetaObject::Call, int, void**) + 0x53 (QtCore.so.4)
0x190064: QMetaObject::activate(QObject*, QMetaObject const*, int, void**) + 0x274 (QtCore.so.4)
0x30d77: RPWQ_REPORT_TOC_VIEW::request_to_open_page(QString const&) + 0x45 (resr_rpwq)
0x31dc4: RPWQ_REPORT_TOC_VIEW::on_clicked(QModelIndex const&) + 0x232 (resr_rpwq)
0x61c24: RPWQ_REPORT_TOC_VIEW::qt_metacall(QMetaObject::Cal l, int, void**) + 0x108 (resr_rpwq)
0x17fd53: QMetaObject::metacall(QObject*, QMetaObject::Call, int, void**) + 0x53 (QtCore.so.4)
0x190064: QMetaObject::activate(QObject*, QMetaObject const*, int, void**) + 0x274 (QtCore.so.4)
0x7002a3: QAbstractItemView::clicked(QModelIndex const&) + 0x43 (QtGui.so.4)
0x70f980: QAbstractItemView::mouseReleaseEvent(QMouseEvent*) + 0x150 (QtGui.so.4)
0x75638c: QTreeView::mouseReleaseEvent(QMouseEvent*) + 0x9c (QtGui.so.4)
0x1aead9: QWidget::event(QEvent*) + 0x5d9 (QtGui.so.4)
0x5b70f3: QFrame::event(QEvent*) + 0x33 (QtGui.so.4)
0x656392: QAbstractScrollArea::viewportEvent(QEvent*) + 0x32 (QtGui.so.4)
0x710265: QAbstractItemView::viewportEvent(QEvent*) + 0x525 (QtGui.so.4)
0x753d1a: QTreeView::viewportEvent(QEvent*) + 0x14a (QtGui.so.4)
0x1798c1: QCoreApplicationPrivate::sendThroughObjectEventFil ters(QObject*, QEvent*) + 0x91 (QtCore.so.4)
0x1489a3: QApplicationPrivate::notify_helper(QObject*, QEvent*) + 0x93 (QtGui.so.4)
0x151104: QApplication::notify(QObject*, QEvent*) + 0x18f4 (QtGui.so.4)
0x17947b: QCoreApplication::notifyInternal(QObject*, QEvent*) + 0x7b (QtCore.so.4)
0x14b9a2: QApplicationPrivate::sendMouseEvent(QWidget*, QMouseEvent*, QWidget*, QWidget*, QWidget**, QPointer<QWidget>&, bool) + 0xf2 (QtGui.so.4)
0x1dafe6: QApplication::x11ProcessEvent(_XEvent*) + 0x1966 (QtGui.so.4)
0x17850d: QEventLoop::processEvents(QFlags<QEventLoop::Proce ssEventsFlag>) + 0x4d (QtCore.so.4)
0x17879a: QEventLoop::exec(QFlags<QEventLoop::ProcessEventsF lag>) + 0xaa (QtCore.so.4)
0x17a811: QCoreApplication::exec() + 0xb1 (QtCore.so.4)
0x148317: QApplication::exec() + 0x27 (QtGui.so.4)
0x633f: __gxx_personality_v0 + 0x373 (quartus)
0x23208: msg_main_thread(void*) + 0x18 (ccl_msg)
0x5e5e: thr_final_wrapper + 0xe (ccl_thr)
0x23f1b: msg_thread_wrapper(void* (*)(void*), void*) + 0x6c (ccl_msg)
0x1591d: mem_thread_wrapper(void* (*)(void*), void*) + 0xdd (quartus)
0xffd8: err_thread_wrapper(void* (*)(void*), void*) + 0x2a (ccl_err)
0x62ba: thr_thread_wrapper + 0x2f (ccl_thr)
0x367c7: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xb7 (ccl_msg)
0x6411: __gxx_personality_v0 + 0x445 (quartus)
0x194d3: __libc_start_main + 0xf3 (c.so.6)
0x61f1: __gxx_personality_v0 + 0x225 (quartus)
End-trace
Quartus II 32-bit Version 12.1 Build 177 11/07/2012 SJ Full Version


PID TTY TIME CMD
2157 pts/1 00:00:15 quartus
2194 pts/1 00:00:02 quartus_sh
2197 pts/1 00:00:00 system-console
2198 pts/1 00:00:00 sh
2199 pts/1 00:00:07 java
2355 pts/1 00:00:00 ps
3650 pts/1 00:00:00 bash

USB Blaster not working properly

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So, I need to get my Board Programmed for a project due next week. I've installed the drivers and everything has seemed to work fine. I went to start programming the board, and when I tried to connect to the USB Blaster adapter it could not be found. In the "Hardware Select" Menu It said there was "No Hardware". I thought, that's not right I just installed the hardware. Then I went to Add Hardware to see if that might be what went wrong. Nope. There it only said "Hardware Type" "ByteBlasterMV or ByteBlaster II" or "Ethernet Blaster". Neither of which could be used in my case. This was getting a little ridiculous. I've been scouring the internet looking for a solution, but I can't seem to find one.

Some Information:
I think that I installed the correct driver, it shows up as "Altera USB-Blaster" in Device Manager.
I am using Windows 7 64bit Proffesional version.
I have tried Quartus II 6.0, just the Quartus II 12.1 stand-alone programmer, and Quartus II 12.1 subscription edition.
I am trying to use this with the Altera Stratix II GX board.
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