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aud_ws_in signal in SDI audio extractor

February 7, 2013, 9:22 pm
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Hi

The aud_ws_in signal in SDI audio extractor is used as a reference word select signal to align the serial outputs of multiple audio extractors.
(please see SDI use guide for the original description).

So, I expect to see aligned serial audio data if I connect a clock of 48KHz to the aud_ws_in of several audio extractors.
(My bit clock for the audio is 3.072MHz)

However, when I really do this, I don't think I have seen seen aligned serial audio data from signaltapII. Please see the attached siganltapII waveform.

The embedded audio data in SDI are all 1KHz tone from a test pattern generator. So their serial data should be the same. All I need is to align data between multiple audio extractors. Should I add FIFO to do this?

Does anyone have some suggestions about my question? Thanks.
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Interfacing STRATIX 3 FPGA with RS485 and RS232.

February 7, 2013, 10:39 pm
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Hello sir,

I am designing a hardware multipurpose board using STRATIX 3 FPGA(EP3SL340F1517C3N). I have never worked on Fpga practically. So kindly let me know how to interface this Fpga with RS485 AND RS232. Can FPGA be directly connected to RS485 or any intermediate block is required? Kindly reply in detail.

Thank you
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SGDMA's alt_avalon_sgdma_construct_mem_to_mem_desc_burst driver

February 7, 2013, 10:55 pm
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Hi,

I could not find much information about alt_avalon_sgdma_construct_mem_to_mem_desc_burst device driver. I have been using alt_avalon_sgdma_construct_mem_to_mem_desc driver in my applications. Does burst driver has any advantages over regular driver. Even the IP user guide does not describe the use of this driver.

Thanks
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Displayport Auxiliary Channel Receiver

February 8, 2013, 12:38 am
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Hi all,

I'm trying to decode a DisplayPort Auxiliary Channel signal with my EP4CGX22. I'm using the input termination as required by the standard:

DP_AUX_RX.jpg

C_aux is 100n and Vbias_RX is 3.3V.

The measured voltage at the DP connector looks like this:

Signal_Sink_Connector.jpg

and at the FPGA pin:

Signal_FPGA_Pin.jpg

The FPGA pin is configured as an input only and has the I/O-Standard 3.3V LVCMOS. Obviously this doesn't work. Does anyone know what could be wrong or has already any experience connecting DisplayPort to an FPGA? There are expansion boards for FPGA eval boards where they have the exact same schematic and I guess it works there. Do I need to specify another I/O-Standard? And if yes, which one?

Thanks,
Oliver
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Port Connection Error: Output must be connected to a structural net expression...?

February 8, 2013, 3:19 am
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Hi All,

I'm getting a frustrating error that appears to be a incorrect syntax involving wires vs reg but i've tried all combinations and can't solve it. So i'm after any help you can please provide. I'll try keep this concise.

WHAT I'M DOING
  1. A module that i'm adapting VGA_Control; i'm trying to connect it to my top model. No need for you to worry about specifics i think atm.
  2. When i try instantiate the module, i get the error for each output of the module.
  3. I've ensured that all the module outputs are connected to wires, and this is what my understanding of the IEEE section 12.3.9 is.


THE ERROR
Quote:
Error (10663): Verilog HDL Port Connection error at TPAD_Basics.v(365): output or inout port "vga_clk" must be connected to a structural net expression
I get this error for all the output signals of that module.

THE INSTANTIATION - Cause of Errors
Code:
wire wVGA_Clk;
wire [7:0]  oVGA_R;      // VGA Red
wire [7:0]  oVGA_G;      // VGA Green
wire [7:0]  oVGA_B;      // VGA Blue
wire wLCD_DEN;
wire wLCD_NCLK;
wire wVGA_HS;
wire wVGA_VS;

VGA_Control VGA2
(
  clk(wVGA_Clk),
  reset_n(KEY[0]),
  // VGA export interface
  data_in({wRed, wGreen, wBlue}),
  iDataValid(1'b1),
//  vga_clk(LCD_NCLK),
  vga_hs(),
  vga_vs(),
  vga_de(LCD_DEN),
  vga_r(oVGA_R),
  vga_g(oVGA_G),
  vga_b(oVGA_B)
);
assign LCD_DEN = wLCD_DEN;
//assign LCD_NCLK = wLCD_NCLK;
assign VGA_HS = wVGA_HS;
assign VGA_VS = wVGA_VS;
assign LCD_DIM = 1'b1;

assign  LCD_R = oVGA_R[7:2];
assign  LCD_G = oVGA_G[7:2];
assign  LCD_B = oVGA_B[7:2];

PORT DECLARATIONS IN THE MODULE (VGA_CONTROL)
Code:
// global signal
input      clk;
input      reset_n;
input [23:0]    data_in;
input      iDataValid;
 
  // VGA export interface
output    vga_clk;
output reg  vga_hs;
output reg  vga_vs;
output reg  vga_de;
output reg [7:0] vga_r;
output reg [7:0] vga_g;
output reg [7:0] vga_b;
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vhdl code for tic tac game

February 8, 2013, 3:40 am
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i am going to do project on simple game tic tac on vhdl. I am using 9 switch and and nine led for display and 2 led to indicate the winner. i am thinking to distinguish to play by flashing of LED. if first player press the switch than led will be on and when 2nd player press the switch than led will start to flash for infinite time. So any one please help me for this project. i am quite new for vhdl.
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Clock generate by C-Code

February 8, 2013, 4:11 am
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Can it be possible to generate a Clock of 1 Mhz/ 125 Kbps from Code in eclips environment.

I have altera DE2_115 board, working on clock rate of 50Mhz

regards

kaushal
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Button press to change state machine - "Can't resolve multiple constant drivers..."

February 8, 2013, 4:34 am
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I'm trying to set up a small demo to make a stepper motor move in various ways in which I'll need a series of buttons to control the action of the motors.


To do this I'm using a state machine to perform the required actions depending on the button press, however some of the states aren't continuous and need to drop to another state after completion of the action. The trouble is I'm getting errors. I kinda understand why the compiler doesn't like it, but I don't know how to circumvent the issue, so suggestions welcome.

Also, it would appear that I'm not getting the desired clock signal on my step_clk output, which also confuses me greatly.




Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;




entity motor_demo is
    port(    clk: in std_logic;
       
            RST, EN, CTRL, HALF, CW, Step_clk: out std_logic;
            sw: in std_logic_vector(0 to 4)
            );
end motor_demo;




architecture stm of motor_demo is


    type motor_action is (STOP, CWISE, CCWISE, CW_45, CCW_180);
    signal motor_state: motor_action := CWISE;
   
    signal stepcount: integer := 0;
    signal clk_div: std_logic;


begin


    -- Clock divider for stepper action
    clk_divider: entity work.clk_divide port map(clk, clk_div);
   
   
    process(sw) is
    begin
   
        case sw is
            when "01111" =>
                motor_state <= CWISE;
            when "10111" =>
                motor_state <= CCWISE;
            when "11011" =>
                motor_state <= STOP;
            when "11101" =>
                motor_state <= CW_45;
            when "00001" =>
                motor_state <= CCW_180;
            when others =>
                motor_state <= STOP;
        end case;
   
    end process;
   


    process(clk_div, motor_state) is
    begin
   
        if rising_edge(clk_div) then
       
            case motor_state is
                when STOP =>
                    step_clk <= '0';
                    stepcount <= 0;
                   
                when CWISE =>
                    step_clk <= clk_div;
                    CW <= '1';
                   
                when CCWISE =>
                    Step_clk <= clk_div;
                    CW <= '0';
                   
                when CW_45 =>
                    CW <= '1';
                    if(stepcount < 49) then
                        step_clk <= clk_div;
                    else
                        motor_state <= STOP;
                    end if;                   
                    stepcount <= stepcount + 1;
               
                when CCW_180 =>
                    CW <= '0';
                    if(stepcount < 199) then
                        step_clk <= clk_div;
                    else
                        motor_state <= STOP;
                    end if;                   
                    stepcount <= stepcount + 1;                   
       
            end case;
       
        end if;
   
    end process;
   


end stm;

Code:
Error (10028): Can't resolve multiple constant drivers for net "motor_state.STOP" at motor_demo.vhd(52)
Error (10029): Constant driver at motor_demo.vhd(31)
Error (10028): Can't resolve multiple constant drivers for net "motor_state.CWISE" at motor_demo.vhd(52)
Error (10028): Can't resolve multiple constant drivers for net "motor_state.CCWISE" at motor_demo.vhd(52)
Error (10028): Can't resolve multiple constant drivers for net "motor_state.CW_45" at motor_demo.vhd(52)
Error (10028): Can't resolve multiple constant drivers for net "motor_state.CCW_180" at motor_demo.vhd(52)
Error (12153): Can't elaborate top-level user hierarchy
Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 7 errors, 5 warnings
Edit: So apparently if I put the 'sw' case statement within 'if rising_edge(clk_div)' statement I don't have a problem, but the only downside is that's not ideal if the clock were to be going a few Hz.
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Byte Enabled RAM Issue

February 8, 2013, 7:53 am
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Hi,

I am facing an issue while using byte enable memory. My memory is
  • 128-bit wide
  • dual clocked
  • read clock runs at 400MHz while write clock runs at 200MHz
  • Its depth is only 2 i.e. read and write addresses are 1-bit wide only
  • Forced to map on M9Ks
  • Read port is connected to 200MHz clock (instead of making a toggling signal using 400MHz clock)


This RAM is written only once, 2 bytes at a time, during run time and then I read it for a long period. So I used total 16 clock cycles to fill complete. I have verified my logic in simulation but after synthesis and debugging using SignalTap I found that the RAM outputs are always zero. Input behavior is somewhat similar to the scenario i tested in simulation. Hope u may got what i am trying to do. I have checked the synthesis warning and I didn't found anything related to this RAM.

Please try to correct me where did I make the violation of rule(s) related to memory usage.
Thanks In Advance
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VIP demo with PAL on NEEK (EP3C25F324C8)

February 8, 2013, 9:39 am
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Hello,

I'm actually an engineering student and I have a project (video processing on altera). Based on VIP demo "AN427" I'm trying to build a system that streams a PAL video input on a 800x600 VGA screen (later DVI 800x600).
I have some issues since I'm blocked

1. I get this message while programming the device :

Code:
Info: SRAM Object File  C:/Users/Mohamed/Desktop/TEST_Altera_VIP/Video_System_time_limited.sof  contains time-limited megafunction that supports OpenCore Plus feature  -- Vendor: 0x6AF7, Product: 0x0003
Info: SRAM Object File  C:/Users/Mohamed/Desktop/TEST_Altera_VIP/Video_System_time_limited.sof  contains time-limited megafunction that supports OpenCore Plus feature  -- Vendor: 0x6AF7, Product: 0x00B1
Info: SRAM Object File  C:/Users/Mohamed/Desktop/TEST_Altera_VIP/Video_System_time_limited.sof  contains time-limited megafunction that supports OpenCore Plus feature  -- Vendor: 0x6AF7, Product: 0x00B7
Info: SRAM Object File  C:/Users/Mohamed/Desktop/TEST_Altera_VIP/Video_System_time_limited.sof  contains time-limited megafunction that supports OpenCore Plus feature  -- Vendor: 0x6AF7, Product: 0x0003
Info: SRAM Object File  C:/Users/Mohamed/Desktop/TEST_Altera_VIP/Video_System_time_limited.sof  contains time-limited megafunction that supports OpenCore Plus feature  -- Vendor: 0x6AF7, Product: 0x00B1
Info: SRAM Object File  C:/Users/Mohamed/Desktop/TEST_Altera_VIP/Video_System_time_limited.sof  contains time-limited megafunction that supports OpenCore Plus feature  -- Vendor: 0x6AF7, Product: 0x00B7
I don't know where the problem is !

2. I get either a white or black screen on VGA and I tried the terasic exemple "VGA TV" and works just fine with NTSC input. I attached my Quartus 10.0 project files so you can help out with what I've done wrong and here is a screen shot :

33dxv2g.jpg


I desperatly need your help guys please !!
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Power schematic for Cyclone IV

February 8, 2013, 11:13 am
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Hi, i am designing a very simple development board and need some tips on Cyclone IV power design. The board will be used for learning purposes with simpled designes. It is not aimed for very fast deisgns (100Mhz max i would say). The 3.3V, 2.5V and 1.2V are generated with standard 1117 LDOs with a bypassing 22uF tantalum capacitor. For decoupling i am using a 100nF x7R capacitor at each pin. My doubt is on the VCAA and VCCD desing.

Is the following schematic a reasonable circuit? The 1.2V is used fo VCCINT. The filter is a ferrite bead, i still have to chose the 100Mhz impedance. I added the 4.7uF X5R capacitor but still not sure if is really needed... the 2 100nF capacitors at VCAA adn VCCD are the decoupling capacitors at the pins.

power_ach.jpg

Any sugestion is more than appreciated. The board is just for very low level (and low cost) FPGA design and learning.

Regards,

LR
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ModelSim-Altera Starter Edition (Free) - Download Failure

February 8, 2013, 11:13 am
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I am a teaching assistant for a class using the Quartus II Web Edition installer for the Quartus II Web Edition (free) with Cyclone IVE device family and the ModelSim-Altera Starter Edition (free). A student running on 64 bit Windows 7 is getting an error message during installation that download of the Starter Edition has failed. This happens repeatedly, and the installation fails every time. The student has space on his hard drive for the installation and has the proper permissions to install the software. All other software appears to download without any problems. Does anyone have any clues as to what might be causing this issue or how to resolve it?
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Qsys-based example design for a Cyclone V GX Dev Board

February 8, 2013, 11:16 am
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Hi,

I'm struggling to get DDR3 accesses working on the dev board and am wondering if anyone has a Qsys-based design working yet. Basically, I get an error when I attempt to download my .elf and receive the following message when I attempt to control the NIOS using System Console:

error: com.altera.systemconsole.internal.plugin.jtag.oci. Nios2DebugException: Target is broken and needs to be reset
while executing

The EMIF toolkit seems to indicate that it can access the DDR3 ok and the provided example design (DDR3A) indicates a pass. The DDR3A example design appears to be pretty simplistic in that it doesn't use bursting (from what I can see in SignalTap). I initially thought that perhaps the DDR3 timing parameters were wrong. When I 'grep' through files in the example design, several files contain parameters (of which some are different) and none of them correspond to the speed grade of the DDR3 on the actual board. That said, I've tried a bunch of different combinations (Micron datasheet, parameters provided with kit) with no success.

Any help appreciated.
Thanks.
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Any examples for set_instance_assignment -name DUPLICATE_ATOM

February 8, 2013, 12:13 pm
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I am trying to speed up my design. I have a large fan out clock enable signal that goes through a combinatorial logic. I do not want to pipeline the signal. I see that it is possible to duplicate combinatorial logic. It seems simple enough but I do not get why I need to specify entity name. I am bit sure what the entity name refers to.

So any examples or alternative ways to accomplish the same thing. Besides duplicating hdl code.

Quote:
December 2012 Altera Corporation Quartus Settings File
Reference Manual
DUPLICATE_ATOM
Directs the Compiler to duplicate the source node, and uses the new duplicate node to
fan out to the destination node; the original source node no longer fans out to the
destination node. Use the Value field to specify the name of the duplicate node.
Syntax
set_instance_assignment -name DUPLICATE_ATOM -from <from> -to <to> -entity <entity name> <value>
Also can I specify wildcard characters like is done is the SDC files like this:
set_instance_assignment -name DUPLICATE_ATOM -from "*lpm_counter_component|cntr_lok:auto_generated|co unter_reg_bit[1]"
-to "*dcfifo_lql1:auto_generated|rdemp_eq_comp_msb_aeb " -entity <entity name>"dupname*"
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Verification failed for device number (Quartus programmer, verify option) [SOLVED]

February 8, 2013, 1:27 pm
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Hi,

I have search the web and found couple of places speaking about it (Verification failed for device number (Quartus programmer with verify check)) but still I'm not satisfy with what I have read :(

We have boards with cyclone 4 + flash (EP4CE115 + EPCS64)

We are not able to do a verify of a .jic file?

We are using quartus web 12.1 inside a Windows 7 inside a VMWare and it just fail with this message:
209027 Verification failed for device number 1

The VM was running on Mac OS X.

SOLUTION OF MY PROBLEM: Rebooting the Windows with boot camp fix the problem of being able to verify a jic file with the programmer on a cyclone 4.

This post is simply to save some times in case other people have the same error
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VIP Frame Buffer Locks

February 8, 2013, 3:05 pm
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Periodically, especially immediately following a Reset to my VIP system, one or the other of the 2 independent frame-buffers hangs up. I have SignalTap on the DoutValid and DoutReady signals throughout the QSys system. When I see the issue occurring (characterized by no video output to monitor) this shows that the DoutReady signal driving back into the FrameBuffer is always High, but the DoutValid from the FrameBuffer never toggles. My only option here is to reset the whole system. Normally, this solves the issue, but it is not a viable workaround.

Do you have any thoughts on what I could be doing wrong and how to resolve this?
My system includes no Ctrl Syncs. Might the solution to this issue involve the use of Ctrl Syncs? I guess my understanding about where/when to place a Ctrl Sync into my system is a little confusing to me.
Could incorrect reset connectivity cause a problem?
How should I be debugging it?

Thanks
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vhdl for reading pwm

February 8, 2013, 3:56 pm
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hi i'm using ultrasonic sensor to detect water level and implement on De2 board. The output of the sensor is in pulse width which is 147uS/inch. Can anyone guide me how i can write the vhdl code for this output if i want to detects to 8 level? Let say im using 50Mhz clock on FPGA then (147us/20ns) i will get 7350 count per inch.
can anyone help me what should i do so it can detects 8 levels of water level. tq
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Walkthrough Jam STAPL Player / JTAG / GPIO / ARM

February 8, 2013, 4:21 pm
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My problem is that the verify option with the jamplayer fails (Exit code = 11... Device verify failure), see at the end the output...


But to add more context and extra details here my walkthrough:


Let's start by stating my goal: Program an Cyclone 3 or 4 / flash (EP3C16 or EP4CE115 / EPCS16 or EPCS64) from a ARM embedded device by using GPIOs.


From internet search and reading the JAM player was our stating point:


http://www.altera.com/support/device...m/tls-jam.html


More precisely I started with this version of the source code:


https://www.altera.com/download/lega...dnl-player.jsp


I had to fix some problem to compile on Linux:
Build instructions:
- unzip jp_25.exe
- cd jp_25/source
- Rename all files with lowercases:
- for f in `find`; do mv -v $f `echo $f | tr '[A-Z]' '[a-z]'`; done
- chmod 664 *
- vim jamport.h
- Change "#define PORT WINDOWS" TO "#define PORT EMBEDDED"
- Remove the io.h, conio.h, process.h to move them inside the "PORT == WINDOWS" like:
if PORT == WINDOWS
#include <windows.h>
#include <io.h>
#include <conio.h>
#include <process.h>


- To remove the warning :vim jamstub.c +1328 and replace the %ld to %d


- run direct on ARM otherwise use a cross compiler:
gcc -o jamplayer *.c
./jamplayer --help


Here JTAG tutorial that help nicely to start with JTAG:
http://www.fpga4fun.com/JTAG.html


#### Adding my own implementation to communicate to the JTAG from jamstub.c


void initialize_jtag_hardware()
{
// Init the GPIO file descriptor and the rest.
// Add super test that help a lot for debugging the HW the "checkboard pattern" (1010101010) see cyclone handbook for the description.
// Here the short version:
// 1- Do a JTAG reset (tms=1 for 5 clock of the TCK)
// 2- Move to SHIF_IR state
// 3- Set 10 1 in TDI
// 4- Each time a 1 is written on TDI it possible to read something on the TDO and the pattern will be (1010101010)
}


void close_jtag_hardware()
{
// Close all the FD and the rest for GPIO.
}


int jam_jtag_io(int tms, int tdi, int read_tdo)
{
int tdo = 0;


if (!jtag_hardware_initialized)
{
initialize_jtag_hardware();
jtag_hardware_initialized = TRUE;
}


if (specified_com_port)
{
printf("NOT SUPPORTED\n");
}
else
{
// JTAG One tick of the jtag clock.
// Create my own GPIO interface to interact with the JTAG pins: TCK, TMS, TDI and TDO.
// ex: set TCK = 0 set TMS & TDI sleep for half period read TDO. set TCK to 1 sleep half period set TCK = 0 (Just to start and end to zero, looked cleaner on the oscilloscope)
}


if (tck_delay != 0) delay_loop(tck_delay);


return (tdo);
}




##### Create a JAM file
1- Compile your quartus project it result in sof file
2- Convert the sof file to jic Menu File / Convert Programming Files set:
3- Programming file type: jic
4- Configure device: EPCS64
5- Add Device for the Flash loader: Cyclone IV E -> EP4CE115
6- Add File to the SOF data
7- Click Generate to have your JIC file
8- Open the programmer
9- add jic file
10- check program/configure + verify + blanck check
11- Go Menu File / Create JAM, etc
12- click OK


#### Program your FPGA with your JAM file
The first thing to understand with the JAM player is that you need to program SFL (Serial Flash Loader) to by able to program the FPGA.
1- jamplayer -aconfigure file.jam
If you add the verbose in the source code, search for verbose and define to one could be easy way:
Here the output of the jamplayer:


./jamplayer -aconfigure BS_C4_SOME.jam
Jam STAPL Player Version 2.5 (20040526)
Copyright (C) 1997-2004 Altera Corporation


CRC matched: CRC value = B874
Export: key = "JAM_STATEMENT_BUFFER_SIZE", value = 3547
NOTE "CREATOR" = "QUARTUS II JAM COMPOSER 12.1"
NOTE "DATE" = "2013/02/07"
NOTE "DEVICE" = "EP4CE115"
NOTE "FILE" = "BS_C4_SOME.jic"
NOTE "TARGET" = "1"
NOTE "IDCODE" = "020F70DD"
NOTE "USERCODE" = "FFFFFFFF"
NOTE "CHECKSUM" = "4B533CE2"
NOTE "SAVE_DATA" = "DEVICE_DATA"
NOTE "SAVE_DATA_VARIABLES" = "V0, A12, A13, A25, A42, A93, A43, A92, A94, A95, A103, A104, A105, A109, A111"
NOTE "STAPL_VERSION" = "JESD71"
NOTE "JAM_VERSION" = "2.0"
NOTE "ALG_VERSION" = "63"
root@BrainsightNIRS:~/JAM#
root@BrainsightNIRS:~/JAM# ./jamplayer -aconfigure BS_C4_SOME.jam
Jam STAPL Player Version 2.5 (20040526)
Copyright (C) 1997-2004 Altera Corporation


CRC matched: CRC value = B874
Export: key = "JAM_STATEMENT_BUFFER_SIZE", value = 3547
NOTE "CREATOR" = "QUARTUS II JAM COMPOSER 12.1"
NOTE "DATE" = "2013/02/07"
NOTE "DEVICE" = "EP4CE115"
NOTE "FILE" = "BS_C4_SOME.jic"
NOTE "TARGET" = "1"
NOTE "IDCODE" = "020F70DD"
NOTE "USERCODE" = "FFFFFFFF"
NOTE "CHECKSUM" = "4B533CE2"
NOTE "SAVE_DATA" = "DEVICE_DATA"
NOTE "SAVE_DATA_VARIABLES" = "V0, A12, A13, A25, A42, A93, A43, A92, A94, A95, A103, A104, A105, A109, A111"
NOTE "STAPL_VERSION" = "JESD71"
NOTE "JAM_VERSION" = "2.0"
NOTE "ALG_VERSION" = "63"
Device #1 IDCODE is 020F70DD
configuring SRAM device(s)...
DONE
Exit code = 0... Success
Elapsed time = 00:22:47




The second step is to program the FPGA that will perform an erase, program and verify and this last step is my problem it fail the verify??
Resetting the FPGA reset it properly with the correct code but fail the verify?


Here the output:
./jamplayer -aprogram BS_C4_SOME.jam
Jam STAPL Player Version 2.5 (20040526)
Copyright (C) 1997-2004 Altera Corporation


CRC matched: CRC value = B874
Export: key = "JAM_STATEMENT_BUFFER_SIZE", value = 3547
NOTE "CREATOR" = "QUARTUS II JAM COMPOSER 12.1"
NOTE "DATE" = "2013/02/07"
NOTE "DEVICE" = "EP4CE115"
NOTE "FILE" = "BS_C4_SOME.jic"
NOTE "TARGET" = "1"
NOTE "IDCODE" = "020F70DD"
NOTE "USERCODE" = "FFFFFFFF"
NOTE "CHECKSUM" = "4B533CE2"
NOTE "SAVE_DATA" = "DEVICE_DATA"
NOTE "SAVE_DATA_VARIABLES" = "V0, A12, A13, A25, A42, A93, A43, A92, A94, A95, A103, A104, A105, A109, A111"
NOTE "STAPL_VERSION" = "JESD71"
NOTE "JAM_VERSION" = "2.0"
NOTE "ALG_VERSION" = "63"
Device #1 is EPCS64
erasing ASC device(s) in sector mode...
programming ASC device(s) in sector mode...
CRC verify ASC device(s) in sector mode...
Device verify failure
Exit code = 11... Device verify failure
Elapsed time = 00:27:13



Any ideas about that: Exit code = 11... Device verify failure???



Cheers,

-KA
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Nios II timer and erroneous usleep() results

February 8, 2013, 7:02 pm
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I am using a Nios II processor running at 50MHz with a timestamp timer and a system timer. I am noticing that the usleep() function is not returning expected time delays. For the code:

frame_start_time = alt_timestamp();
usleep(400);
frame_stop_time = alt_timestamp();
delay = frame_stop_time - frame_start_time;

I get a delay value of 47,342 where I would expect a value of 20,000. Am I misunderstanding how the alt_timestamp() counter is counting or how the usleep() function operates? The alt_timestamp() function does produce expected timing results in another location in the code, I am just not able to get expected delays using the usleep() function.
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Cyclone IV E JTAG issues - VCCA voltage level

February 9, 2013, 1:20 pm
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Hi all, I have a custom board with Cyclone IV E (EP4CE115-F484).

I am trying to access it via JTAG from Quartus, but keep receiving the "Error: Can't access JTAG chain".

I check the Quartus and USB Blaster by scanning a chain on a devkit board and it worked fine. So I assume my SW and USB BLASTER is ok.

One of the issues on my board is that I need to run banks 1,2,5,6 at 1V8 and bank 3,4,7,8 at 3V3.

Thus all the banks are powered. AND the JTAG bank (believe it is Bank1 is powered at 1V8) - QUESTION: Is this OK?
My pins to the Blaster header are TCK pulled down by 2k7, TDI and TMS pulled up to 1V8 by 10k. Tdo just comes from the Cyclone
Pin4 and Pin 6 on blaster is tied to 1V8 - QUESTION: Is this OK?
and of course pin 2 and 10 to GND.

The other issue I might have had is that the VCCA is also powered to 1V8. I read in the handbook somewhere that it should be 2V5.- QUESTION: Is this OK?
I doubt if this is the problem, since I have now changed the 1v8 rail to 2v5 (this all the pin that used to be at 1v8 is now at 2v5) and the problem persists

I have probed all 4 signals and there is activity on them all.
HOWEVER:
TCK only switches to almost 1V2 (which is the VccINT level) - the clock is normally low (due to the pull down)
TDO is normally low and switches high (2V) during config (not quick data pulses but more like high for the config attempt off about 330ms, then low for 26ms, then high again for 72ms, thereafter low)
TDI is normally high(pull up to 2v5) and switches during config. The pattern is: High, then low for 68ms, then high for 285ms then low again for 86ms, thereafter high.
TMS is normally high(pull up to 2v5) and switches during config. The pattern is low at the same time as TMS for 82ms, then high for 283ms then low again for 80ms.

Triggering the scope on the TMS signal, the following is obvious:
1. The TDO is almost a exact inverse of the TMS.
2. The TMS signal frames the TDI signal as expected
3. The TCK signal is only active during the first portion of the TMS signal, but at much lower voltage.

The other config signals are:
nCE = Gnd
MSEL 0 - 3 = 0100
nStatus pulled to 1V8 via 10k
ConfDone pulled to 1V8 via 10k
nConfig pulled to 1V8 via 10k

ACTUALLY, JUST REALISED A POSSIBLE CAUSE:
The device text on top is ep4ce15f23i8LN - meaning 1V0 Core voltage. I am driving it at 1V2.
Could this be it?
Have not seen any smoke coming out.:o

Please, any hints, tips, words of wisdom are welcome.
I have done many FPGA boards in my career, but this one has me boggled.

If need be, I can attach config section of schematic and maybe some photos of the scope signals. But let see if their is something VERY STUPID I am doing (that's except for the 1V2 on 1V core)

Regards
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