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Serial Presense Detect and Altera Memory Controller IP

May 29, 2015, 7:56 am
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Hi all,

I am going to work on a project on a Stratix V using the standard Altera HPC DDR3 memory controller and UniPHY. I need to detect how many DIMMs are plugged in and their sizes. The timing parameters should be fixed though. So do you guys know if the Altera memory controller supports the Serial Presence Detect protocol? Or do I have to implement this outside?

thanks

-G
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CPLD as a pass through (Input pin directly goes to Output pin) good or bad idea?

May 29, 2015, 9:09 am
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Hi everyone,

I have a custom board created by another person. The board contains a Netburner processor that is connected to a CPLD. The CPLD is then connected to a DDS.

The DDS uses a SPI interface and the Netburner is able to send SPI commands, however, there is a CPLD in between these two devices. The person who created board
has the idea that we can use the CPLD as a pass through device, where we simply connect the Input to the Output.

However, after reviewing the schematic, the SPI clock is NOT connected to a dedicated clock input and uses a regular I/O pin.

My understanding is that in good designs we have to first register any inputs that goes into a CPLD/FPGA device. In this case, I won't be able to do that because the clock is not
attached to a clock tree and altera will bark at me if I specify it as a clock. My CPLD also contains another external clock but it runs a lot slower than the Netburner SPI clock (10 MHz vs 66 MHz).

I haven't tried and I'm about to, but for my learning sake why do I have a gut feeling that this isn't a good idea? I think I've tried it before where I don't register my inputs (other than asynchronous resets) and the data would get attenuated or lose power as it propagated in my design.
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OpenCL memory banks

May 29, 2015, 11:48 am
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Hello,

From the hello world example, I got:
CL_DEVICE_GLOBAL_MEM_SIZE = 4294967296,
which means 4GB global memory.
I am using a nallatech 385a7 board, so why the global memory size I got from the example is not 8GB instead? (2banks of 4GB). Is it possible to use all the 8GB memory on board?

Thanks.
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Volume Cyclone V price

May 29, 2015, 12:49 pm
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Hello all,

For volume quantity what can cost an FPGA that cost 180$ in single unit? Can it reach 20$ target price?

I bought an entire dev-board with that FPGA at that price so it will for sure cost much less..

Thanks
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Problems with Eclipse Build Tools and Model Sim

May 29, 2015, 1:59 pm
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I am at the point where I am beginning to test some of the code I have written in the Eclipse GUI. I am trying to simulate this code on an RTL level using Model Sim. When I select Nios II model sim on the run tab, I receive a pop-up window with the following error attached.



I am running the web edition of Quartus. Is this the issue? Does anyone have any ideas?
Attached Images
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Problems accessing memory with Avalon MM Master Templates

May 30, 2015, 7:23 am
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Hello everyone,

I'm a University student and i have been working on NIOS and Qsys for a few months now, my objective was to create a custom instruction that was able to read at least 3 or more variables from memory. I have used the Avalon MM Master Templates from Altera website but i have some issues...

I need to read 3x32bits of data(3 variables) and for that i'm currently using 1 burst of 128 bits, it's the only setting that seems to work, i have tried 3 burst of 32 bits but it without success. The problem now is that for some reason the 96 bits data that i need either come in the beginning of the word (X,Y,Z,?) or in the end (?,X,Y,Z).

Does anyone have some idea of what could be wrong with the Avalon interface or give me some clues on how to enable Burst Reads?

Thank You!
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HPS power is being analyzed for a device with an HPS without HPS power

May 31, 2015, 6:42 am
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Where is HPS Power Calulator Dialog Box in QII web edition?
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Altera Quartus II bin directory

May 31, 2015, 8:41 am
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Hi all,
I am developing a program that uses Altera Quartus II bin directory to synthesis, place and route ... etc. using the command line in the background. My question is can I extend the bin directory to be able to use it in new computers even if Altera Quartus II is not installed? if yes How ? and Do I need any license for that?
Thank you ,
Regards,
AB
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HPS power consumption

May 31, 2015, 11:04 am
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If I use only FPGA part of Cyclone V SE device, the HPS is in reset state with CPU0 and CPU1 or I should load code to sleep CPU1?
And if HPS is not used the default frequency is 800 MHz? Should I load code to slow down CPU to save energy?

Thanks
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Undefined output

May 31, 2015, 11:55 pm
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Hi
I have asked to write compare machine which compare 2 numbers with 4 bits.
I made it by ussing XOR.
My outputs dont react to the change in the inputs, they undefined.
The inputs works well with my test bench.
You can see my code at attached files.
Attached Images
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Altera USB Blaster JTAG problem: Suddenly unable to connect to FPGA

June 1, 2015, 1:03 am
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Hi

I'm using a custom Cyclone V board which I've been using for several days through the Altera USB Blaster with no problems. Suddenly, the Blaster is unable to connect to the board. The blaster is OK because is properly working with other boards, but it fails with the first one. FPGA looks is ok because during start-up, the loaded bitstream turns on and turns off several leds according to the expected behaviour. But USB Blaster still unable to connect.

Today, a second board has started to fail as the first one.

Whats going wrong? I've found several threads where people suggest to load 3.8V or 5V directly on the TDO pins for several seconds in order to blow up a protection. I've tried this with no success.

The jtagconfig -d output shows this message:

$ jtagconfig -d
1) USB-Blaster [USB-0]
Unable to read device chain - JTAG chain broken

Captured DR after reset = (02B050DD)
Captured IR after reset = ()
Captured Bypass after reset = (0)
Captured Bypass chain = ()


What could I do? Any suggestion?

Thanks in advance.

Regards,

Eduardo
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Problem usng UART with serial device

June 1, 2015, 1:22 am
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Hi,

I'm trying to get data from a GPS serial module link to the Soc fpga cycloneV dev Kit. But it doesn't work. I disabled the login prompt, configure the UART and use "cat /dev/ttyS0" but nothing happens. I use the Linux GSRD from rocketboard but it don't seem to included the cp210x driver for USB/uart device.
It works when I send data from a PC.

Anyone have solution ?

Thanks.
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altera cyclone V banks

June 1, 2015, 1:46 am
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hi

im new in the FGPAs world looking a useful source to learn all the banks subject on cyclone V.(how its work..considerations..etc.)

can someone help me with this?


thanks
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Cyclone IV: What is Internal Oscillator IP in Quartus 15?

June 1, 2015, 4:59 am
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Cyclone IV has a hidden internal oscillator that now is useable?
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max10 on chip flash read/write in nios

June 1, 2015, 5:37 am
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hi everone, for two weeks i stuck in the max10 on chip flash read/write in nios.
in my project, it has a nios system and the clk frequency is 100mHz.
i want to use the internal configuration mode of max10(single compressed image with memory initialization), as well as read/write the chip flash UFM in nios.
i can read the UFM, but i can not write to it.
the following is my code, i run it in debug mode


flash_status_reg1=IORD_32DIRECT(ONCHIP_FLASH_0_CSR _BASE,0x0); // read the flash_status_reg, the result is 0xfffffc04,
flash_control_reg1=IORD_32DIRECT(ONCHIP_FLASH_0_CS R_BASE,0x4); // read the flash_control_reg, the result is 0x3fffffff,


flash_data_reg1=IORD_32DIRECT(ONCHIP_FLASH_0_DATA_ BASE,0x0); // read the first 32 bit of UFM1,the result is 0x0,
while(1)
{
flash_status_reg1=IORD_32DIRECT(ONCHIP_FLASH_0_CSR _BASE,0x0);//read the flash_status_reg, the result is 0xfffffc04, it means read success
flash_status_reg1=flash_status_reg1&0x4;


if (flash_status_reg1== 0x4) break; // write success
}




// write to UFM1
IOWR_32DIRECT(ONCHIP_FLASH_0_CSR_BASE,0x4,0xff7fff ff);// disable the write protection of UFM1
flash_control_reg1=IORD_32DIRECT(ONCHIP_FLASH_0_CS R_BASE,0x4);// read the flash_control_reg, the result is 0x3f7fffff,
IOWR_32DIRECT(ONCHIP_FLASH_0_DATA_BASE,0x0,0x12345 678);// write to the first 32 bit of UFM1, then the debug stuck in here



can someone gives me some help?
i have found the reference desin for how to use the UFM　in quartus without nios;
i also have found the reference desin for how to use the onchip internal configuration mode of max10 in nios system;
but i have not found a reference desin use nios, and the UFM

thanks!
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LCD over Ethernet

June 1, 2015, 11:14 am
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Hi,

I'm using the simple socket example on the DE2-115 board. It seems to work well. The program is written to take commands to turn on/off the leds and to display on the seven segment display. My final goal is to send data to the SDRAM of the DE2-115 board over ethernet from the PC. Next, I would like to modify the files to be able to send some data to the LCD (this way I can easily know if I have managed to send data or not). For this I created a new task to display on the LCD screen. And I gave it a low priority (means a higher number). I basically created functions and tasks just like the ones for LEDs. When I run the project as NIOS hardware, it compiles and loads onto the board but goes into a loop when the link has to be established. This is what it looks like:

InterNiche Portable TCP/IP, v3.1


Copyright 1996-2008 by InterNiche Technologies. All rights reserved.
prep_tse_mac 0
Calling DE2-115 Mac Address Finder
Your DE2-115 Ethernet MAC address is 00:07:ed:ff:6b:c7
Your Ethernet MAC address is 00:07:ed:ff:6b:c7
prepped 1 interface, initializing...
[tse_mac_init]
INFO : TSE MAC 0 found at address 0x08222000
INFO : PHY Marvell 88E1111 found at PHY address 0x10 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link not yet established, restart auto-negotiation...
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
INFO : PHY[0.0] - Link established
INFO : PHY[0.0] - Speed = 100, Duplex = Full
OK, x=1, CMD_CONFIG=0x00000000


MAC post-initialization: CMD_CONFIG=0x04000203
[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created
mctest init called
IP address of et1 : 0.0.0.0
Created "Inet main" task (Prio: 2)
Created "clock tick" task (Prio: 3)
Acquired IP address via DHCP client for interface: et1
InterNiche Portable TCP/IP, v3.1


Copyright 1996-2008 by InterNiche Technologies. All rights reserved.
prep_tse_mac 0
Calling DE2-115 Mac Address Finder
Your DE2-115 Ethernet MAC address is 00:07:ed:ff:6b:c7
Your Ethernet MAC address is 00:07:ed:ff:6b:c7
prepped 1 interface, initializing...
[tse_mac_init]
INFO : TSE MAC 0 found at address 0x08222000
INFO : PHY Marvell 88E1111 found at PHY address 0x10 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link not yet established, restart auto-negotiation...
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
InterNiche Portable TCP/IP, v3.1


Copyright 1996-2008 by InterNiche Technologies. All rights reserved.
prep_tse_mac 0
Calling DE2-115 Mac Address Finder
Your DE2-115 Ethernet MAC address is 00:07:ed:ff:6b:c7
Your Ethernet MAC address is 00:07:ed:ff:6b:c7
prepped 1 interface, initializing...
[tse_mac_init]
INFO : TSE MAC 0 found at address 0x08222000
INFO : PHY Marvell 88E1111 found at PHY address 0x10 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link not yet established, restart auto-negotiation...
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
InterNiche Portable TCP/IP, v3.1


Copyright 1996-2008 by InterNiche Technologies. All rights reserved.
prep_tse_mac 0
Calling DE2-115 Mac Address Finder
Your DE2-115 Ethernet MAC address is 00:07:ed:ff:6b:c7
Your Ethernet MAC address is 00:07:ed:ff:6b:c7
prepped 1 interface, initializing...
[tse_mac_init]
INFO : TSE MAC 0 found at address 0x08222000
INFO : PHY Marvell 88E1111 found at PHY address 0x10 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link not yet established, restart auto-negotiation...
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
InterNiche Portable TCP/IP, v3.1


Copyright 1996-2008 by InterNiche Technologies. All rights reserved.
prep_tse_mac 0
Calling DE2-115 Mac Address Finder
Your DE2-115 Ethernet MAC address is 00:07:ed:ff:6b:c7
Your Ethernet MAC address is 00:07:ed:ff:6b:c7
prepped 1 interface, initializing...
[tse_mac_init]
INFO : TSE MAC 0 found at address 0x08222000
INFO : PHY Marvell 88E1111 found at PHY address 0x10 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link not yet established, restart auto-negotiation...
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
InterNiche Portable TCP/IP, v3.1

And this keeps going on. I know my question is a little vague since I haven"t posted what code I changed but would anyone know what could possibly be wrong by looking at the NIOS II console output above. Thanks!
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Nios II megafunction IP on QSYS

June 1, 2015, 11:50 am
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Hello,

I've successfully implemented my first Nios II program both synthesis and code simulation through Modelsim. The design was quite simple and the procedure straightforward. The testbench was automatically generated by QSYS and I was able to perform the simulation in eclipse with modelsim (no board available at the moment). Now I wanted to insert one of Altera's megafunction IP blocks like LPM _ADDER to QSYS and let the QSYS generate the testbench for Modelsim as before. I tried to join the two blocks (Nios and LPM_ADDER) for example in schematic editor, the design was synthesized successfully but I was unable to perform simulation cause my simulation model consisted only with the Nios model and not LPM_ADDER as I was expected. I know that there is a possibility to create a new component in QSYS by inserting HDL code and then connect this component through PIO in Nios II, but is there another way to do that and what happens when you want to insert the existing IP blocks in Quartus? My main concern as I said is the final simulation in Modelsim through Eclipse.
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Executing multiple host program at the same time

June 1, 2015, 12:49 pm
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Hi everyone,

I am just wondering if the Altera OpenCL driver is able to handle multiple host programs running at the same time? Is this feature vendor specific? I am using AOCL 14.1.1 and DE5-net from Terasic.
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FPGA to HPS interrupts

June 1, 2015, 1:23 pm
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Hi,


I'm trying to interrupt HPS from FPGA. I'm generating interrupts from the slave on the FPGA which I can see it on the signal tap. I'm checking for interrupts in Linux using 'cat /proc/interrupts', I see that my interrupts are registered but I don't get any interrupts.


In the RTL viewer (shown in fig 1; HPS.jpg), I see that the interrupt bus (f2h_irq_p0[31:0] & f2h_irq_p1[31:0]) are not connected to anything in the 'fpga to hps interfaces'( this is the block where it shows connections of all the bridges between HPS and FPGA). Is it just not illustrated in the RTL viewer or is not connected.

I don't know what I'm doing wrong or if I'm missing something. Do I have to make any changes to the device tree? Or should I enable something like I enable the bridges?


Thanks,
Karthik
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How to simulate the FPGA neural network in Altera

June 1, 2015, 4:16 pm
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I want to simulate the some kind of schematics that work by principle of neural networks. I have Altera Quadrus 11. But when trying create some verilog or vhdl code I see that compilation and simulation items of menu is disabled. Should it due to absence of installed device --such warning is appered when creating the project or I do not entered the license properly. If the issue is in not installed device, which one can I use for my student work, how much space it could take. Can I use the web-edition for this purposes, with or without device?
And the next set of questions relates to the ocding of logical circuit in Altera or Modelsim (which one could I use-- now I have just Model-Sim free edition). The logic circuit should sort analog signals. The other components of circuits is adders with 2 addings and one substraction, and one with adding of all N signals (or non-binary numbers) the N+2 step functions (comparators of amplitude of signals with some x), and one multiplicator and one integrator. So definitive question is the concept and specific of neural networs with back-propagation method in HDL, and other ones is concerning the converting decimal numbers to binary ones (or it could be allowed to be binary from the start), how implement of multiplication for the big coeficent, how the comparator works in Verilog/VHDL, and the most unsure --about integrating the function. I do not exactly even know what is the role of integrator in logic circle (in this case it is connected with the multiplicator and authors even jjust whol ethe whole structure --inverting integrator --*(-Alpha)). Where I could find such examples in VHDL, but it would be better in Verilog, that I studied something. What structure and size of teh whole programming module should be if N (number of sorted items) is 5-6...
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