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Device problem(EP4CGX150DF27I7)

June 1, 2015, 8:26 pm
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hi:
I have buy some fpga devices , EP4CGX150DF27I7,the silkscreen of device surface as the following imae. I can`t understand the silkcreen represent what mean? or the devices are bad?
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Flash issues

June 2, 2015, 12:56 am
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Hi.

Is there a proper guide that explains how to flash the configuration memory with both hardware and software?

Nios II Flash Programmer User Guide 2.2 seems to be outdated.

I hope someone here has the knowledge to help me.

(I'm using Quartus 14.0 and a DE0-NANO board.)

It is not easy to find any answer on this forum. All I see is others having trouble and no clear solutions :(
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ADC in FPGA verilog HDL

June 2, 2015, 4:06 am
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I want to know the read the digital (1 or 0) from the 2.5-3.5v in veriloge HDL in quarturs II software by 1 pin.
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USB 3300 PHY not showing up on DE1-SoC board.

June 2, 2015, 5:40 am
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Hello All,

I was trying to get some data to pop up over the 3300 USB phy.
And was finding the .QSF file was incomplete, so I assigned the pins at 3.3v LVTTL.

and used..
Code:

module Phytherface (
input clock,
input direction,
input [7:0] readline,
inout [7:0] uart,
output[7:0] writeline
);

reg [7:0] a;
reg [7:0] b;

assign uart = direction ? a : 8'bz;
assign writeline = b;

always @ (posedge clock)

begin
b <= uart;
a <= readline;

end
in conjunction with.
Code:
Phytherface AK01 (.direction(HPS_USB_DIR),.clock(HPS_USB_CLKOUT),.uart(HPS_USB_DATA),.writeline(take));
wire [7:0]take;
takeone TK01 (.in(take),.out (HEX5)); /*<-- posedge sample&hold*/
endmodule
But no go,
Did I do something obviously wrong (with the tristate?)?
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Alteraforum is crazy?

June 2, 2015, 8:45 am
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This website today send me email with updates ("Reply to thread") of a month ago...
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QSYS 15.0 hanging (hung, wedged, locked-up etc) when loading my design

June 2, 2015, 9:26 am
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Hi,

I am experiencing some troubles with 15.0 qsys-edit becoming wedged when loading my 13.1 design. The qsys editor GUI becomes completely comatose with the "open system" dialog box visible. I eventually conclude that there are no options remaining other than to fall back to kill from the linux command line in order to stop the zombie qsys-edit. I am running ACDS 15.0 on Ubuntu 14.04 LTS. I skipped 14.1 because I heard there were crashes on Ubuntu. The following are the last gasp messages I can see in the pop-up window before the GUI locks up. I don’t observe that CPU is being consumed by java when this lock-up occurs, so the issue maybe isnt caused by an infinite loop in the qsys software. The hang appears to occur during the "validating" phase.

Warning: periph_clk: Used clock_source 15.0 (instead of 13.1)
Warning: irq_bridge_0: Used altera_irq_bridge 15.0 (instead of 13.1)
Warning: ext_memory: Used altera_mem_if_ddr3_emif 15.0 (instead of 13.1)
Warning: isolation_im: Used altera_avalon_mm_bridge 15.0 (instead of 13.1)
Warning: tight_coupled_ram: Used altera_avalon_onchip_memory2 15.0 (instead of 13.1)

Has anyone experienced this problem that could suggest a workaround.

I did try increasing the JVM heap size with a command line similar to this, but this didn’t change the outcome.

"qsys-edit --jvm-max-heap-size=2048m".

I could submit a service request, but no doubt they will not know how to proceed unless I could send a complete copy of my design, but unfortunately I cant do that, and I suspect also their response will be that Ubuntu/Debian are not supported Linux versions at Altera.

Jeff
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Transceiver Toolkit (TTK) Example Designs Review (using Quartus II v15.0)

June 2, 2015, 10:37 am
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Hi all,

While working on an Arria V GZ transceiver design I found I was getting timing errors in a design compiled under version 15.0 that compiled fine under 14.x. I've filed a Service Request, but haven't heard back yet. I figured that other transceiver users might benefit from my review of the Altera and AlteraWiki example designs.

https://www.ovro.caltech.edu/~dwh/co...k_examples.pdf

I'm working on another document with more detailed examples for the Arria V GZ (which uses the same PHY as the Stratix V devices). I'll post that when I get it completed.

IMPORTANT NOTE: The document also shows how to enable Hidden Qsys Components ... a trick I picked up from an Altera video (see the doc for a reference to the video).

Cheers,
Dave
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OpenCL ICD Linux Problem

June 2, 2015, 1:48 pm
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I am having trouble getting the ICD to function properly for loading the Altera OpenCL library (.so). When running simple OpenCL host code on a CentOS 2.6 environment, I get a message similar to the following:

Code:
./print-devices: /opt/altera/15.0/hld/linux64/lib/libOpenCL.so.1: no version information available (required by ./print-devices)
./print-devices: symbol lookup error: /opt/altera/15.0/hld/linux64/lib/libOpenCL.so.1: undefined symbol: dlopen
I have tried modifying the Altera.icd to have both the library name (libalteracl.so) and absolute path. In regards to libOpenCL.so.1, which is what the error message above is complaining about, here is the output of ldd:

Code:
linux-vdso.so.1 =>  (0x00007fffe868a000)
libc.so.6 => /lib64/libc.so.6 (0x00007f282a60d000)
/lib64/ld-linux-x86-64.so.2 (0x0000003845a00000)
In my current setup, I can use the Intel ICD and NVIDIA ICD successfully. I can compile and link to the Altera library manually, but would like to utilize the ICD in the same way as Intel and NVIDIA. Has anyone run into similar issues? Has anyone had success using the ICD?
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How to configure MSI interrupt

June 2, 2015, 2:07 pm
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Hi,

For PCIe Hard IP, how to setup/configure MSI interrupts?
For example, I have DMA read and DMA write transactions, setting up through descriptors. At the last PTR, it sends MSI interrupts. How to configure the MSI so that the DMA read and write receive different message IDs or call different ISRs ?

Thanks,

Tiger
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LVDS power requirement

June 2, 2015, 9:50 pm
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graphic processing unit support

June 2, 2015, 10:10 pm
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Hi,

Is any one can confirm whether the Stratix 10 supported hardened GPU?
Thank you
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Quartus II v15 (small) bug?

June 3, 2015, 1:32 am
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After installing new Quartus II v 15 I came up with following problem:
- normally, when I try to open a project file (let's call it test1.v) which is already open in Quartus window, it won't open but will get focus,
- let's now assume that I close a Quartus with this file open. When I reopen Quartus and project and than try to open test1.v file, it won't get focus, but will be opened again (as a second file).

It's not very intuitive and was changed (why?) comparing to older Quartus versions. Is there something that can be done with it?
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epcs does not configure cyclone V

June 3, 2015, 1:46 am
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Hello,
my ecps on my board does not configure my fpga. I create a jic file and programm the epcs.This works ok.
But my programm does not boot.
With the nios2flash programmer i can convert sof2flash and elf2flash and programm the epcs,but it still not configure my fpga.

On my design board i have the vccbat at 1.8V? Is that the problem?
I've seen in reference design that this Voltage is set to 2.5V.

Has someone the same problem and can help?

Thanks.
Sacko
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altera_avalon_tse.h and _TIMEOUT_THRESHOLD #defines

June 3, 2015, 5:41 am
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Hello,

We are using NIOS2 with uCOS2 and the NicheStack and need to be able to
run our embedded app even if we don't have a network connection.
We noticed with the below default altera_avalon_tse.h settings,
the processor hangs up and seems to hold interrupts causing the app
to have issues loading.

#define ALTERA_AUTONEG_TIMEOUT_THRESHOLD 250000
#define ALTERA_CHECKLINK_TIMEOUT_THRESHOLD 1000000
#define ALTERA_NOMDIO_TIMEOUT_THRESHOLD 1000000
#define ALTERA_DISGIGA_TIMEOUT_THRESHOLD 5000000

I tried these settings and it allowed to progress without a network connection fine,
but this seems like overkill.

Is there another Altera #define or code block that would allow obtaining the IP in
a lower priority task/thread ?


#define ALTERA_AUTONEG_TIMEOUT_THRESHOLD 2500
#define ALTERA_CHECKLINK_TIMEOUT_THRESHOLD 1000
#define ALTERA_NOMDIO_TIMEOUT_THRESHOLD 10000
#define ALTERA_DISGIGA_TIMEOUT_THRESHOLD 50000
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nios-ii-on-die-temperature-sensor example

June 3, 2015, 5:29 am
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Hi

im totally new to FPGA's...Im trying to run the following example.

http://www.alteraforum.com/forum/sho...sensor+example

if i load the .pof file supplied all is good :-)...

I would like to build&modify the c-code for the project as described in http://www.alterawiki.com/uploads/e/...sor_design.pdf
but i cant locate the nios_setup.sopcinfo file. I tried with eth_std_main_system.sopcinfo found at https://cloud.altera.com but then i get this error

fatal error: altera_modular_adc_sequencer_regs.h: No such file or directory

i cant find this .h file.

thanks in advance
/Stefan
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Dynamic io delay

June 3, 2015, 6:34 am
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Hello, i'confusing about the dynamic io delay chain? Is there any relationship between the dynamic io delay with the d1,d3 setting? Can I get dynamic io delay value from the resource property editor? Thank you
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DeviceIOControl - DMA - Interrupt issues

June 3, 2015, 8:49 am
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Hi,

Here is the logic flow:

1. GUI program sends DeviceIoControl command setup to driver:
setup DMA descriptors
2. GUI program sends DeviceIoControl command Start to driver:
call the routine of start DMA Read and write (with parameter of # of loops)
3. ISR routine receives interrupts
Checks # of loops, if not, zero, call the same of above routine to restart DMA R/W.

It works only if put a debug line before start DMA:
KdPrintf("."); //if this line is commented, no interrupts will be received.
StartDMA();

Anyone has any suggestions what is wrong?
Thanks,

Tiger
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MAX10 can't accept 125 MHz clock without timing violations

June 3, 2015, 8:58 am
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Hi.
I'm using quartus 15.0.0 64-bit on Windows 7 pro.
I'm working on a design that uses an MAX10 (10M08SAU169C8). The design calls for two clock domains.
The first is 50 MHz and the second is 125 MHz.
The 50 MHz clock domain is used for the majority of the design (well less than 50% utilization in all categories).
The 125 MHz clock feeds an instantiated PLL which is to provide a 10 MHz output on C0.
The 10 MHz output from the PLL clocks the ADC block for the temperature sense function.
When I compile the design I get timing errors in all three temperature/speed models suggesting that the restricted fmax is below 100 MHz due to a low minimum pulse width violation.
I do understand that the tool is saying I can't run over 98.something MHz.
I don't know what a low minimum pulse width violation is or what exactly the restricted FMAX means.

I thought that perhaps my other logic was the problem so I created a test design that includes only the PLL, the ADC, and a single registered output bit from the ADC.
Again, the 125 MHz goes only to the PLL which provides an 10 MHz output for the rest of the design.
When I compile the new project with or without the proper pin assignments (for my board) I still get restricted fmax low minimum pulse timing errors and a restricted fmax under 100 MHz.

I've been poking around the datasheet and can't find anything to suggest that this device can't utilize an 125 MHz clock.
I'm sure I'm doing something wrong as I'm clearly no timing expert.

Any suggestions on how to appease the timing tools?
I've attached an archive of my test project for reference.

Thanks in advance.
Attached Files
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missing socal folder

June 3, 2015, 9:16 am
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Hi!

I will be using DE1-SOC board for my bachelor's degree and Im learning on how to use it. I noticed that user's manuals are for version 13 of Quartus and current version is version 15. I have already encountered some differences that puzzled me but I managed to solve them with a bit of googling. Now Im at FPGA-HPS project and I get an error from command shell:

Code:
$ makearm-linux-gnueabihf-gcc -static -g -Wall  -IE:/Programs/altera/15.0/embedded/ip/
altera/hps/altera_hps/hwlib/include -c main.c -o main.o
main.c:6:25: fatal error: socal/socal.h: No such file or directory
 #include "socal/socal.h"
                        ^
compilation terminated.
make: *** [main.o] Error 1
I noticed that there are now two folders there: soc_a10 and soc_cv_av, which both include the missing files. What do these two folders mean? Which one should I use? Do I fix the header to match the new folder configuration?

Thank you for help!
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Where is my IP Megastore/Base Suite itens?

June 3, 2015, 10:02 am
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Hello guys, I'm new with Altera so I'll be really happy if you help me.

I'm following an Altera tutorial and it teach to add a PLL Megafunction/Base Suite as follows:

- Right click > Edit > Insert Symbol;
- Click Megawizard Plug-in Manager;
- Click Next;

And on the left shoul appear a list on the field Select a Megafunction from the list below; but I see nothing, only a empty IP MegaStore/Base Suite icon on the tree.

I'm using the Quartus-II WEB 11 SP1 once my dev board do not accept newer releases... I'm using the EP1C3T144C8.

Please Help me to populate the IP list :)
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