Asserting DEV_CLRn during configuration

June 3, 2015, 8:01 pm

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Hi,

I would like to know if on Cyclone IV devices DEV_CLRn is held asserted during configuration and beyond the initialization phase if that will cause the registers to remain reset right out of configuration. I want to do this so some pins are tri-stated initially until DEV_CLRn is released to avoid bus contention. I can't use DEV_OE because it tri-states all pins and I don't want that. Thanks.

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Simulation Tools

June 4, 2015, 12:06 am

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Any other simulation tools which is easy to use and can get the user manual/other document related to the tools easily? Thanks. :oops:

FPGA is not responding to code

June 4, 2015, 3:46 am

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Hello,

I have downloaded vhdl code in cyclone III fpga. But fpga is not responding after downloading. I have two vhdl codes. When I download first vhdl code, fpga works fine. But when I download second code (first code with some modification), fpga doesn't respond. Can any one tell me what can be the possible root cause of this?

the total resources that second code is utilizing are less than first one...

Cyclone V E A7 into A2 migration

June 4, 2015, 4:12 am

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Hi


I would like to make a new design with a Cyclone V E. I could calculate that a A2 or A4 would be enough for this application.
But for engineering I would like to use a A7 to have more memory etc... What would be the best way to start with my pcb design?
I was thinking to take the schematic from the cyclone V e A2 and just place a A7 onto my first boards. Do you see there any problem?
The A7 should be more powerful and has more IOs as the A2. Is there mayba a good way to check if really every pin function from the
A2 is supported in the A7?


As peripherie I will use a LPDDR2 SDRAM, a SDRAM, a ethernet phy, a flash and some user IOs


Thanks a lot!

"Cant place node -- illegal location assignment INCONSISTENCY"

June 4, 2015, 6:20 am

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The fitter produces the error below, which I have no clue how to analyze.

Code:

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Error (171016): Can't place node "pio2:u0|pio2_hps_0:hps_0|pio2_hps_0_hps_io:hps_io|pio2_hps_0_hps_io_border:border|emac1_inst" -- illegal location assignment INCONSISTENCY File: .../synthesis/submodules/pio2_hps_0_hps_io_border.sv Line: 123
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:00
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Error (11802): Can't fit design in device

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I've created a simple 2 GPIO Qsys design reading switches and driving leds on a DE1-SoC board, using a .qsf generated with DE1-SoC System builder.
The error also appears when switching devices, i.e. with ALL location assignments removed.
Also I tried DE1-SOC.qsf downloaded from the TerASIC website.

Actually, I managed to generate a bitfile once, and now the flow is broken again.

Any suggestions? BTW I'm using Quartus 15.0

Any similar Kit to DE1-SoC that can scale to 4.5 million logic units and run 100 MHz?

June 4, 2015, 9:58 am

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I wanted to use DE1-SoC to iron out the learning curve.
Then when ready for the a bigger design, buy a high
density version without much change to my SW setup.

Please advice

Fing.

Error booting linux on Nios II on Stratix V

June 4, 2015, 12:34 pm

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I made the necessary kernel images (as per instructions on : http://www.rocketboards.org/foswiki/...lding_U_45Boot)
Now, when I try to nios2-download -g ~/linux-socfpga/vmlinux && nios2-terminal
I get the following error :

Using cable "DE5 Standard [2-1.7]", device 1, instance 0x00
Pausing target processor: OK
Initializing CPU cache (if present)
OK
Downloaded 3523KB in 5.1s (690.7KB/s)
Verifying C0000000 ( 0%)
Verify failed between address 0xC0000000 and 0xC000FFFF
Leaving target processor paused

Is this because my memory is incorrectly configured?

Also,

1. On the page http://www.rocketboards.org/foswiki/...alForStratixIV
Under the section To boot Nios II linux from CFI flash, we make a proper address mapping, programming the u-boot image first (at the CPU base address), then the DTB and then the Linux kernel with built in rootfs.

In the method (To boot Nios II linux from RAM), we do no such thing, neither do we program u-boot nor anything related to rootfs. All it says is that we compile the .dts file into the kernel (in make menuconfig). Is this *all* that is required ?

2. My error says conflict between 0xC0000000 and 0xC000FFFF ; why and how does it reach to 0xC ?

I'd greatly appreciate any help on this.

Error booting linux on Nios II on Stratix V

June 4, 2015, 12:49 pm

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I made the necessary kernel images (as per instructions on :http://www.rocketboards.org/foswiki/...lding_U_45Boot )
Now, when I try to nios2-download -g ~/linux-socfpga/vmlinux && nios2-terminal
I get the following error :

Using cable "DE5 Standard [2-1.7]", device 1, instance 0x00
Pausing target processor: OK
Initializing CPU cache (if present)
OK
Downloaded 3523KB in 5.1s (690.7KB/s)
Verifying C0000000 ( 0%)
Verify failed between address 0xC0000000 and 0xC000FFFF
Leaving target processor paused

Is this because my memory is incorrectly configured?
Also,

1. On the page (http://www.rocketboards.org/foswiki/...alForStratixIV)
Under To boot Nios II linux from CFI flash, we make a proper address mapping, programming the u-boot image first (at the CPU base address), then the DTB and then the Linux kernel with built in rootfs.

In the method (To boot Nios II linux from RAM), we do no such thing, neither do we program u-boot nor anything related to rootfs. All it says is that we compile the .dts file into the kernel (in make menuconfig). Is this *all* that is required ?

2. My error says conflict between 0xC0000000 and 0xC000FFFF ; why and how does it reach to 0xC ?

I'd greatly appreciate any help on this.

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PCIe MSI interrupt sharing problem

June 4, 2015, 1:40 pm

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Hi,

MSI shared for DMA Read and Write. In ISR() routine, checks status to determine read or write completion. Either there is missing MSI or Read completion MSI can be mistaking as Write completion, and vice versa.

If the same routine, runs ok for read only dma (loop 10000 times) and for write only Dma(10000 times). But sometimes it fails to do simultaneously R/W.

How to resolve this issue?

Thanks,

Tiger

Can I start Modelsim/Questa GUI when I am using command line mode?

June 4, 2015, 1:42 pm

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When I do simulation, ususally I will start with command line mode, to save some resource (I also hear it may accelerate the simulation). But after simulation done, sometimes I want to open the GUI to have a look, to check such as whether the simulation duration is enough. So I wonder whether I can open GUI when I am using command line mode? If I can, how?

Thank you in advance.

NIOS is constantly reading from instruction memory and reading/writing to data memory

June 4, 2015, 2:35 pm

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Hello all,

I am still working on my first NIOS design and am having troubles with the instruction/data memory access. Below is a schematic of the NIOS and its peripherals. The NIOS is connected to a ROM for instruction memory, and a RAM for data memory. The data memory is also connected to an Avalon bridge in order to communicate with an external RTL component.



When I do an RTL simulation of this design, I see very random reads and writes to data memory and continuous reads from the instruction memory. Regardless of what is included in my .s source file, I see this behavior. Can anyone explain to me why I am seeing this? Shouldn't I be expecting instructions reads based off the instructions in my assembly file?

Attached Images

• Capture.jpg (21.4 KB)
• Capture1.jpg (21.7 KB)

Flash Programmer, EPCS Reserved Fields are non-zero

June 4, 2015, 2:46 pm

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Greetings -

While trying to program a Spansion S25FL032P Flash device on my EP4CE10E22 Cyclone-IV board with the Nios II Flash Programmer, I get the following error messages:

"Looking for EPCS registers at address 0x00011100
Initial values: 9300023.................
Not here: reserved fields are non-zero
No EPCS registers found: tried looking at addresses ..............
Error Code: 8"

Do I need an override file and what should go in it? Any help would be greatly appreciated.

Thank you very much,
Falcon234

Looking for FPGA that can have FF and shift register that can clock at 1GHz

June 4, 2015, 4:10 pm

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Hi
I designed with Apex 10 years ago. I am designing circuit that use FF, latches, 14 bit adders, and some simple combination logic that can run on a synchronous 1GHz clock. I don't need any fancy processor, DSP etc, just simple circuit even the old MAX Plus can do, but just need to run at 1GHz clocking.

Can you suggest the fastest and latest family FPGA I can look into?

I programmed with the Quartus 10 years ago, what is the latest version for programming? Is it similar with the original Quartus I learned before?
Is there any free simulation program?

Thanks

Alan

FPGA Area Optimization

June 4, 2015, 11:26 pm

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I have a code for in Altera project (Sensorless control algortihm) with resource utilization aroung 66000 gates. My supervisor wants me to do area optimization to reduce the gates. Can, any guide my how to do this.

FPGA to HPS simple communication

June 5, 2015, 4:40 am

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Hello,

In advance, sorry for my english (it's not my mother tongue).

I'm a beginner into qsys and linux (1 month). I have experience on microcontrollers without OS.
I work on a DE1-Soc board (and also a SocKit). The OS used is the linux provided by terasic on their website.

I am trying to make the HPS react to a communication initiated by the FPGA. The piece of information to send from the FPGA to the HPS should be around 200 bits ?

I thougth about two ways to resolve this problem.
1. Use one of the two IRQ in the HPS IP. When arrived in the interrupt routine, read a reserved part of the FPGA sdram through the h2f_axi bridge (the FPGA put there the right data before sending the interrupt signal).

2. Use the f2h_axi bus to directly transfert the data.


I began the first solution.
I succeed in the h2_f_axi reading but I have big difficulties to understand how the interrupt works. I read a lot on this forum and on rocketboards.org but I think that I miss serious basis in embedded linux development.

I saw that I have to modify the device tree file. I ran sopc2dts.exe (gui mode) on mysystem.sopcinfo. I understood that this device tree makes the correspondence between the hard and the soft. But I couldn't find any trace of "IRQ" or "interrupts = <0 40 1>;" in the dts generated file.

There is my Qsys design in the attached file. (It's a test design, the components I developed have very simple behaviour)
My interrupt sender simply makes the link between a Key of the board and the interrupt signal. But in the end it will be triggered from a finite state machine.

Is there a tutorial with all the steps requiered to implement interrupt (from Qsys to C program) ?
Is the interrupt way the simpliest way to achieve my goals (just having a FPGA to HPS communication that trigger a routine) ?


I work on a Windows7 computer. As shown in the terasic tutorials, for the moment, I write my C programs in a text editor and compile with a makefile thanks to the "Embedded_command_shell" provided. (Is that a good way ? I saw a lot of people working on DS5)


Can someone help me ?
Thanks

Attached Images

• 20150603_qsys.jpg (229.5 KB)

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Error While generating HDL code using Standard and Advanced Blockset

June 5, 2015, 5:26 am

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I have tried using Standard Blockset with Advanced Blockset COmbined.
First Question is
1) Whether I need to have HDL Coder for this ?

I am referring to 3-4 section in this document https://www.altera.com.cn/content/da...esign_flow.pdf
I just attached the Basic Design of what I am trying.
I just gave Input and Output connected. I used Standard and Advanced Blockset, the Simulation is running and I am getting expected Output (3.5 here).
But When I am trying to generate HDL code using this Signal Compiler, I am having below trouble.

Matlab Error :
Error using alt_dspbuilder_mdl2xml (line 63)
Java exception occurred:
com.altera.dspbuilder.common.DSPBuilderException: java.io.FileNotFoundException: D:\rtl\NewModel\NewModel_Adv_Blk___entity.xml (The system cannot find the file specified)
at com.altera.dspbuilder.simulation.templates.XMLPars er.loadDocument(Unknown Source)


The error I am getting is NewModel_Adv_Blk___entity.xml file is not specified, but NewModel_Adv_Blk_entity.xml is generated.
I am not understanding why there are three underscores (___) in before entity.
Can you please help me this. Am I doing anything wrong in Procedure.

Attached Files

• NewModel.mdl (41.0 KB)

How to fix LUT inputs?

June 5, 2015, 6:18 am

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I implemented ring oscillators on an Altera Cyclone IV with Quartus II.

The compilation choses arbitrarily which inputs of the LUTs are used.
I could edit each LUT seperatly but this is very time-consuming.

Is there a way to determine which LUT inputs are used without changing each one severally?

Attached Images

• LE LUT.jpg (28.7 KB)

Altera Monitor Program JTAG issues

June 5, 2015, 6:18 am

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Hi,

I've been learning how to use the Monitor program in conjunction with the DE2-115 board for about a week now, and every time I try to load my program to the board, I get an error message saying that the JTAG instance ID isn't correct, and that I need to make sure the .sof and .sopcinfo files are from the same project.

Any ideas as to what might cause this problem, and how to solve it?

I'm currently working on Windows 7 (64bit), with Quartus II 15.0. I've been following the tutorials provided with the DE2-115 development board.

-N

nios cpu control the ram on chip

June 5, 2015, 6:40 am

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hi!
as I know ,there are two ways for nios cpu to control the ram on chip .one way is to write the data and address to the ram by PIO ,the other way is to make myself componet to control the ram .however, I'm not sure is that, how should I driver the input clock of the ram.can I make the nios cpu clock as the ram clock?

Cyclone IV E Configugation pin MSEL3 issue

June 5, 2015, 8:11 am

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Hi, I need some help with Cyclone IV E configuration.

EP4CE22F17 does not have MSEL3 pin and handbook says:

Quote:

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Smaller Cyclone IV E devices or package options (E144 and F256 packages) do not
have the MSEL3 pin. The AS Fast POR configuration scheme at 3.0- or 2.5-V
configuration voltage standard and the AP configuration scheme are not supported in
Cyclone IV E devices without the MSEL3 pin. To configure these devices with other
supported configuration schemes, select MSEL2..0 pins according to the MSEL
settings in Table 8-5.

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https://www.altera.com/content/dam/a...cyiv-51008.pdf

Ok, that sounds good, but which MSEL3 pin value I must assume when looking in that table?
0, 1 or equal to some other MSEL pin?