Hello everyone,
I'm designing a board with a Cyclone V driving a DAC running at 420MS/s using a parallel DDR interface. To achieve this datarate (840Mb/s per stream), there is an ALTLVDS_TX component with a serialization factor of 4, so that I can work with SDR signals at 210MHz internally. Achieving timing closure is still annoying enough, but should be possible. When checking the TimeQuest output, I found some automatically generated constraints which I don't really understand. In the document UG-MF9504 (
https://www.altera.com/content/dam/a...altlvds.pdf#65), there is a timing diagram (fig. 15 on p. 65) showing the three clock signals driving the SERDES. My serialization factor is 4 and not 10, but the relationships are the same: c0 is running at 840MHz, c1 at 210MHz with (in my case) 45° advanced phase, 25% duty cycle and c2 is 210Mhz with 50% duty cycle. Now, as far as I can tell, c1 is the enable signal to latch the input data into the internal registers. This happens every four cycles of the fast clock c0, so in my opinion, the constraint should be something like
Code:
set_multicycle_path -setup -end 4 -to [get_pins { tx|ALTLVDS_TX_component|auto_generated|sd*|txin*}]
set_multicycle_path -hold -end 4 -to [get_pins { tx|ALTLVDS_TX_component|auto_generated|sd*|txin*}]
But when checking the automatically generated constraints, I see a 3 there. This is also visible in the timing diagram of TimeQuest, the data is required to be stable after 3 cycles of c0. Why is that? I couldn't achieve timing closure this way, so I've overridden the constraint and, well, it works. But this obviously doesn't mean that it is also actually correct.
The other strange thing with this serializer is that I have to invert the MSB (the first serial bit per word) of each stream. This is not a problem to do as soon as one knows it, but what is the reason for this behaviour? I also wasn't able to find any statement about that in the documentation at least, but maybe I've just overlooked it. Is this an anomaly of my design, or is this usual and designers are just expected to know it?
Thanks!
Best regards,
Philipp