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Carry chain on Cyclone V

January 18, 2016, 4:43 pm
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Hi,
I'm new and I have a problem with implementation carry chain in Cyclone V. I have to make a ring oscillator on this line and I have a problem with which component should I use ?
I think about component carry_sum or lpm_add_sub.
Also I have a problem with carry_sum. In quartus prime this buffers carry_sum are ignored and nothing. Do you have any suggestion ? :confused::confused:
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Reg: Max5 CPLD eval/demo kit for 5M160ZE64A5

January 18, 2016, 5:58 pm
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I have some questions regarding the Max5 CPLD 5M160 family and associated boards/kits.

I have looked online and I dont see CPLD kits with the 5M160ZE64A5 part (I can see 5M570, 5M1270 or 5M2210 CPLDs)

I wanted to know if -

1) Are there any evaluation kits/boards available specifically with the 5M160ZE64A5N so that I can evaluate this particular part and verify my design?

2) I understand Altera might not be making eval. boards for the 5M160 family. However can someone recommend any 3rd party board/kit which I can buy/use for evaluating the 5M160ZE64A5N part?

3) Is there any (unpopulated) socket board or break out board, on which I can simply mount the 5M160ZE64A5 chip (without the need for soldering etc.) so that I can simply bring up the CPLD and evaluate the functionality?

4) In order to load the CPLD, I understand I need the USB-blasterII kit (s/w and dongle). Can these be used in stand alone fashion?
Do I need some other associated hardware/peripheral/software in order to flash the CPLD?

Please let em know soon ...

Thanks and regards,
Z.
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JTAG Error

January 18, 2016, 8:39 pm
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Hi all,

Please can anyone help me with this error,,,,thanks in advance

Error: Can't configure device. Expected JTAG ID code 0x020B40DD for device 1, but found JTAG ID code 0x020B60DD.

my board is DE2-70 cyclone 2

i read all the previous posts about this error and nothing help... dose someone have another idea how can i pass this problem
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"cannot place 2 nodes into a single alm" error message while doing signalProbe

January 18, 2016, 10:15 pm
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Hi All,

I am getting this "cannot place 2 nodes into a single alm" error message while doing signalProbe. This issue comes to me suddenly, and I have always been able to do signalProbe without issues, using the same Quartus version and on this same project.

I have googled, and found a few related answers posted by Altera. Altera says that this is their tool bug, and will be fixed in future Quartus releases. They also suggests some workaround. I tried the workaround, but still cannot get rid of this issue.

https://www.altera.com/support/suppo...22013_171.html

Does anybody know other possible workarounds? Thanks.

My Quartus version is 13.1.0, Linux 64-bit version.
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Reg: Max5 CPLD 5M160ZE64 clk/gpio pins ...

January 18, 2016, 10:44 pm
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hi,

i had a question regarding the max5 5m160z cpld.

i need to provide 4 or 5 clocks into my design. the max5 cpld databook says there are only 4 dedicated global clk pins (which can also be used as general purpose IO).

since I need to give more clock inputs into my design compared to the no. of gclk pins available, i wanted to know if it's possible to use other general purpose IO pins to feed a clock into my design?

my design is low speed (about 40MHz). also, i did try to compile my design in QuartusII and assigned the clocks in my design to a general purpose IO (instead of dedicated clock pins) and the tool did not complain.

so i just wanted to know if this (feeding clock into cpld via GPIO) has been tried by someone on actual hardware and/of if there were any issues?

please let me know ...

thanks,
z.
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Timer Period not correctly

January 18, 2016, 10:44 pm
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Hi all,
my goal is to set a timer with a period time of 1ms and start it. After the time is elapsed it should rise an IRQ (once).
The timer itself with interrupt works, but the time is always about 6 to 8us. regardless what i write into the timer period registers?
I also tried to set 80'000 (80MHz clock) but nothing changed on the 6 to 8 us.

Qsys settings:
Period: 1us
size: 32bit
Hardware Options: Full featured

Here the code for the timer:

init:

Code:
alt_ic_isr_register(HIRES_TIMER_IRQ_INTERRUPT_CONTROLLER_ID, HIRES_TIMER_IRQ, hires_timer_ISR, NULL, NULL);
note: i made this according to the BSP generator for my niosII / uC-OSII project

IRQ:

Code:
void hires_timer_ISR() {
  IOWR_ALTERA_AVALON_PIO_DATA(DEBUG_BASE, 0);
  IOWR_ALTERA_AVALON_TIMER_CONTROL(HIRES_TIMER_BASE, 0x0000); // disable IRQ
}
start the timer:
Code:
// set debug io
        IOWR_ALTERA_AVALON_PIO_DATA(DEBUG_BASE, 1);
        // set period
        IOWR_ALTERA_AVALON_TIMER_PERIODL(HIRES_TIMER_BASE, 0x03E8);
        IOWR_ALTERA_AVALON_TIMER_PERIODH(HIRES_TIMER_BASE, 0x0000);
        // Start timer, single, with IRQ
        IOWR_ALTERA_AVALON_TIMER_CONTROL(HIRES_TIMER_BASE, 0x0005);
Thanks in advice, Thomas
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Forum Signatures

January 19, 2016, 4:56 am
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Hi, according to the forum rules, discrete signatures are allowed:

Quote:
Do not spam the site with advertisements. You will be banned for such activity. If you have an Altera related product or service you provide, send in a Marketplace entry form. You can also use custom signatures to link to your website service. Of course, you must have a post that is of use to forum to use your signature. This is a passive way of letting other people know about you.
However, I can't find anything on the settings page to set such a signature. There is an option do show/not shot other user's signatures.
Has something changed or am I missing something?
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Should I use quartus prime standard documentation for lite version?

January 19, 2016, 9:14 am
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Max10 Unique Identifier

January 19, 2016, 9:17 am
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Haven't been able to find information on this.

Do MAX10 chips have unique identifiers associated with them?
Something like a serial number, some unique ID that you can use to tell two chips of the same device number apart?
If there is a unique ID, An official source would be appreciated.

Thanks.
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Modular SGDMA Streaming

January 19, 2016, 10:01 am
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Hi,

I'm trying to stream data from an ADC to my DDR RAM. I’ve hit a roadblock with using the modular SGDMA core to do streaming to memory mapped transfers to DDR RAM. An interrupt that is supposed to go off when the transfer is complete never goes off. This isn’t because the data never stops being written but is actually because the data never begins to be written. I’ve noticed this because I print out some of the memory addresses during the wait for the interrupt -> the values that get written out don’t correspond to the values being fed into the SGDMA. I’ve noticed issues which point to either a software or hardware problem.





The software issue is that the IOWR and IORD commands don’t seem to be working correctly.


IOWR_32DIRECT(MEM_IF_DDR2_EMIF_0_BASE, testNumber, testNumber);


IORD (MEM_IF_DDR2_EMIF_0_BASE, testNumber);


/////////////////////////////////////////////////////////////^Doesn’t work
memcpy(MEM_IF_DDR2_EMIF_0_BASE + testNumber*sizeof(int), &testNumber, sizeof(testNumber)); ->writing


memcpy(&value, (MEM_IF_DDR2_EMIF_0_BASE+testNumber*sizeof(int)), sizeof(int)); ->reading

////////////////////////////////////////////////////////////^Works


I’m not sure if this is because in my tests I am writing to RAM, I will look into that, but this is an issue since the data transfer descriptor is initialized using the IOWR_32DIRECT function. I don’t think this is the issue though because I’m able to call these same functions successfully when I do memory-mapped to memory-mapped data transfers. I've attached the c file that I'm using to test the streaming data transfer (main.c), the line that doesn't work is #74: if (sgdma_interrupt_fired == 1) -> I've changed this to a while check and noticed that the interrupt never gets asserted.


The next area that I think might be an issue is the way I collect data from the incrementing register (the one I’m streaming data from). I simply connected the bus streaming data bus to the streaming sink of the write master in the Qsys project. I have an image of that project with the connection circled (Qsys.png). Is that the correct way to connect streaming data to a Qsys project? Is there anything that’s obviously wrong with the way I’ve set up the connections? Any advice on how to approach figuring out why the interrupt I need doesn’t go off?
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Want to determine which version of firmware the FPGA is loaded with

January 19, 2016, 10:25 am
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Greetings!

I have a StratixV dev kit and am using quartus II 64-bit software. A long time ago, some version of firmware was stored in the FPGA and no one knows which version it was.

Is there a way to read back the checksum of the firmware the FPGA is loaded with using quartus or some other tool?

I'm very green to Altera chips and their software, so please be specific as possible.

Thanks,
Jason
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Stratix V Development Kit Transceiver Clock Settings

January 19, 2016, 7:16 pm
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I'm new to FPGA and need to use the transceiver toolkit to transfer the data at rate from 5000MBps up to 10000MBps. After searching some information I download one sample project from http://www.alterawiki.com/wiki/Transceiver_Toolkit, which is as follows:

http://www.alterawiki.com/uploads/7/...h_11p3gbps.qar


For this project, the Data rate by default is set as 11300MBps. While when I was trying changing it to some random value between 5000MBps and 10000MBps by using Qsys, some of the value cannnot be set. Even though some of the value is set successfully and can compile without any problem. But the thing is after I program it into the FPGA, the transceiver links cannot operate properly.

Can I know what is the rule to adjust the base rate for this board?
Attached Images
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Stratix V Development Kit Transceiver Clock Settings

January 19, 2016, 9:15 pm
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I'm new to FPGA and need to use the transceiver toolkit to transfer the data at rate from 5000MBps up to 10000MBps. After searching some information I download one sample project from <a href="http://www.alterawiki.com/wiki/Transceiver_Toolkit" target="_blank">http://www.alterawiki.com/wiki/Transceiver_Toolkit</a>, which is as follows:<br>
<br>
<a href="http://www.alterawiki.com/uploads/7/75/SV_7ch_11p3gbps.qar" target="_blank">http://www.alterawiki.com/uploads/7/75/SV_7ch_11p3gbps.qar</a><br>
<br>
<img src="http://www.alteraforum.com/forum/attachment.php?attachmentid=11723&amp;stc=1" border="0" alt=""><br>
For this project, the Data rate by default is set as 11300MBps. While when I was trying changing it to some random value between 5000MBps and 10000MBps by using Qsys, some of the value cannnot be set. Even though some of the value is set successfully and can compile without any problem. But the thing is after I program it into the FPGA, the transceiver links cannot operate properly.<br>
<br>
Can I know what is the rule to adjust the base rate for this board?
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Setting up RS232 protocol on DE0 board?

January 19, 2016, 10:16 pm
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Hi! Total newbie here, I was wondering if anyone can help me out with setting up my TAB board to transmit messages, on a loop, from my TAB board from its Rx and Tx terminal.

My whole idea is like this:

1) DE0 sends looping messages via RS232 pins (Rx / Tx)
2) Goes to a IC chip converter to convert the signals to the appropriate voltage (5v to 3.3V I believe)
3) Goes from IC chip back to the PC via the USB/RS232 port and is displayed on the PC via Tera Term or HyperTerminal

Issues im facing: Getting the codes/protocols or blueprints to set up the looping messages on RS232.

Any help is appreciated, thanks in advance!
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Remote System Debug over Ethernet Cyclone V / Arria V

January 19, 2016, 11:09 pm
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Differences between LVDS, true-LVDS, emulated-LVDS and mini-LVDS

January 20, 2016, 5:13 am
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Hi,
I am designing a board with MAX 10 FPGA. I am really confused by all these LVDS standards. I have gone through the datasheets and user guides. But nowhere do I get any description about what all these standards really mean. I am well aware of LVDS, but I am just not able to understand the meaning of true-LVDS, emulated-LVDS and mini-LVDS. I am not finding any source which explains the differences between these.
Can someone please point out the differences, or provide some good document.
regards,
rajesh
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Quartus Prime Lite IP Cores compiling

January 20, 2016, 6:14 am
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Hi, My name is Eloy Navarro, and I have a doubt about compiling with Quartus Prime.

The fact is that I was used to Ciclone III family with Quartus 10.1, having no problems to compile and program IP Cores with time limitation.
Now I have moved to Cyclone V and I'm unable to compile a project with IP Cores (FFT is the one I'm trying).
I am working with Quartus 15.1 Lite Edition and a BeMicro CV A9 as target board.

The user guide (ug_fft.pfd) tolds to manually add .qsys .qip and .sip.
Once attached, the compilation exits with errors ("can't generate netlist output files because "..." is an OpenCore Plus time-limited file." and "can't generate netlist output files because the encrypted file "..." is not available.")

I have not added anything else.
I don't know if these errors are related with something missing, licensing, libraries or maybe I'm doing all wrong in this new Quartus.



Thanks in advance and Best regards,
Eloy
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F2H Avalon Bridge is stuck... How to release?

January 20, 2016, 8:18 am
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Hello,


In my design, I use the F2H Avalon Bridge to directly access the SDRAM Memory Controller located in the HPS.


For some reason, the bridge is stuck (the hps_0_f2h_sdram0_data_waitrequest signal, which is coming from HPS is stuck to HIGH). Why? Actually no one should access the SDRAM Controller in HPS besides FPGA through the Avalon bridge... MPUs do not run any code, only U-Boot is located in the external DDR3 memory...


Should I run the "bridge_enable_handoff” command from the U-Boot prompt in order to open the Avalon Bridge?


How can I release the Avalon Bridge? How can I debug why it's stuck?

Thank you!
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cheap DE0 NANO SOC and DE0 NANO expansion board (CAPE) for altera forum members

January 20, 2016, 8:41 am
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Hi all.

I´m designing a expansion board (for my own) for the de0 nano soc, it´s compatible with the de0 nano too.

I place this post for two reasons:

-In order to ask if anybody is interested in this board to make a group order.
-For share the project.

IM NOT INTENDED TO EARN MONEY WIT THIS BOARD.

The following elements are pending to place: HDMI DDR,SLIDERS SOME LEDS ... ANY IDEAS?

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IP Regeneration Policy - Quartus Prime Lite 15.1

January 20, 2016, 2:23 pm
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What has happened to IP regeneration policy? In the past, I could compile my QSYS or SOPC Builder system, and then compile my FPGA. And the FPGA build would use the result of the last Qsys/SOPC Builder build. These days, with Quartus Prime, there is an "IP regeneration policy" which has two options - "Always regenerate synthesis files for IP cores" and "Never regenerate synthesis files for IP cores". Unfortunately the latter is greyed out, and the former is the only thing you can select. Changing the setting in the QSF file doesn't help either - it ignores it!

My issue is that I have a DDR3 hard memory interface in my Cyclone V design, built with Qsys. It takes over 10 minutes to generate the Qsys model for synthesis. So when I hit Generate HDL in Qsys I wait 10 minutes and it's done. And then I hit compile in Quartus and it does it all again. Even if I don't touch the Qsys file, it ALWAYS spends over 10 minutes rebuilding the Qsys system. And, to make matters even worse, if I compile a new file into my project, and have a syntax error in my file, Analyse Current File doesn't spot it, so I hit "Start Compilation" and it spends 12 mintues rebuilding the Qsys system and THEN checks the new file and says - "Ooops, you messed up there and I can't get any further". This is a HUGE waste of time.

Can the tool be changed to stop regeneration of IP UNLESS the files have changed? Please?
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