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EP4CE75 programmer : verification failed for device number 1

January 20, 2016, 6:04 pm
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1. I have checked the schematic and PCB. Both of them are right.
2. This chip(flash and fpga) and schematic were used in another board without any problem.
3. I used two usb-blasters and three PCs to program. failed with the same problem.
4. I repalced the flash.
5. signaltap works well.

win7+quartus II 13.1+EP4CE75+M25P64
use jtag mode to program(jic file)

wrong infomation:
209027 verification failed foe device number 1.
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How to resolve Path to SOPC Builder directory is not found

January 21, 2016, 12:42 am
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I am just starting with Altera OpenCL. I have been able to compile and run some of the example designs. Yesterday I tried using the emulator. After some missing environment variables I got it working. Today I tried some more emulations but whenever I want to compile, either for emulator or for chip I get the message:
Code:
aoc: Unable to determine the execution envoronment of the Altera SDK for OpenCL
aoc: Detailed error: Internal error: Path to SOPC Builder directory us not found!
I assume I have an enviroment variable wrong, but which one, and how do I find out which it is. I could run checks on all variables but that takes a lot of time. Could you point me to the right variable?

Or, if it has another couse, correct me and point me to the correct problem.
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PowerPlay very low IO current estimation

January 21, 2016, 3:10 am
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Hi,

I have a Cyclone V device, with 64 1.8V IO pins planned for ADCs and DACs (sampling about 125M).
Now, i have ran PowerPlay analyzer to estimate the power usage of this design. I set the default toggle rate to 125M and the result came back as 30mA for VCCIO and also 30mA for VCCPD.

I am wondering if these results are realistic? 30mA for 64 pins seems very low...

Thanks :)

Pets
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mSGDMA response FIFO stucks if receives 256...512 bytes

January 21, 2016, 5:49 am
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I use Quartus II 64-Bit Version 15.02 Build 153
mSGDMA is used in ST to MM mode

in the Control register set bits
DESCRIPTOR_CONTROL_GO_MASKDESCRIPTOR_CONTROL_ERROR _IRQ_MASK
DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK
DESCRIPTOR_CONTROL_EARLY_DONE_ENABLE_MASK
DESCRIPTOR_CONTROL_END_ON_EOP_MASK
Transfer length is 8192
1) ST source generate packets 100...248 , bytes with controlled period
reset mSGDMA
push descriptor
ST generates packet
read response in FIFO
read data
OK
1) ST source generate packets 256...512 , bytes with controlled period
reset mSGDMA
push descriptor
ST generates packet
response fill level is incremented
read response in FIFO - response fill level is not decremented, "response FIFO is empty" is 0
data is correct
push descriptor
ST generates packet
response fill level is incremented
read response in FIFO - response fill level is not decremented, "response FIFO is empty" is 0
data is correct
mSGDMA receives next portion of data, but response FIFO is stucks

Have anybody thought on solving this trouble?
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Documentation request for a SoCrates II (Cyclone V - SX) development kit from EBV.

January 21, 2016, 11:54 am
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Dear all,

I need your help in getting a link to the documentation of SoCrates II. I need to use SoCrates-II kit to evaluate Gigabits transceiver suitability for a R&D work.

I could not find user guide/board documentation neither nay reference design about SoCrates II board. I wrote to EBV , there I was directed to some engineer yet no response.

any link / hint to documentation like user manual/guide of the development kit, device pinout description and board configuration?..... all i get from ALTERA / EBV web is product marketing pamphlet.

thanks in advance for your time!

cheers,
Mirza



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Max 10 Eval Kit - creating .pof file

January 21, 2016, 11:54 am
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The Max 10 FPGA Evaluation kit User Guide instructions for generating a .pof file (to burn into Flash) do not appear to match the menus I see on Quartus 15.01 lite. Does anyone have example settings for the assignment/device and assignment/settings menus and Generating a .pof file,or a step-by-step "my first FPGA" style tutorial I can use as a starter guide? The Max 10 FPGA Configuration User Guide and Max 10 FGA Evaluation Kit User guide both have the same procedure but appear to be written for a different version of Quartus.
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Determine Pipeline Depth

January 21, 2016, 2:30 pm
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Does anyone know a quick way to determine how many pipeline stages are created for a compiled kernel? I tried calculating the number based on the kernel clock frequencies and overall execution time, but it doesn't seem to give an accurate result.
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New 15.1 install - Quartus Prime can't see devices

January 21, 2016, 4:09 pm
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I just jumped from v 11.1 to 15.1. 15.1 downloaded and installed itself, and appeared to install devices. However, when I start Quartus, I get a pop-up:
"You successfully installed the Quartus Prime software, but did not install any devices. Do you want to launch the device installer to add devices?"
Hmm, I did install devices, but I click Yes anyway.
then I get:
"The Quartus Prime software cannot launch the Device Installer for Widnows 8 and newer operating systems" and words about launching from the Start button.
Hmm, I'm running Windows 7, but OK, I launch Device Installer from the Start button. I click Next over to the Select components dialog box. It shows everything clicked and grayed out. Wish I could make the screen shot bigger:


I click Next and get this message:
"You didn't select any components to install. You need to select at least one component to be able to continue. Any components that are selected and appear in dimmed text are already installed."

So they're already installed, but when I start the app, it doesn't think they're installed.
I tried re-booting, no help. Based on a post from last October, I'm going to try uninstalling and re-installing with the Quartus install files and the device files in the same folder.

Anybody have other ideas? Does this behavior maybe have to do with licensing (4 of us share a single floating license)?
Is this a bug fixed in 15.1.1 (currently downloading that)?
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Conflicting VCCIO settings

January 21, 2016, 6:52 pm
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I'm creating a design for Arria 10 that uses the Bitec HDMI IP to receive and transmit video + auxilliary data. A Bitec HDMI input output board is connected to an ReflexCES ALARIC development board via an FMC connector. Video lines use the high speed transceiver, but auxilliary data is transmitted via LVDS pins as i2c. My question is, how do I initialize these pins properly to work as i2c pins.

My input/output parameter in the top Verilog design are:

output hdmi_rx_hpd_n,
inout hdmi_rx_i2c_sda,
input hdmi_rx_i2c_scl,

input hdmi_tx_hpd_n,
inout hdmi_tx_i2c_sda,
inout hdmi_tx_i2c_scl

Pin characteristics are:
I/O Standard, 1.5V

Pins used are:
AM6, AM5, AP9, AH10, AH9, AJ7

Quartus analysis and synthesis works alright, but when running the fitter I get the following error:

Error (11924): Bank '3A' has conflicting VCCIO settings
Error (11928): 'hdmi_rx_hpd_n' with I/O standard 1.5 V, was constrained to be within bank '3A'
Info (11929): '1.5V' is a valid VCCIO value
Error (11928): 'fmc_clk_dir' with I/O standard 1.8 V, was constrained to be within bank '3A'
Info (11929): '1.8V' is a valid VCCIO value
Error (16297): An error has occurred while trying to initialize the plan stage.

I'm using Quartus 15.1 Standard, no patch.

Any idea, what I did wrong?

Klaus
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quartus_pgm command line

January 21, 2016, 7:00 pm
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Hi,

I need to program file to alter CPLD in other development language. Commnd line is one method, or have any other method?
While use command line, how can I get the programming progress in real-time?
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A10 LL 10G MAC and XAUI PHY Reference Design

January 22, 2016, 2:04 am
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Receive Ethernet Packets on DE-4 board with NIOS II

January 22, 2016, 2:09 am
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Hi, :)
I have a DE-4 board to which I would like to receive Ethernet packets from my PC. I have run the example provided with the tutorial (using triple-speed Ethernet on DE-4 boards) and it works as expected. I have got the exact same architecture as specified on that tutorial, with the NIOS II soft processor. But when I remove one end of the Ethernet cable and connect that end to my laptop's Ethernet port, ISR does not seem to be firing (Here I removed the cable on eth0 interface and kept the connection on eth1). I checked traffic on the Ethernet network using Wireshark and packets are sent out from the laptop (mostly broadcasts).

This is what I have got working now. (loopback on eth0)

Code:
#include <altera_avalon_sgdma.h>
#include <altera_avalon_sgdma_descriptor.h>
#include <altera_avalon_sgdma_regs.h>

#include "sys/alt_stdio.h"
#include "sys/alt_irq.h"
#include <unistd.h>

// Function Prototypes
void rx_ethernet_isr (void *context);

volatile char *onchip_control = (char *) 0x00000FFF;
volatile char *onchip_data_rx = (char *) 0x00001000;
volatile char *onchip_data_tx = (char *) 0x00008000;

// Global Variables
unsigned int text_length;

// Create a transmit frame
unsigned char tx_frame[1024] = {
        0x00,0x00,                                                // for 32-bit alignment
        0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,        // destination address (broadcast)
        0x01,0x60,0x6E,0x11,0x02,0x0F,        // source address
        0x03,0xF0,                                                // length or type of the payload data
        '\0'                                                        // payload data (ended with termination character)
};

// Create a receive frame
unsigned char rx_frame[1024] = { 0 };

// Create sgdma transmit and receive devices
alt_sgdma_dev * sgdma_tx_dev;
alt_sgdma_dev * sgdma_rx_dev;

// Allocate descriptors in the descriptor_memory (onchip memory)
alt_sgdma_descriptor tx_descriptor                __attribute__ (( section ( ".descriptor_memory" )));
alt_sgdma_descriptor tx_descriptor_end        __attribute__ (( section ( ".descriptor_memory" )));

alt_sgdma_descriptor rx_descriptor          __attribute__ (( section ( ".descriptor_memory" )));
alt_sgdma_descriptor rx_descriptor_end  __attribute__ (( section ( ".descriptor_memory" )));


/********************************************************************************
 * This program demonstrates use of the Ethernet in the DE4 board.
 *
 * It performs the following:
 *  1. Records input text and transmits the text via Ethernet after Enter is
 *    pressed
 *  2. Displays text received via Ethernet frame on the JTAG UART
********************************************************************************/
int main(void)
{
        // Open the sgdma transmit device
        sgdma_tx_dev = alt_avalon_sgdma_open ("/dev/sgdma_tx");
        if (sgdma_tx_dev == NULL) {
                alt_printf ("Error: could not open scatter-gather dma transmit device\n");
                return -1;
        } else alt_printf ("Opened scatter-gather dma transmit device\n");

        // Open the sgdma receive device
        sgdma_rx_dev = alt_avalon_sgdma_open ("/dev/sgdma_rx");
        if (sgdma_rx_dev == NULL) {
                alt_printf ("Error: could not open scatter-gather dma receive device\n");
                return -1;
        } else alt_printf ("Opened scatter-gather dma receive device\n");

        // Set interrupts for the sgdma receive device
        alt_avalon_sgdma_register_callback( sgdma_rx_dev, (alt_avalon_sgdma_callback) rx_ethernet_isr, 0x00000014, NULL );

        // Create sgdma receive descriptor
        alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor, &rx_descriptor_end, (alt_u32 *)rx_frame, 0, 0 );

        // Set up non-blocking transfer of sgdma receive descriptor
        alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor );

        // Triple-speed Ethernet MegaCore base address
        volatile int * tse = (int *) 0x00083000; //tse.control_port at Qsys address map

        // Initialize the MAC address
        *(tse + 3) = 0x116E6001;
        *(tse + 4) = 0x00000F02;

        // Specify the addresses of the PHY devices to be accessed through MDIO interface
        *(tse + 0x0F) = 0x10;
        *(tse + 0x10) = 0x00;

        // Write to register 20 of the PHY chip for Ethernet port 0 to set up line loopback
        *(tse + 0xB4) = 0x4000;

        // Set the PCS to operate at SGMII mode        and enable SGMII auto-negotiation
        *(tse + 0x94) = *(tse + 0x94) | 0x0003;

        // Set PHY address for accessing the PHY chip for Ethernet port 1
        *(tse + 0x10) = 0x01;

        // Write to register 16 of the PHY to enable automatic crossover for all modes
        *(tse + 0xB0) = *(tse + 0xB0) | 0x0060;

        // Software reset the PHY chip and wait
        *(tse + 0xA0) = *(tse + 0xA0) | 0x8000;
        while ( *(tse + 0xA0) & 0x8000  )
                ;

        // Enable read and write transfers, gigabit Ethernet operation, and CRC forwarding
        *(tse + 2) = *(tse + 2) | 0x0000004B;

        alt_printf( "send> " );
        text_length = 0;

        while (1) {

                char new_char;
                tx_frame[16] = '\0';

                //Read the PCIe received data
                int i;

        while( *onchip_control != 'B' ) ;// polling the control byte
        i = 0;
        while( (new_char = *(onchip_data_tx + i) ) != '\n' ) {
            if (text_length < 1007) {

                // Add the new character to the output text
                if ( new_char >= 'a' && new_char <= 'z' )
                    tx_frame[16 + text_length] = new_char - 'a' + 'A';
                else if ( new_char >= 'A' && new_char <= 'Z' )
                    tx_frame[16 + text_length] = new_char - 'A' + 'a';
                else
                    tx_frame[16 + text_length] = '#';

                text_length++;

                // Maintain the terminal character after the text
                tx_frame[16 + text_length] = '\0';

            }
            i++;
        }

                *onchip_control = 'K' ; // keep the control in the board until receive

                // Create transmit sgdma descriptor
                alt_avalon_sgdma_construct_mem_to_stream_desc( &tx_descriptor, &tx_descriptor_end, (alt_u32 *)tx_frame, 1024, 0, 1, 1, 0 );

                // Set up non-blocking transfer of sgdma transmit descriptor
                alt_avalon_sgdma_do_async_transfer( sgdma_tx_dev, &tx_descriptor );

                // Wait until transmit descriptor transfer is complete
                while (alt_avalon_sgdma_check_descriptor_status(&tx_descriptor) != 0)
                        ;
        }

        return 0;
}

/****************************************************************************************
 * Subroutine to read incoming Ethernet frames
****************************************************************************************/
void rx_ethernet_isr (void *context)
{
        int i;

        // Wait until receive descriptor transfer is complete
        while (alt_avalon_sgdma_check_descriptor_status(&rx_descriptor) != 0)
                ;

        // Clear input line before writing
        for (i = 0; i < (6 + text_length); i++) {
                alt_printf( "%c", 0x08 );                // 0x08 --> backspace
        }

        // Output received text
        alt_printf( "\nreceive> %s\n", rx_frame + 16 );

    while( *onchip_control != 'K' ) ;// polling the control byte

    for (i = 0; i < (6 + text_length); i++) {
    *(onchip_data_rx + i) = rx_frame[16 + i];
    }
        *onchip_control = 'H' ; // pass the control right to the host PC

        // Reprint current input line after the output
        alt_printf( "\nsend> %s", tx_frame + 16 );

        // Create new receive sgdma descriptor
        alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor, &rx_descriptor_end, (alt_u32 *)rx_frame, 0, 0 );

        // Set up non-blocking transfer of sgdma receive descriptor
        alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor );

        text_length = 0;
}
How do I change the above to receive Ethernet traffic on DE-4? :( Sorry if this is too simple and thanks a lot in advance!
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can i create netlist from vhdlp file

January 22, 2016, 4:03 am
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if someone has an encrypted version of my ip. that is i encrypted my vhdl to produce vhldp file can he use this file to implement it on hardware or will he be only able to simulate my work to check it out.
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what kind of refclk standard do alt2gxb need?

January 22, 2016, 8:10 am
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I use ArriaGX in a PCIe design, and use ICS9DB403 to generate 100MHz refclk for alt2gxb. But GXB cannot receive any refclk signal. ICS9DB403 generate a HSCL standard signal. I wonder if alt2gxb could accept this kind of signal?
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Quartus 12.1 SP1: "m10k resources"

January 22, 2016, 8:28 am
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Hi,
I am using Quartus 12.1 SP1, cyclone V (5CEFA5U19I7N).
I have an error:
" Internal Error: Sub-system: U2B, File: /quartus/db/u2b/u2b_av_m10k_param.cpp, Line: 2018."

when I searched it, I found a similar problem with a fix but for Quartus II 13.0 DP2;

is there any fix/solution anyone is aware of? any advice?

Thank you,
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Quartus prime lite v15.1: customizing colors/font size?Hi,

January 22, 2016, 1:38 pm
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Hi all,

The new Quartus prime lite 15.1 has the home screen in a very pale blue and the recent project listing has white font. I find that hard to read. I try to change the font color but I could not find the setting under either Tools|Customize or Tools|Options. Did I missed it? Is there a way to change the colors as well?

Thanks
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Is it worth to upgrade from 15.0 to 15.1?

January 22, 2016, 1:41 pm
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Hello, I've been using 15.0 for a while and not sure if I should upgrade to 15.1? I'm only working with the Cyclone V FPGA and not doing any ARM development. Are there any really big differences between the two version?

Thanks,
Joe
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Problem : University VWF

January 22, 2016, 2:09 pm
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Hello everyone. I'll start by saying that my english sure it's not the best, i apologise for that; but i'll try anyway to be as clear as possibile , so i'm trying to simulate this fives clockS but i'm getting this error :(

1st i've create a new verefication / debbugin files which is ==> University Program VWF , and i've added my In/Out and i get the following error !



Please help me as soon as possible thanks in advance.
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Quartus_pgm command line

January 22, 2016, 5:22 pm
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Hi

How can I get the program progress in realtime when use Quartus_pgm cmd line in other development language.
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DE1-SoC MSEL [00000] or [01110] Unable to program FPGA from HPS

January 23, 2016, 12:52 am
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Hello together,

I'm just getting started with my DE1-SoC, and I seem to be unable to program the FPGA from Linux w/ frame buffer or LXDE/UBUNTU. I have set the correct MSEL[4:0].

root@socfpga:~# ERROR: Incompatible MSEL mode set. Cannot continue with FPGA programming.

If I program the FPGA from Linux w/o frame buffer (01010), it works fine just as configuring from EPCS (10010).
Am I missing anything, or is there a way to test where the problem is?

Thanks,
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