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Reloadable Video Pattern Generator

January 23, 2016, 5:38 pm
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Hi Guys,

Can someone suggest a simple reloadable video pattern generator via a .mif file?
I used the regular color bar generator and it works fine.Now, I need a reloadable one
that is simple , i.e. no NIOS II.

Any suggestions?

Thanks,

S.
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Exploring Altera product, would like to know what software skill is required.

January 23, 2016, 10:17 pm
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I am exploring the possibilities to use FPGA products to speed up our software applications which is running on CPUs now. It is a large scale (run on many computers) application which is very computational intensive. It processes a large amount of images.
I would like to know how FPGA products from Altera can help, including what kind of hardware and software. I also want to know whether we need software skills such as programming in VHDL or Verilog. We have engineers proficient in high level programming languages such as C++. Is OpenCL sufficient?

Thank you.
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Dealing with Cyclone II SRAM

January 24, 2016, 3:11 am
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Hello, I need to program SRAM on vhdl, when I read some tutorials I found difference in the types of pins and the pin table I have. please may any one lead me to design SRAM tutorial according to cyclone II. Many thanks.
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Having hard time choosing FPGAs used in DNN

January 24, 2016, 3:17 am
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I was new to FPGAs but I'll use OpenCL for programming. I was planing to run Deep learning algorithm on FPGAs.

Even though I will train the models on my computer, speed still need to be considered.

The algorithm that I will use is similar to super-resolution algorithm.

What kind of FPGA should I choose?
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Arria 10 hosted debugging

January 24, 2016, 8:08 am
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Hello Guys,

Is there any hosted design example for Arria 10? I'm having diffiiculty searching online, most examples are for Cyclone or Arria V. What I'm looking for especially is the DS-5 debug script for Arria 10, that loads u-boot and eventually the application. A10 It uses bootloader as SSBL vs preloader of Arria V, and so I think just substituting references to the preloader in existing .ds scripts with that of u-boot bootloader is not enough because of their differences (where to tbreak in u-boot just before target .axf is loaded? What about device tree?).

Thanks and best regards.
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Open Source Linux DMA driver

January 24, 2016, 10:33 am
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Hi, I am new to FPGA use and seeking helpful advices.

Here is what I need on Linux:

Application needs to use the following interface to communicate with FPGA on PCIe:

fpga_processing(int fpga_channel, char *input_buf, int input_size, char *out_buf, int *output_size);

* fpga_channel: specify which fpga to use ( assuming there are multiple on board )
* input_buf stores raw data ( of size input_size) to be passed to FPGA
* FPGA stores processed data at output_buf, and returns its size to output_size


My question: are there any Linux DMA drivers ( preferably open source ones ) to accomplish this?


Thanks in advance for any info.
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Video Pattern-Generator (e.g. color-bar) reloadable

January 24, 2016, 12:26 pm
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Hi Guys,

Can someone suggest a simple reloadable video pattern generator via a .mif file?
I used the regular color bar generator and it works fine. Now, I need a reloadable one
that is simple , i.e. no NIOS II.

I am thinking of using the VIP IPs based design, such as using a buffer-reader, video sequencer, etc.
Yeah, I could us a memory and some counters, as was suggested, but I don't want to start from scratch.

Any suggestions?

Thanks,

S.
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Ethernet traffic to DE-4 Board

January 24, 2016, 8:12 pm
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Hi,
I need to receive live Ethernet traffic to my DE-4 board, which I have connected to a PC through PCIe. What is the easiest way to do this? I just want to get some traffic, not to send anything from the DE-4 board to any host.

I tried out the example on using TSE on DE-4 boards and its working fine. Is there a way to change that such that the DE-4 would receive traffic from another host, not packets generated on the board?

Thanks in advance! :D
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What is the max ddr2 clock frequency support by cycloneiv?

January 24, 2016, 11:03 pm
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For EP4CE30F23C6N device, what is its max clock to drive external ddr2? I just find one statement on handbook "support to DDR2 SDRAM interface up to 200Mhz"

Where I can find the detail specification about my concerns?

I need to have this clock value to estimate the data buffer bandwidth.

Thanks a lot.
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Add device to Quartus II . Cyclone II to QII Web Edition 64 bits.

January 25, 2016, 2:45 am
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Hi,

Boards: DE2 and DE1-soc
FPGA: Cyclone II on DE2 and Cyclone V on DE1
SO: linux 64 bits
Quartus II Web edition : 13.0sp1 (32bits) support Cyclone II and Cyclone V . Support DE2 but not DE1
Quartus II Web edition : 15.1 64bits) support Cyclone V but not Cyclone II. Support DE1 but not DE2


I would like work with DE2 and DE1 and only one Quartus II application. Can I add Cyclone II to linux Quartus II Web Edition 15.1 for compatibility with DE2 or I need work with 2 versions of Quartus II.

Thanks
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can I use 10G PHY IP core without Transceiver Reconfiguration controller

January 25, 2016, 3:41 am
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Dear Sir,
I am using 10G PHY hard ipcore. I am not changing the reconfiguration of 10G PHY IP core dynamically. So can I use 10G hard ip core without transceiver reconfiguration controller in Stratix V GX and Arria10 FPGAs. Can you reply me regarding this.
with regards,
y v subba rao
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DE0-Nano SoC Kit - Questions about Qsys and automatic tcl pin assignments

January 25, 2016, 4:20 am
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Hello, I'm writing here after a two-days research on internet, without successful answer to my question(s).

I'm facing problems with the part of the HPS-FPGA tutorial included in the CD for DE0-nano platform that explains how to automatically assign pins, and I found the identical problem following this guide.
I'm running Quartus 15.1 Prime Edition on both Ubuntu 14.04.3 LTS (ok, I know it isn't supported) and Windows (that is supported instead, so my question should be valid).

Here's the problem:
when Qsys project is generated, and included in Quartus project, I throw an analysis and synthesis task. Then I should execute the TCL script for pin assignment... BUT: after the execution, I see no variations in the assignment table and also in the pin planner window. On Ubuntu I also get some errors during the execution of the script, although the Quartus software and all the Altera Suite work smoothly on this system.

Here's the question:
what exactly the TCL pin assignment script does? should I see changes in the pin assignments or not?
extra: does the Qsys system need to be toplevel in my Quartus project?
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DE1-SoC MSEL [00000] or [01110] Unable to program FPGA from HPS

January 23, 2016, 12:52 am
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Hello together,

I'm just getting started with my DE1-SoC, and I seem to be unable to program the FPGA from Linux w/ frame buffer or LXDE/UBUNTU. I have set the correct MSEL[4:0].

root@socfpga:~# ERROR: Incompatible MSEL mode set. Cannot continue with FPGA programming.

If I program the FPGA from Linux w/o frame buffer (01010), it works fine just as configuring from EPCS (10010).
Am I missing anything, or is there a way to test where the problem is?

Thanks,
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VHDL sequential vs concurrent statement

January 25, 2016, 10:50 am
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Hi,

I am bit confused over sequential vs concurrent statements in VHDL. In almost all books, it is mentioned as process body will contain sequential statements. Consider following code fragments.
Code:
architecture concurrent  of xyz is

signal sig1, sig2 : std_logic;

begin
  out  <=  sig1 or sig2;
  sig1 <= in1 and in2;
  sig2 <= in1 or in2;

end architecture concurrent;
Code:
architecture sequential of xyz is

signal sig1, sig2 : std_logic;

begin

process(all)
begin
  out  <=  sig1 or sig2;
  sig1 <= in1 and in2;
  sig2 <= in1 or in2;

end process;
end architecture sequential;
Both fragments results in same RTL view. Whats the difference?

Thank you,
sawaak
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question about SDK license for OpenCl

January 25, 2016, 11:03 am
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Hi there I am a student and I have some question about the SDK license for OpenCL:

1. Do you have special price license for academic use?
2. Is it possible that the license can be use for 2 people?
3. Is it possible that the license can be use in two computers (1 desktop, 1 laptop)?
4. How long is the license?

Also I found a link about the purchase of the license, its cost 200 dlls.
http://www.terasic.com.tw/cgi-bin/pa...o=526&PartNo=7

Thanks a lot in advance and I will waiting for your response.
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Transceiver Toolkit - "locked" indicators

January 25, 2016, 11:39 am
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I'm looking for some further explanation of the LOCKED indicators in TTK.

Currently I use version 15.0 build 153 of System Console.

My questions are:
--> Is it normal for the Rx LOCKED indicators to blink green and then yellow with a properly functioning link? If so, what is this indicating? Does the TTK only say "LOCKED" when data is coming across the link, and then goes unlocked after?

I have a loopback cable that connects Tx to Rx on 4 channels. Whether or not the cable is actually connected, I see "LOCKED to ref" and "LOCKED to data" fluctuate between green and yellow within TTK. My initial interpretation was that "LOCKED to ref" would only turn green when I plugged my loopback connector in...and would stay green until the cable was disconnected. However, since TTK is saying "LOCKED to ref" without any cable on the interface, I'm a bit confused. The toggling of LOCKED also occurs whether or not I'm running something with TTK.

I put SignalTap on the "lockedtoref" and "lockedtodata" signals from the XCVR and those are also toggling unexpectedly; therefore I think it's not just the TTK GUI being flakey.
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BEMICROMAX10 and the provided SDRAM in Qsys - ROWS COLUMNS AND TIMING !

January 25, 2016, 2:27 pm
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I am doing my first memory card project, doing the SLS evaluation for the SD/eMMC card IP. Would like to get a roll on this. When i am in Qsys plugging in the ram info the amount of system ram is drastically different from what i am expecting.

The ram on the arrow website (where i bought the bemicromax10 from) is IS42S16400 . Here is that data sheet
http://www.issi.com/WW/pdf/42S16400.pdf
The data sheet proclaims that " Each 16,777,216-bit bank is organized as 4,096rows by 256 columns by 16 bits."
The 64Mb (8MB) ram is supposed to be what is on the board.
The data sheet also does proclaim that "Internallyconfigured as a quad-bank DRAM with a synchronousinterface."

When i plug this into Qsys it spits out back at the bottom "0 Megabytes"


please do take note that i am using the Avalon Sd-Ram Controller .

I am following the SLS pdf on setting up this system for the SD/eMMC card Host Controller. I would post the PDF if i could as it is outdated (wants me to do it in cyclone IV or III , i forget which) but the IP claims that it is good for MAX10
Thanks ! Also if someone could help me decipher what to put in for the timing, i would be grateful !
Attached Images
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NIOS II Non-GUI Simulation in ALtera ModelSim Starter

January 25, 2016, 7:06 pm
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Hi,

Can I please know how to switch off the GUI and run the simulation for NIOS II simulation on Alter Model Sim starter version in Non-GUI mode.I am running on windows.

Thank you
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Read VHDL files using TCL command

January 26, 2016, 4:23 am
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Hi All,

How could I read the VHDL source files into Quartus-II using the TCL commands?

I'm seeking for something like following:
read_rtl <path_to_rtl_file>

Thank you
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Where Quartus-II keep a list of source files?

January 26, 2016, 4:29 am
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Hi All,

Where the Quartus-II keep a list of the source files? I mean does it maintain a file like *.QSF where it keep a list of the source files?

Thank you
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