Deca Kit Mipi Camera Orientation?

January 26, 2016, 10:16 am

≫ Next: DECA Kit Lab 8 MIPI Camera Working?

≪ Previous: Where Quartus-II keep a list of source files?

Hello,

I am working on the Deca Kit Lab 8 from the wiki, and I would like to confirm the MIPI camera orientation. Neither the Deca Kit user guide nor the Lab 8 guide address this issue, nor can I find any picture with the camera actually plugged into the Deca Kit.

On the DECA board by the MIPI interface, there is an bold arrow, presumably indicating pin 1.

On the camera ffc when viewing the connector, there is a label 1, again presumably indicating pin 1.

Assuming these must be pressed together, the camera would then orientate with the ffc and camera hanging off the edge of the board, camera facing the ground.
Is this correct?

If so, I have another issue.
When I compile and load Lab 8 from the wiki onto the board, the camera gets really hot, which feels unsafe.
This is why I wanted to check the orientation.
Is this normal?

Thank you for any advice.

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DECA Kit Lab 8 MIPI Camera Working?

January 26, 2016, 10:36 am

≫ Next: Quartus Software for 32-bit XP

≪ Previous: Deca Kit Mipi Camera Orientation?

Hello,

I am working with the Max 10 DECA Kit, and am working on Lab 8 from the Wiki.
When I compile the completed project, start the code on the fpga, and use the System console to start the tcl script, I get an screen that is totally aquamarine green. I can see no influence from the camera.

I've tried resizing the TPG image and turning off the TPG image with master_write_32 $nm $frm1 0, but there is absolutely no reaction on the monitor.

Do you have any advice to how I can confirm the Image Sensor is working?
Confirm the tcl commands are working?

Any other advice?

Thank you

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Quartus Software for 32-bit XP

January 26, 2016, 10:41 am

≫ Next: MAX V max and min Tco identical

≪ Previous: DECA Kit Lab 8 MIPI Camera Working?

Can someone tell me which Quartus version to download to run on a 32-bit XP machine? I lost my hard drive as well as my Quartus software. BTW, we have an Altera Programming Unit that we were told needed to run under XP because Altera did not include this unit when they upgraded their software to W7. Any comments on that? Thanks. - Bill

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MAX V max and min Tco identical

January 26, 2016, 12:56 pm

≫ Next: Is it possible to make the USB-UART interface look like a MIDI class compliant device

≪ Previous: Quartus Software for 32-bit XP

All - We are using a MAX V -40 to +125 degree device. Why is TimeQuest reporting that the same maximum Clock to Output is identical to the minimum Clock to Output. Even when we set different "Operating Conditions" in TimeQuest, those are the same also.

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Is it possible to make the USB-UART interface look like a MIDI class compliant device

January 26, 2016, 1:54 pm

≫ Next: Quartus II 13.1.4, no choice programing Cyclone V-5CGTFD9E5F35

≪ Previous: MAX V max and min Tco identical

Many dev kits come with a USB-UART interface, is it possible to make it look like a USB MIDI class compliant device so that it would automatically be detected as a MIDI device when plugged into a computer's USB port?
If so, where would I start to find out how to do it?

I am particularly interested in the DE1-SoC and DE0-Nano-SoC's USB-UARTs, but information on how to get it to work on the DE0-Nano-SoC's USB-OTG interface or on any other dev kit's USB-UART interface would also be appreciated.

Thank you.

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Quartus II 13.1.4, no choice programing Cyclone V-5CGTFD9E5F35

January 26, 2016, 4:33 pm

≫ Next: Installation of multiple license files

≪ Previous: Is it possible to make the USB-UART interface look like a MIDI class compliant device

Hi,

after installing the Quartus II 13.1 Web Edition and updating to 13.1.4 I can not set as a target device Cyclone V - 5CGTFD9E5F35, while it is supposed to support all variations of Cyclone V device family. In addition, I have checked the Subscription Edition of Quartus II device support file for Cyclone V and it is similar size as the Web Edition, so I suppose it is the same. If anyone had the same issue before and knows the solution I would be very grateful to see her/his post.

Thanks in advance

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Installation of multiple license files

January 26, 2016, 5:50 pm

≫ Next: Ethernet packets on DE-4 board

≪ Previous: Quartus II 13.1.4, no choice programing Cyclone V-5CGTFD9E5F35

This seems like a very very beginner problem, but if anyone could spare the time, please help.

I'm having two license files, one for a node-locked Quartus Prime 15.1 Standard, and one for a Bitec HDMI IP core. At the moment I have to select the Bitec license file in Quartus License Setup to synthesize my design and then later change to the Quartus license to build the output files. I can't load the two license simultaneously. Now I don't know, if I'm just looking in the wrong place or if this is not possible by design. I screened the forum and documentation about this, but didn't find any information.

Thanks!!
Klaus

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Ethernet packets on DE-4 board

January 26, 2016, 7:10 pm

≫ Next: shift_left and shift_right for large vectors freeze Quartus

≪ Previous: Installation of multiple license files

Can someone please tell me a way to receive Ethernet traffic on a DE-4 board? I've gone through the example provided in the tutorial, using TSE on DE-4, and it works fine. Now I need to receive actual network traffic on the DE-4. What is the easiest way to do this?

Thanks a lot in advance. :D

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shift_left and shift_right for large vectors freeze Quartus

January 27, 2016, 4:17 am

≫ Next: Arria 10 Fitter Error :Design requires contiguous fully bonded lanes

≪ Previous: Ethernet packets on DE-4 board

I am using Quartus 15.1.1 64 bit

I just found that shift_left and shift_right for large vectors freeze Quartus analysis and synthesis

Code:

y <= std_logic_vector(shift_right( unsigned(x), i));

where x and y are std_logic_vector(1023 downto 0) and i is an integer range 0 to 1023

Using 512 instead of 1024 have compile time of 18 seconds, but with 1024 is more than 1 hour and seem in a forever loop..

Could anyone reproduce my problem?

Thanks

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Arria 10 Fitter Error :Design requires contiguous fully bonded lanes

January 27, 2016, 4:24 am

≫ Next: Arria 10 GX PHY latency number

≪ Previous: shift_left and shift_right for large vectors freeze Quartus

Hi all

I was trying to compile my design in quartus 15.0 targeting the Arria 10 fpga device -10AX115R4F40I3SG.I ran just the tcl scripts for pin assignments present in the new Arria 10 EMIF-ddr3 IP generated. Analysis and synthesis ran successfully for the particular device . But it threw error in fitter .The error i got looks like this :

16344 Design requires 11 contiguous fully bonded lanes,but the target device for your design has a maximum of 8 contiguous lanes.Choose a different target device for your design.

Did anyone face similar issues before?

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Arria 10 GX PHY latency number

January 27, 2016, 7:40 am

≫ Next: Hardware for quartus

≪ Previous: Arria 10 Fitter Error :Design requires contiguous fully bonded lanes

Hi,

I am planning to use the Arria 10 transceivers for a low-latency application.

Is there a table of GX RX/TX latency values vs. the various GX PCS / PMA modes?

I am looking for something similar to this answer record from Xilinx:

http://www.xilinx.com/support/answers/64309.html

which gives clear / unambiguous latency tradeoffs vs functionality.

Thanks,
Terry

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Hardware for quartus

January 27, 2016, 7:55 am

≫ Next: Partial reconfiguration Time for a small block

≪ Previous: Arria 10 GX PHY latency number

Hello everyone,
I would like to ask question about hardware with I use for JTAG usb controller.because i use jetlink usb controller and quartus didnt find this hardaware/and thaths why i want ask you.I should use only altera usb blaster or i can use other different controllers ?

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Partial reconfiguration Time for a small block

January 27, 2016, 8:45 am

≫ Next: Low Latency PHY in Qsys

≪ Previous: Hardware for quartus

Does any one have a handle on how long it might take to partially reconfig a small
block in an ARRIA V FPGA.

I would like to reconfig some LVDS drivers out of a design. In one revision I would like
to have 10 LVDS drivers working, in a second revision, I would like to replace the
drivers with nothing, to reduce power.

I would like to be able to partially reconfig between the revisions.

From the little I understand of partial reconfiguration I would like to store the partial
reconfig file in on-chip memory and pull it out using the PR IP core. Nothing off chip

I am just looking for an idea of how long it might take to do this reconfigure. Is it 100's ms,
10's ms or in the microseconds.

Any thoughts would be warmly accepted

Best Regards

C

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Low Latency PHY in Qsys

January 27, 2016, 11:02 am

≫ Next: Verilog HDL error : cannot connect instance ports both by order and by name

≪ Previous: Partial reconfiguration Time for a small block

I want to bring the low latency PHY to a project in Qsys. HOwever it seems that none of the protocol-specific nor any of the native PHYs are available in the Qsys IP catalog.
What would be the best line of action in this case?

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Verilog HDL error : cannot connect instance ports both by order and by name

January 27, 2016, 5:35 pm

≫ Next: What is the register's initial value after FPGA power up?

≪ Previous: Low Latency PHY in Qsys

am doing the SLS SDHC_eMMC card host tutorial
enclosed in two jpegs are my code.

Attached Images

error1.jpg (392.4 KB)
error2.jpg (435.6 KB)

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What is the register's initial value after FPGA power up?

January 27, 2016, 7:03 pm

≫ Next: Program FPGA with multiple different kernels in parallel

≪ Previous: Verilog HDL error : cannot connect instance ports both by order and by name

hi:

For example, after CycloneIV device power up, what is the initial value of the internal registers?
I found a interesting thing: usually,we set the initial value for the registers like this: always@(posedge clk or negedge reset) reg <= 0; But when you trace the reset signal to the most original, it would be pure controlled by the FPGA hadrware itself instead of verilog statement.

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Program FPGA with multiple different kernels in parallel

January 27, 2016, 9:14 pm

≫ Next: Execute gate level simulation, the read empty signal of the FIFO is unknown

≪ Previous: What is the register's initial value after FPGA power up?

I'd like to be able to run multiple kernels with different operations at the same time using the CycloneV SoC (DE1-SoC). Can you guys check if my understanding is correct:

It's possible to compile multiple different kernels into the same aocx file
How are these kernels called from the host side? Do I just duplicate the relevant OpenCL API calls like clCreateProgramWithBinary, clBuildProgram, clCreateKernel, clEnqueueNDRangeKernel, etc. for each kernel?
For point #2 above (duplicating the API calls), does it program the FPGA once with all the kernels so they can be run at the same time? Or does the FPGA get programmed with the first kernel, run the first kernel, then reprogram with the second kernel, run the second kernel, and so on?
If I use `aocl flash` to load the aocx image into the FPGA, the FPGA will automatically be programmed with my kernels upon startup and I won't need to reprogram the FPGA with clCreateProgramWithBinary in my host program. Is that right?

Are there are any example projects where multiple different kernels are programmed together into the FPGA and executed at the same time? If so, I would appreciate a link to it.
Thanks!

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Execute gate level simulation, the read empty signal of the FIFO is unknown

January 27, 2016, 10:39 pm

≫ Next: Clear explaination about system interconnect fabric

≪ Previous: Program FPGA with multiple different kernels in parallel

simulation:Gate level simulation
Where,the ADbuffer rdempty signal is the rdempty pin of the FIFO ,I don't know why the signal turs to an unknown state after some time.

Attached Images

newscreen7577701.jpg (34.4 KB)

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Clear explaination about system interconnect fabric

January 27, 2016, 11:08 pm

≫ Next: How to do the timing constrain of the clolks of ALTCLKCTRL

≪ Previous: Execute gate level simulation, the read empty signal of the FIFO is unknown

Hi

I'm newbee in altera board and using DE1-SoC.

And I'm having confusion of system interconnect fabric.

As far as I know, FPGA and HPS are connected via 'bridge' (HPS to FPGA, FPGA to HPS, HPS to FPGA lightweight).

and also, according to the HPS's block diagram from 'Cyclone V Hard Processor System manual 1-4), bridges are connected to L3 interconnect(NIC-301).

And I found that NIC-301's role is sort of routers or switches.

Besides, Avalon MM peripherals are connected via 'system interconnect fabric'

So this is what causes confusion, if I make Avalon MM slaves such as PIO be connected to HPS, what is the relationship between 'system interconnect fabric' , 'bridges', and L3 interconnect??

According to the HPS's block diagram from 'Cyclone V Hard Processor System manual 1-4), I don't know where to add 'system interconnect fabric' in that block diagram.

thanks in advance

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How to do the timing constrain of the clolks of ALTCLKCTRL

January 27, 2016, 11:47 pm

≫ Next: What's the difference between area sequencer optimization and performance in qdr II

≪ Previous: Clear explaination about system interconnect fabric

I had instanced a ALTCLKCTRL IP core in my project .The ALTCLKCTRL IP core has two clocks input ports and one output ports, the one is 125MHz(inclk0),the other one is 48MHz(inclk1). So How can I do the timing constrain.

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