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Unable to program .pof into internal flash.

February 4, 2016, 5:52 am
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Hello,
I am not able to program MAX10 FPGA (device: 10M16SAU169C8G) using Quartus Prime Version 15.1.0 Build 185 10/21/2015 SJ Standard Edition. I am following all the steps provided in the MAX 10 FPGA Configuration User Guide to program .pof into internal flash. The following messages are displayed,

Info (209060): Started Programmer operation at Thu Feb 04 14:24:57 2016
Info (209017): Device 1 contains JTAG ID code 0x031830DD
Info (209060): Started Programmer operation at Thu Feb 04 14:24:59 2016
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x031830DD
Info (209007): Configuration succeeded -- 1 device(s) configured Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Thu Feb 04 14:25:02 2016
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Thu Feb 04 14:25:03 2016

I tried two options while programming : 1. To program CFM only. 2. To program CFM and UFM only. I have got the same error for both the options.

Any suggestions about how to get rid of this problem would be grateful.
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DSP vs altera airthmetic cores

February 4, 2016, 6:54 am
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Hi,

i am new to altera and i want to do basic floating point operations in my vhdl code. What is the difference between using Altera arithmetic cores (fp add_sub) and using native floating point point DSP? thet are both offered in IP catalog. I just want to perform add sub mult and sqrt in 32 bit inputs
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Buying pre-programmed MAX 10's

February 4, 2016, 5:41 pm
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Does anyone know of vendors or a process through Altera where it is possible to buy MAX 10 CPLD's already programmed? I have a customer with a a requirement to use the CPLD as a provisioning tool and we would like to program the chips before they are stuffed.

We are using the 8x8 153pin BGA which might limit the vendors with available programming sockets.

I've found a few vendors with appropriate sockets, but ideally, we would just like to buy them pre-programmed.

Thanks.
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Modelsim-Altera Error VHDL package file

February 4, 2016, 11:07 pm
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Hi ,

I am working on a VHDL project with many components , i have written a package file with all components declared in it and its been added as a library in my Top file .

The project compiles with no errors , but when i try to do modelsim-altera simulation i get error that this package file is not specified ???

do i have to specify complete path for modelsim in my library declaration ???

How to get rid of this error ?

I am using Quartus and Modelsim of version 13.0.

Regards ,
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Linux driver for Low Latency Ethernet 10G MAC

February 5, 2016, 12:44 am
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Hi everyone!

I want to know about linux driver for "Low Latency Ethernet 10G MAC".
https://www.altera.com/en_US/pdfs/li...hernet_mac.pdf

Is there any linux driver for Low Latency Ethernet 10G MAC?

I could be able find the TSE linux driver (Altera Triple-Speed Ethernet MAC driver) in kernel.org v3.15 source.
I would like to know whether this driver can use for Low Latency Ethernet 10G MAC?

I would really appreciate, If you let me know any information related to the linux driver of "Low Latency Ethernet 10G MAC".

Thanks,
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Quartus Instantiated megafunction and then synthesized away

February 5, 2016, 12:59 am
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Hi,
In my project i have instantiated more than one VHDL unit that realize a moving average filter. During Analysis and Synthesis i found that only for one i have the following info messages:

Info (19000): Inferred 1 megafunctions from design logic
Info (276034): Inferred altshift_taps megafunction from the following design logic: "IN_BLOCK:U4|FILTERS:U1|moving_avg:FILT|\ma_gen:re g_data[0][13]_rtl_0"
Info (12133): Instantiated megafunction "IN_BLOCK:U4|FILTERS:U1|moving_avg:FILT|altshift_t aps:\ma_gen:reg_data[0][13]_rtl_0" with the following parameter:
Info (12134): Parameter "NUMBER_OF_TAPS" = "1"
Info (12134): Parameter "TAP_DISTANCE" = "8"
Info (12134): Parameter "WIDTH" = "126"
Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE"

And then i receive this warning:

Warning (14285): Synthesized away the following RAM node(s):
Warning (14320): Synthesized away node "IN_BLOCK:U4|FILTERS:U1|moving_avg:FILT|altshift_t aps:\ma_gen:reg_data[0][13]_rtl_0|shift_taps_mev:auto_generated|altsyncram_1j c1:altsyncram4|ram_block7a84"

As a consequence all my logic that depends on the above unit is synthesized away.

I use Quartus 13.1

Thanks for your help
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ep2c5t144c8n fifo ram ?

February 5, 2016, 1:37 am
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1-are ep2c5t144c8n have fifo ram or internal sram (i want to buffer adc small data fifo) or i need external sram ?
2-are epm240t100c5n have fifo ram or internal sram (i want to buffer adc small data fifo) or i need external sram ?

what is internal sram size in both chip if it have
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Image Cropping on De2-115 using Verilog

February 5, 2016, 1:53 am
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Good Day. I'm currently doing signature verification on DE2-115 using Verilog. I need to compare two different images and I'm having trouble in cropping them. My system needs to crop both my test and genuine signatures which are both initially a 640x480 image. What i know is that i have to determine the rows and columns of the image that are non-zero.My problem now is how would i know the location of the non-zero rows and columns and the maximum value where i would crop it. Also the cropping itself, can I shift them to either right or left or is there another way?
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How to implement a System like this easily using Altera Tools of my DE1-SOC?

February 5, 2016, 2:05 am
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Hi,

I want to implement a system as follows: Four cores (Processing Elements) to read a black and white image of 240x240 pixels = 57.600 pixels in total (each pixel with a intensity integer value of 0 to 255).

Every core will take care of 14.400 of the pixels. Every core will read 1 pixel at a time, calculate an equation and update a register, then read the next pixel and do the same again until finishing its 14.400 pixels.

Finally, each of the four cores will sum their results with the results of the other 3, and perform a different equation, spitting out a value "V", this value "V" will be used as input along with the (static and constant) pixel value to do the whole process again, until reaching "V" which comply a condition (less than a predefined value).

I want to say, I have more or less an Idea for how to implement everything in Verilog (State Machines, ROM, task instantiation). However, I'd like to take advantage of the resources of my board DE1-SOC for this proyect, specially the software tools (Qsys?, Nios-II?).

For example, I would like to NOT relay on my code to read the Picture itself nor transform it in integers, so probably I will have to use ROM from the board, my intention is to use the board and altera tools as much as possible, for easiness and time economy. I could code the Cores and implemented into Nios-II maybe?

There is not speed or energy specifications, if Altera tools can make them automatically.

I'd like to know your advice and general guidance.

Thank you
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SPI with generated clock output constraint problem

February 5, 2016, 3:38 am
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  1. This interface is similar to SPI - runs with 10 MHz clock
  2. I got 20 MHz reference clock in my design REF_CLK Data to transfer is shifted on falling edge on every 2nd toggle of REF_CLK clock to output port D
  3. Output clock is generated by DFF {REF_CLK} [cant by generated by pll] and is transfered to output port C
  4. Ts /Th of extrernal device is 8 ns

in sdc i got:
  1. create_clock -name REF_CLK -period 50.000 [get_ports {REF_CLK}]
  2. create_generated_clock -name C -source [get_ports {REF_CLK}] -divide_by 2 [get_ports {C}]
  3. set_output_delay -clock C 8 [get_ports {D}]
  4. it doesnt work ;l
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ALTSHIFT_TABS automatically inserted into the design

February 5, 2016, 3:49 am
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I had the following in my design:
Code:
r_reg1[127:0] <= { r_reg1[126:0], inputpin };
Then I had to introduce a condition to select which register input data will be shifted into, I did it this way:

Code:
if(r_condition)
        r_reg1[127:0] <= { r_reg1[126:0], inputpin };
        else    r_reg2[127:0] <= { r_reg2[126:0], inputpin };
And my project stops compiling because Quartus tries to use another M9K block for Altshift_Tabs megafunction, and all the RAM blocks are already in use.
Why Quartus is doing it? Why it does not do what it was instructed to do - just use two registers and shift input data in respective one on the condition?
Please advise. Thank you.
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Accesing Character LCD

February 5, 2016, 6:06 am
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Hi,

I have Problems, Accesing a Character Display wit NIOSII.
I´m using the 16x2 Character Display IP from the University Programm.
I have wired R/W to ground, so that I only can perform Write operations to the Display.
Could this be a Problem?
Here is my my main Code:

Code:
#include <stdio.h>
#include <unistd.h>
#include "system.h"
#include "altera_avalon_pio_regs.h"
#include "altera_up_avalon_character_lcd.h"


int main()
{


    printf("working!\n");
    alt_8 count = 0;

    alt_up_character_lcd_dev * char_lcd_dev;
    // open the Character LCD port
    char_lcd_dev = alt_up_character_lcd_open_dev("/dev/lcd");
    if
    ( char_lcd_dev == NULL)
    {
    printf ("Error: could not open character LCD device\n");
    printf(char_lcd_dev);
    }
    else
    printf ("Opened character LCD device\n");

    /* Initialize the character display */
    alt_up_character_lcd_init (char_lcd_dev);
    /* Write "Welcome to" in the first row */
    alt_up_character_lcd_string(char_lcd_dev, "Welcome to");
    /* Write "the DE2 board" in the second row */
    char second_row[] = "the DE2 board\0";
    alt_up_character_lcd_set_cursor_pos(char_lcd_dev, 0, 1);
    alt_up_character_lcd_string(char_lcd_dev, second_row);

  /* Event loop never exits. */
  while (1)
  {

      IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE,count);
      usleep(100000);
  }

  return 0;
}
When I try it, char_lcd_dev is NULL.
I get This Message via JTAG-UART:
Code:
working!
Error: could not open character LCD device
4
In Qsys the lcd is named lcd, so i think "/dev/lcd" is correct.

You can see a screenshot of my Qsys Sytem as Attachment.
Or here in higher Resolution:
http://abload.de/image.php?img=displayqsysr5jmu.png

This is my system.h:
Code:
#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/* Include definitions from linker script generator */
#include "linker.h"


/*
 * CPU configuration
 *
 */

#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x00010820
#define ALT_CPU_CPU_ARCH_NIOS2_R1
#define ALT_CPU_CPU_FREQ 50000000u
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "tiny"
#define ALT_CPU_DATA_ADDR_WIDTH 0x11
#define ALT_CPU_DCACHE_LINE_SIZE 0
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_DCACHE_SIZE 0
#define ALT_CPU_EXCEPTION_ADDR 0x00008020
#define ALT_CPU_FLASH_ACCELERATOR_LINES 0
#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
#define ALT_CPU_FLUSHDA_SUPPORTED
#define ALT_CPU_FREQ 50000000
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 0
#define ALT_CPU_HARDWARE_MULX_PRESENT 0
#define ALT_CPU_HAS_DEBUG_CORE 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
#define ALT_CPU_HAS_JMPI_INSTRUCTION
#define ALT_CPU_ICACHE_LINE_SIZE 0
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_ICACHE_SIZE 0
#define ALT_CPU_INST_ADDR_WIDTH 0x11
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_OCI_VERSION 1
#define ALT_CPU_RESET_ADDR 0x00008000


/*
 * CPU configuration (with legacy prefix - don't use these anymore)
 *
 */

#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x00010820
#define NIOS2_CPU_ARCH_NIOS2_R1
#define NIOS2_CPU_FREQ 50000000u
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "tiny"
#define NIOS2_DATA_ADDR_WIDTH 0x11
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_EXCEPTION_ADDR 0x00008020
#define NIOS2_FLASH_ACCELERATOR_LINES 0
#define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0
#define NIOS2_FLUSHDA_SUPPORTED
#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
#define NIOS2_HARDWARE_MULTIPLY_PRESENT 0
#define NIOS2_HARDWARE_MULX_PRESENT 0
#define NIOS2_HAS_DEBUG_CORE 1
#define NIOS2_HAS_DEBUG_STUB
#define NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
#define NIOS2_HAS_JMPI_INSTRUCTION
#define NIOS2_ICACHE_LINE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE_LOG2 0
#define NIOS2_ICACHE_SIZE 0
#define NIOS2_INST_ADDR_WIDTH 0x11
#define NIOS2_OCI_VERSION 1
#define NIOS2_RESET_ADDR 0x00008000


/*
 * Define for each module class mastered by the CPU
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_TIMER
#define __ALTERA_NIOS2_GEN2
#define __ALTERA_UP_AVALON_CHARACTER_LCD


/*
 * System configuration
 *
 */

#define ALT_DEVICE_FAMILY "MAX 10"
#define ALT_ENHANCED_INTERRUPT_API_PRESENT
#define ALT_IRQ_BASE NULL
#define ALT_LOG_PORT "/dev/null"
#define ALT_LOG_PORT_BASE 0x0
#define ALT_LOG_PORT_DEV null
#define ALT_LOG_PORT_TYPE ""
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/null"
#define ALT_STDERR_BASE 0x0
#define ALT_STDERR_DEV null
#define ALT_STDERR_TYPE ""
#define ALT_STDIN "/dev/null"
#define ALT_STDIN_BASE 0x0
#define ALT_STDIN_DEV null
#define ALT_STDIN_TYPE ""
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_BASE 0x11030
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_SYSTEM_NAME "NIOS_sys"


/*
 * hal configuration
 *
 */

#define ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
#define ALT_MAX_FD 4
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK none


/*
 * jtag_uart configuration
 *
 */

#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart
#define JTAG_UART_BASE 0x11030
#define JTAG_UART_IRQ 0
#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_SPAN 8
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8


/*
 * lcd configuration
 *
 */

#define ALT_MODULE_CLASS_lcd altera_up_avalon_character_lcd
#define LCD_BASE 0x11038
#define LCD_IRQ -1
#define LCD_IRQ_INTERRUPT_CONTROLLER_ID -1
#define LCD_NAME "/dev/lcd"
#define LCD_SPAN 2
#define LCD_TYPE "altera_up_avalon_character_lcd"


/*
 * led_pio configuration
 *
 */

#define ALT_MODULE_CLASS_led_pio altera_avalon_pio
#define LED_PIO_BASE 0x11020
#define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define LED_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LED_PIO_CAPTURE 0
#define LED_PIO_DATA_WIDTH 5
#define LED_PIO_DO_TEST_BENCH_WIRING 0
#define LED_PIO_DRIVEN_SIM_VALUE 0
#define LED_PIO_EDGE_TYPE "NONE"
#define LED_PIO_FREQ 50000000
#define LED_PIO_HAS_IN 0
#define LED_PIO_HAS_OUT 1
#define LED_PIO_HAS_TRI 0
#define LED_PIO_IRQ -1
#define LED_PIO_IRQ_INTERRUPT_CONTROLLER_ID -1
#define LED_PIO_IRQ_TYPE "NONE"
#define LED_PIO_NAME "/dev/led_pio"
#define LED_PIO_RESET_VALUE 0
#define LED_PIO_SPAN 16
#define LED_PIO_TYPE "altera_avalon_pio"


/*
 * onchip_mem configuration
 *
 */

#define ALT_MODULE_CLASS_onchip_mem altera_avalon_onchip_memory2
#define ONCHIP_MEM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_MEM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_MEM_BASE 0x8000
#define ONCHIP_MEM_CONTENTS_INFO ""
#define ONCHIP_MEM_DUAL_PORT 0
#define ONCHIP_MEM_GUI_RAM_BLOCK_TYPE "AUTO"
#define ONCHIP_MEM_INIT_CONTENTS_FILE "NIOS_sys_onchip_mem"
#define ONCHIP_MEM_INIT_MEM_CONTENT 0
#define ONCHIP_MEM_INSTANCE_ID "NONE"
#define ONCHIP_MEM_IRQ -1
#define ONCHIP_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ONCHIP_MEM_NAME "/dev/onchip_mem"
#define ONCHIP_MEM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ONCHIP_MEM_RAM_BLOCK_TYPE "AUTO"
#define ONCHIP_MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define ONCHIP_MEM_SINGLE_CLOCK_OP 0
#define ONCHIP_MEM_SIZE_MULTIPLE 1
#define ONCHIP_MEM_SIZE_VALUE 20480
#define ONCHIP_MEM_SPAN 20480
#define ONCHIP_MEM_TYPE "altera_avalon_onchip_memory2"
#define ONCHIP_MEM_WRITABLE 1


/*
 * sys_clk_timer configuration
 *
 */

#define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer
#define SYS_CLK_TIMER_ALWAYS_RUN 0
#define SYS_CLK_TIMER_BASE 0x11000
#define SYS_CLK_TIMER_COUNTER_SIZE 32
#define SYS_CLK_TIMER_FIXED_PERIOD 0
#define SYS_CLK_TIMER_FREQ 50000000
#define SYS_CLK_TIMER_IRQ 1
#define SYS_CLK_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0
#define SYS_CLK_TIMER_LOAD_VALUE 49999
#define SYS_CLK_TIMER_MULT 0.001
#define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer"
#define SYS_CLK_TIMER_PERIOD 1
#define SYS_CLK_TIMER_PERIOD_UNITS "ms"
#define SYS_CLK_TIMER_RESET_OUTPUT 0
#define SYS_CLK_TIMER_SNAPSHOT 1
#define SYS_CLK_TIMER_SPAN 32
#define SYS_CLK_TIMER_TICKS_PER_SEC 1000
#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define SYS_CLK_TIMER_TYPE "altera_avalon_timer"

#endif /* __SYSTEM_H_ */

I think the IP Core is working and the Display is wired correct, because the Cursor of the Display is blinking.


Greets
Olaf
Attached Images
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Variable Precision DSP Block for Cyclone V, number clock cycles for 1 multiplicaition

February 5, 2016, 6:30 am
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I went through the DSP section of hand book for Cyclone V. I did not find any specification on how many clock cycles for the multiplier to finish one multiplication. If any one here in the Forum can help on that I'd really appreciate it. I am assuming one clock cycle per multiply.

Thanks,
FZ
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Error (10404) VHDL error occured when function call by.

February 5, 2016, 7:59 am
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I am in trouble in VHDL analyze & synthesis.

I use "Quartus Prime Verion 15.1.0 Build 185 10/21/2015 SJ Lite Edition".

It defines the function in the package. One of them there is no argument.

sample_code.vhd
Code:
library ieee;
use    ieee.std_logic_1164.all;
use    ieee.numeric_std.all;
package Sample_Code is
    subtype  Code_Type  is std_logic_vector(3 downto 0);
    type      Code_Vector is array (integer range <>) of Code_Type;
    function  New_Code(DATA:std_logic_vector) return Code_Type;
    function  New_Code(DATA:unsigned        ) return Code_Type;
    function  New_Code(DATA:integer        ) return Code_Type;
    function  New_Code                        return Code_Type;
end Sample_Code;

library ieee;
use    ieee.std_logic_1164.all;
use    ieee.numeric_std.all;
package body Sample_Code is
    function  New_Code(DATA:std_logic_vector) return Code_Type is begin
        return DATA(Code_Type'range);
    end function;
    function  New_Code(DATA:unsigned        ) return Code_Type is begin
        return New_Code(std_logic_vector(DATA));
    end function;
    function  New_Code(DATA:integer        ) return Code_Type is begin
        return New_Code(to_unsigned(DATA, 4));
    end function;
    function  New_Code                        return Code_Type is begin
        return New_Code(0);
    end function;
end Sample_Code;
I call no-argment function by <package_name>.<function_name>

sample_1_ng.vhd
Code:
library ieee;
use    ieee.std_logic_1164.all;
use    ieee.numeric_std.all;
use    work.Sample_Code;
entity  Sample is
    port (O: out Sample_Code.Code_Type);
end    Sample;
architecture RTL of Sample is
begin
    O <= Sample_Code.New_Code;
end RTL;
then error occured when Analyze & Synthesis

Quote:
Info: ************************************************** *****************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
Info: Processing started: Sat Feb 06 00:10:09 2016
Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
Info: Processing started: Sat Feb 06 00:10:09 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sample_altera -c sample_altera
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 2 design units, including 1 entities, in source file sample_1_ng.vhd
Info (12022): Found design unit 1: Sample-RTL
Info (12023): Found entity 1: Sample
Info (12022): Found design unit 1: Sample-RTL
Info (12023): Found entity 1: Sample
Info (12021): Found 2 design units, including 0 entities, in source file sample_code.vhd
Info (12022): Found design unit 1: Sample_Code
Info (12022): Found design unit 2: Sample_Code-body
Info (12022): Found design unit 1: Sample_Code
Info (12022): Found design unit 2: Sample_Code-body
Error (10404): VHDL error at sample_1_ng.vhd(10): can't determine object and type associated with indexed name or signature name near text "New_Code" -- found 4 possible objects and types
Info (10797): VHDL info at sample_code.vhd(7): first match for 'New_Code' found here
Info (10797): VHDL info at sample_code.vhd(8): another match for 'New_Code' found here
Info (10797): VHDL info at sample_code.vhd(9): another match for 'New_Code' found here
Info (10797): VHDL info at sample_code.vhd(10): another match for 'New_Code' found here
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 855 megabytes
Error: Processing ended: Sat Feb 06 00:10:34 2016
Error: Elapsed time: 00:00:25
Error: Total CPU time (on all processors): 00:01:01
Error: Peak virtual memory: 855 megabytes
Error: Processing ended: Sat Feb 06 00:10:34 2016
Error: Elapsed time: 00:00:25
Error: Total CPU time (on all processors): 00:01:01
but, I call no-argment function by <function_name> only, then no problem.

sample_1_ok.vhd
Code:
library ieee;
use    ieee.std_logic_1164.all;
use    ieee.numeric_std.all;
use    work.Sample_Code.all;
entity  Sample is
    port (O: out Code_Type);
end    Sample;
architecture RTL of Sample is
begin
    O <= New_Code;
end RTL;
why?

By the way, in Xilinx Vivado this problem does not occur.
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Looking for advice on using OpenCL FPGA for data acquisition

February 5, 2016, 11:01 am
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Greetings!

We are trying to implement an image acquisition hardware based on OpenCL FPGA and I'm wondering if anyone could provide some advice.


Specifically, we would like to write host and kernel code with Altera OpenCL SDK, and implement the following properties on the FPGA:
1) generic digital or analog IOs to communicate with shutter, sensors, cameras (onboard IOs or the HSMC card with a daughter board);
2) asynchronous FIFO channels for buffering incoming data and transferring data to host;
3) interruptions or control signals that allow the host and the kernel to communicate with each other about their status (data transfer completed, acquisition finished, FIFO full, etc.).

I read the Altera OpenCL manual but couldn't find details to address my concerns above. Googling the topic didn't help much either.
Will anyone recommend a development kit that meets our needs? Or, any comments & suggestions are greatly appreciated!

Thanks,
Bing
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bemicromax 10 - sdram CKE pinout needed or not ?

February 5, 2016, 11:06 am
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I have a tutorial for the cyclone III for the core commander board which i am trying to translate to the bemicromax 10 . In it .sdram_wire_cke is defined as

.sdram_wire_cke ( ),

so it is declared but not being used for some reason ?? in a more modern tutorial for the BEMICROMAX 10 i found that it is declared
.sdram_cke (SDRAM_CKE), // .cke

i am unable to boot the system into nios until i declare some more pinouts such as fpga_reset.i also need a regulator for the sd card which is shipping from arrow. the sd card is the main function of the program so i need to perfect everything before i will know if it is ready to boot or not
does anyone know is cke is needed or not ?

sorry for blowing up the board with all these error messages, i am doing my first beginner project and i do not want to have so many unknowns that it will not boot.
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Warning (10236): Verilog HDL Implicit Net warning at cc_r2a_refdes_sdhc_cntrl.v(40):

February 5, 2016, 12:55 pm
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before i begin let me explain that in the last post i made i had a problem deciding whether to assign a sdram pin known as SDRAM_CKE ... in the tutorial i am using in the top level entity file it is established but not assigned to a wire. for example

In the outdated tutorial .sdram_wire_cke is defined as

.sdram_wire_cke ( ),

so it is declared it using a more modern tutorial for the BEMICROMAX 10 i found that it is declared
.sdram_cke (SDRAM_CKE), // .cke

so this is programmed in and saved.... but when i try to start analysis and elaboration it goes all the way through but gives me an warning

Warning (10236): Verilog HDL Implicit Net warning at cc_r2a_refdes_sdhc_cntrl.v(40): created implicit net for "sdr_cke"


for the sdram_cke on this line and there is no sdram_cke in the pin planner... am i missing a step ?
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prebuilt U-Boot does not recognize some USB storage devices

February 5, 2016, 2:11 pm
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Hi All,


I still haven't figured out how to re-build u-boot such that works for USB storage devices (see post: "rebuilt u-boot does not recognize USB storage devices"). I reverted to using the pre-built U-Boot in order to get some work done.

The version (same as before) is:
U-Boot 2013.01.01 (Aug 08 2014 - 10:46:23)
arm-altera-eabi-gcc.exe (Sourcery CodeBench Lite 2013.11-67) 4.8.1
GNU ld (Sourcery CodeBench Lite 2013.11-67) 2.23.52.2013091

This version worked fine for the 3 or 4 different USB sticks I initially tested. Meaning that the USB storage device was found:
SOCFPGA_CYCLONE5 # usb start
(Re)start USB...
USB0: scanning bus 0 for devices... 1 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
SOCFPGA_CYCLONE5 #



But then as I was preparing a (new) USB stick (different make/model) for a colleague - I got a different result:
SOCFPGA_CYCLONE5 # usb start
(Re)start USB...
USB0: scanning bus 0 for devices... DW_USB: Transfer completion interrupt timeout
Timed out waiting for channel to disable
1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
SOCFPGA_CYCLONE5 #


I rounded up all the USB sticks I had access to and found roughly 60% worked, the other 40% produced this same message "DW_USB: Transfer completion interrupt timeout".

There doesn't seem to be a property of the USB stick that would indicate whether it's going to work or not. I have sticks from the same vendor - some work, others don't. Capacity doesn't make a difference - some 16GB sticks work, some don't just as much as 2GB sticks. I looked closely at the 'lsusb -v' output and Linux kernel dmesg output generated on insertion and see no one property that would indicate whether a stick would work or not.


Can somebody who understands the USB support in U-Boot tell me (1) how I can resolve the "DW_USB: Transfer completion..." error, or (2) at the very least tell me what property of a USB stick I can view to know whether it will work or not. I can post some of the lsusb output from failed/working USB sticks if that helps.


Thanks in advance,
--George Broz
Moog Industrial Group
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detailed device pinout drawings?

February 5, 2016, 3:15 pm
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Does Altera publish detailed device pinout drawings like the attached pdf, which was printed from the Pin Planner? Or is the Pin Planner the only place to get this? Seems like these drawings used to be in a document somewhere.
Attached Files
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MAX 10 project ---- fpga reset

February 5, 2016, 4:35 pm
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I have a tutorial for the SLS SD/emmc card open core
so far i have populated all the pins but one... it is called fpga_reset_n but also reffered to in the top level verilog file as being pll_reset,
what should i tie it to ? is is an input
does the fpga reset when it is pulled to a binary 1 or does it reset when it is dropped to a binary 0.
and if it is binary 0 can i connect it to VCC on the pin planner without any problems ? thanks !
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