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quartus || version9.0 and ACEX family related

February 6, 2016, 2:05 am
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hi,
i am a totally new guy in FPGA field.
i want to build a digital oscilloscope by FPGA board.I have pluto rev. F board which is in the family named ACEX.now my question is which quartus version will support the pluto rev. F FPGA board.Two months ago may be i had seen in altera website that quartus || version9.0 support the ACEX family but now i can't find any information about the ACEX family in altera website.so now i am confused.what to do now?
moreover i downloaded the quartus || version9.0 and tried to install it in windows 8 but i couldn't.Does quartus || version9.0 support in windows 8?
please give me a brief description about what should i do to work with pluto rev.F FPGA board?
thanks
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Use HPS DDR3 Memory from FPGA address question

February 6, 2016, 11:47 am
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Hi, i´m following this example to have ddr3 memory available to the Fabric on the DE0 nano soc.

I write to hps ddr3 with a write master and modular scatter gather DMA.

https://support.criticallink.com/red..._to_HPS_Memory

The first is to tell linux from uboot for reduce their memory usage for example from 1gb to 512mb its trivial.

But i don´t undersand how the HPS 2 FPGA SDRAM INTERFACE manages the addresses.For example if it adds some kind of offset.

If i write to the address (1 073 741 824 ) / 2 is my data being written just at the beginning of the second 512 mb ram 0X20000000 ?

I´m developing some drivers to output linux video to an adv7123 and adv 7511 hdmi and audio to a wm8731 and because the nano doesn´t have ddr on the fabric i will use this approach to use for the buffering stuff.
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FPGA to HPS Communication

February 6, 2016, 5:33 pm
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Hi Friends,
I have the Terasic DeE-0 Nano Development board with Cyclone V and ARM Cortex HPS. As a part of my project, I have send some huge amount of data ( in megabytes ) from FPGA to HPS and store it in the SDcard. So the idea is to develop a small program in the Linux which listens to some port (internal) from FPGA and writes the data to a text file as soon as it get a new data.
As I researched over the Internet , I came to know that I can use the AXI bus from FPGA to HPS and transfer as a burst data. The problem is I could not find a proper document , how to do it.
Does anyone have an idea how to do this ? Any help would be greatly appreciated.

Best Regards.
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10g mac - avalon_st_tx_ready de-asserted in the middle of the packet transfer

February 7, 2016, 2:33 am
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Hi All,

Does anybody know why avalon_st_tx_ready de-asserted in the middle of the packet transfer?
Attached a capture of signal tap.

I can see a missing data on the pc that receive this packet. the missing data is correlated with data transmitted while avalon_st_tx_ready de-asserted.

Thanks
Attached Images
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Programmer fail on first Program click

February 7, 2016, 5:22 am
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Quartus Programmer fail on first "Program" click with bemicro cv a9 board.
Anyone have same issue? If I click "Program" for the second time programming works..
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Clocked Video Output - Frame Locking - SOF

February 7, 2016, 9:09 am
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Hello together,

I've got a problem to get the clocked video output from the Altera VIP suite running into frame locking mode. I want to synchronzie the video output using the SOF input of the clocked video output component.

My system is as follows:
QSys: Test Pattern Generator -> Clocked Video Output <- external connection -> Clocked Video Input (cvi_a) -> Clocked Video Output (cvo_b) -> SDI II IP Core

cvi_a has SOF outputs for synchronization.
cvi_b has SOF inputs for synchronization.

Both components are connected for synchronization processes outside the QSys.

I set register of cvi_a at 0x00 to 0x0F for activating SOF outputs.
I set register of cvo_b at 0x00 to 0x1F for activation frame locking.

The system is working, in the case, that I see a 1080p30 SDI video at the SDI II IP Core output.

BUT, the system is not SOF locked.

The cvi_a didn't generate a SOF signal.
The cvo_b didn't lock as a result of the missing SOF input. And it doesn't generate SOF outputs itself.

-> Does anyone has an idea, why the system is not frame locking?
-> Doest anyone has experiance in frame locking for the clocked video output?
-> Is there a actual example design available for using frame rate locking?

Thank you all,

Best regards!
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QSYS vs SOPC -> EPCS boot code hex file different

February 7, 2016, 10:41 am
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Hello,

We are migrating our Cyclone III project from Quartus 11.1sp1 to Quartus 13.1, and of course 13.1 does not support editing our SOPC file. So, we converted SOPC to QSYS but noticed that the EPCS hex file generated was different in the QSYS generation vs the SOPC generation. We use REMOTE UPDATE, so we had the boot file source code which we modified for the two different apps that run in our product.

I assume that the EPCS boot code source file has changed, either for QSYS, or for Quartus 13.1 - is this a correct assumption?

Is it possible to use the SOPC EPCS hex file - will it still run? I'm not sure why it wouldn't as it is the same NIOS IP.

Lastly, if we must use the new EPCS hex file, can someone tell me where the EPCS boot code source files are located?

Thank you in advance.
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BEMICROCVA9 Board definition File for MATLAB

February 7, 2016, 4:52 pm
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I am new to Altera but have some experience with Xilinx. I just ordered a BEMICROCVA9 dev board last week. I am trying to use the matlab toolbox HDL Coder since I have alot of experience with Matlab. When I get into the Workflow HDL advisor in Matlab, I don't have the option to select the altera board I am working with. I have installed the available support packages for Altera within Matlab. According to the BEMICRO documentation, I am looking for a 5CEFA9F23C8N which doesn't seem to be available in the list of available FPGA boards.

I have two other options: "Create custom board" or "Add board from file". When I attempt to "create custom board" I don't see the board I have. The only other option left is to "Add board from file". When I look at the Matlab documentation, its looking for a board defintion file (xml). I haven't been able to find this file. Does anyone have experience with Matlab's HDL Coder or able to provide the board definition file? Thanks in advance!

dave
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Altera Cyclone V PCIe Development Board Write Memory to Root Complex

February 8, 2016, 12:58 am
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Hello Altera-Forum,

This post is about processing receiving unrequested data from an Altera Cyclone V development board IP core. The root complex is an Intel Haswell-CPU/SOC. The development board is plugged in the PCIe x16 slot.
The PCIe specification is allowing that the development board may act as a master in the bus and send a write request TLP (Transaction Layer Packet).

Is there a code example existing for Linux to do this? Where will be the data written to, when the TLP has address 0x0 defined?
The used OS is allowing to allocate DMA memory map. Where in the allocated may appear the incoming data?
Should I ask all this in the Intel developer forums?

with my regards

Apple Cake
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Having problems test benching with Model Sim from Quartus, any ideas?

February 8, 2016, 4:16 am
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// This is the test bench

`timescale 1 ps/ 1 ps

module sum_fix (valor_a,valor_b,result_fx,select);
input [7:-8] valor_a,valor_b;
output reg [8:-8] result_fx;
input select;


always@ (valor_a or valor_b)
begin
if (select==1)
result_fx = valor_a + valor_b;
else
result_fx = valor_a - valor_b;
end
endmodule


//This is the UUT

`timescale 1 ps/ 1 ps
module sum_fix_vlg_tst();
reg select;
reg [7:-8] valor_a;
reg [7:-8] valor_b;

// wires
wire [8:-8] result_fx;

sum_fix i1 (

.result_fx(result_fx),
.select(select),
.valor_a(valor_a),
.valor_b(valor_b)
);

initial
$monitor ("valor_a = %b, valor_b = %b, result_fx = %b", valor_a, valor_b, result_fx);

initial
begin
#10
select = 1;
valor_a = 32'b0000000011111111;
valor_b = 32'b0000000011111111;

#20

valor_a = 32'b1111111111111111;
valor_b = 32'b1111111111111111;

#30

valor_a = 32'b1001100111001000;
valor_b = 32'b0001111000111101;

end
endmodule




Compiled in Quartus well. Then I launch Modelsim like this: Tools > RTL simulation. It launch Modelsim but it only gives me a lot of zzzzzzzzzzzzz in input and xxxxxxxxxxxxxx in output without anything in the wave.
I want to say that I'm not sure if I added this testbench correctly to the project. I'm a beginer. What I did was: Assignments > Settings > Compile Test: click Test Benches > new, looked for the file and add, and ok. I'm not sure that this is the correct way, because it looks too complex. Please help on this.
Also, I comment that I initiate the test bench writter template in quartus, but I ended changing everything from the file, final result is the code above.
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GMII to RGMII converter

February 8, 2016, 5:07 am
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Hi,

Are there any reference designs available to convert GMII interface to RGMII interface?

The main intent on posting this question is that I have a system with an EMAC IP (Third party-Flexibilis) which is configured to GMII interface. Now, that due to obselesence, PHY IC needs to be changed which is compliant with RGMII interface. Hence I need a converter to convert GMII to RGMII interface.
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Creating a CvP jic file with a script

February 8, 2016, 5:19 am
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Hi everyone,

I'm trying to create a CvP jic file using a script instead of using the "Convert Programming File" Wizard. In the wizard there is an explicit option for CvP but I cannot find it in the quartus_cpf options. Has anyone been able to do it?

Regards
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missing a "Permissions" manifest attribute??

February 8, 2016, 7:05 am
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3038287 Jan 28, 2016 7:13 PMI have been working through the steps of creating a .jar file and signing it and adding it to my embedded web server project.

This is a pretty mature product but we’ve never used signed files and as you may know running unsigned applets is getting harder and harder to do, it’s driving our customers crazy so we really need to learn how to sign the applets and revise the code.
I’ve combined three .class files into a .jar file. I’ve used jarsigner and the code signing certificate from Comodo to sign it.

Since this is an embedded webserver I then take the signed jar files and all my .htm and .xml and .png files and run them through a perl script that creates a big .h of constant strings file that I can compile into my code.

So, the error I get when I try to run the applet on my web server is “Your security settings have blocked an application from running due to missing a “Permissions” manifest attribute in the main jar.” I know that there may be a MANIFEST.MF files … somewhere, I’m not using one now. Is there some attribute missing when I create the .jar file? The command I use to create it is:

jar cvf0 myjar.jar applet1.class applet2.class applet3.class


Any help would be appreciated.

Mike
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Where can I see the Netlist?

February 8, 2016, 7:13 am
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Hi All,

As for the Quartus-II, where can I see the Netlist? How can I browse it?

Thank you!
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Avalon On chip Fifo

February 8, 2016, 7:59 am
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Hi all,
i'm having trouble with avalon Fifo core (dual clock mode).
I have a simple FSM that grabs data from a fifo(1) and then transmit the response to another fifo(2) but nothing is written as read level is 0.
But, if i write 3 times the same data in fifo(1) i get one response in fifo(2).
well i think i missed something there...

notes : interrupts are disabled, Almost empty = 1



Code:
init_fifos_in();    init_fifos_out();


 

    init_fifos_in();
    init_fifos_out();


    altera_avalon_fifo_write_fifo(FIFO_PC_TO_DIF_IN_BASE, FIFO_PC_TO_DIF_IN_CSR_BASE, 0x00004005);
    altera_avalon_fifo_write_fifo(FIFO_PC_TO_DIF_IN_BASE, FIFO_PC_TO_DIF_IN_CSR_BASE, 0x00004005);
    altera_avalon_fifo_write_fifo(FIFO_PC_TO_DIF_IN_BASE, FIFO_PC_TO_DIF_IN_CSR_BASE, 0x00004005);
    printf("pio read = x%x\n", IORD_ALTERA_AVALON_PIO_DATA(PIO_0_BASE));


    if(altera_avalon_fifo_read_level(FIFO_DIF_TO_PC_OUT_CSR_BASE)>0)
    {
          printf("altera_avalon_fifo_read_level(FIFO_DIF_TO_PC_OUT_CSR_BASE) = %d\n",altera_avalon_fifo_read_level(FIFO_DIF_TO_PC_OUT_CSR_BASE));
        while(altera_avalon_fifo_read_level(FIFO_DIF_TO_PC_OUT_CSR_BASE)!=0)
        {
            printf("fifo read = x%x\n", IORD_ALTERA_AVALON_FIFO_DATA(FIFO_DIF_TO_PC_OUT_BASE));
        }
    }
    }

Code:

status initializing fifo = 0
pio read = x4005
altera_avalon_fifo_read_level(FIFO_DIF_TO_PC_OUT_CSR_BASE) = 1
fifo read = x30c30c30
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Stratix V MLAB Byte Enable Issue

February 8, 2016, 8:20 am
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Hi,

I am trying to implement a very small memory as a data buffer attached to an Avalon-MM interface.

As the memory is only 16bytes, and I require that the output be unregistered, I am using MLABs to implement this ram using the following altdpram instantiation:

Code:

    altdpram #(
        .byte_size                        (8),
        .indata_aclr                      ("OFF"),
        .indata_reg                        ("INCLOCK"),
        .intended_device_family            ("Stratix V"),
        .lpm_type                          ("altdpram"),
        .outdata_aclr                      ("OFF"),
        .outdata_reg                      ("UNREGISTERED"),
        .ram_block_type                    ("MLAB"),
        .rdaddress_aclr                    ("OFF"),
        .rdaddress_reg                    ("UNREGISTERED"),
        .rdcontrol_aclr                    ("OFF"),
        .rdcontrol_reg                    ("UNREGISTERED"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .width                            (32),
        .widthad                          (2),
        .width_byteena                    (4),
        .wraddress_aclr                    ("OFF"),
        .wraddress_reg                    ("INCLOCK"),
        .wrcontrol_aclr                    ("OFF"),
        .wrcontrol_reg                    ("INCLOCK")
    ) transferMemRead (
        //Write port (from I2C)
        .inclock                          (clock),
        .inclocken                        (busy),
        .wraddress                        (src_address),
        .byteena                          (src_byteen),
        .wren                              (src_write),
        .data                              ({(4){src_data}}), //copy src data to all byte locations
        //Read port (to AvMM)
        .rdaddress                        (csr_address[1:0]),
        .q                                (csr_data),
         
        .aclr                              (1'b0)
    );
Basically when the busy flag is high, the MLAB contents will be written with data from an I2C read transfer. This transfer is done byte-wise whereas Nios works with 32bit words. As such I am using byte enables to select which byte is written - the byte enable is generated by a one-hot counter which I can see from signaltap is correctly producing the required sequence (4'd1,4'd2,4'd4,4'd8,4'd1,...).

The byte enable is doing its job in that the incoming data byte is not written to all bytes, however, the contents of the non-enabled bytes is being cleared. To explain, I end up with the following sequence:

Code:
Byte En | Data In | Mem Contents
  0001  |  0x45  |  0xFFFFFF45
  0010  |  0x22  |  0xFFFF22FF  <- Should be 0xFFFF2245
  0100  |  0x55  |  0xFF55FFFF  <- Should be 0xFF552245
  1000  |  0xAA  |  0xAAFFFFFF  <- Should be 0xAA552245
Notice how the contents of the memory gets wiped - non-enabled bytes are getting replaced by 0xFF.

I have a second memory going the other direction (from Nios to the I2C controller) which if I do byte-wise writes from Nios (using IOWR_8DIRECT), the same thing happens. If however from Nios I do a 32bit write (IOWR_32DIRECT), then the word is written correctly.


So is there a reason for this? Is there something that I am missing about the byte enables that are causing this weird behavior?
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Using Altera PCI AV-MM DMA IP with custom MSI interrupts

February 8, 2016, 9:53 am
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I am researching the necessary elements to create a new design to transfer data from a FPGA based device to a host computer using PCI-e interface. So long, i have looked into the PCI-e Avalon-MM DMA reference design and made it work in the target platform using the Cyclone V GT development kit and the performance is indeed good.

However, for my application it might be good to have custom MSI interrupts so i can notify a variety of states to the host computer, and here lies the problem. The Avalon-MM DMA IP uses the MSI interrupts to signal the host computer the DMA transfer has completed, but, as far as i have been able to deduce from the documentation, it does not expose the interface to generate custom MSI interrupts besides the "DMA transfer done". Can anyone with experience with this IP module that my interpretation of the documents is accurate ? Is there anyway to generate custom MSI/MSI-X interrupts?


I have noticed the Legacy Interrupt generator is available and i might try to launch interrupts through this interface. Does anyone if this works properly ?
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MAX10 remote configuration with MCU

February 8, 2016, 10:24 am
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Design objective is to allow remote configuration update over ethernet with MCU. Is there a reference design or recommended method for this type of configuration?
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A lot of questions about how to initialize the codec in de2 board

February 8, 2016, 3:21 pm
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Hi everyone,

I want to configure the CODEC for now. I do a lot of research on Google and I think the way to initialize the CODEC is use the ip core "audio and video config"? I also read the datasheet of the CODEC, the demonstration from the de2 CD. But I am not sure how to use the Qsys to configure the core...also, Can I configure the CODEC with out NIOS ii?

I may ask a lot of questions because I am not familiar with Qsys...

Q1: The frequency of clock input in "a&v config" is depends on what?
Q2: To configure the CODEC, what IP I will need to use?

--
For now, I just want to confirm I can configure the CODEC, so I want to connect the MICIN and LINEOUT directly.
--

Many Thanks
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DE1 SoC Troubleshoot

February 8, 2016, 9:19 pm
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Hello, I am a second year Electrical engineering student. For my microcomputers class I have purchased a DE1 Soc from Terasic.

One normal evening I was happily coding away Verilog for one of the labs, had my DE1 plugged in to my pc via USB. Suddenly I heard that beeping sound that Windows makes when a usb device is plugged in, except the sound beeped like 5 times in a very short period.

I checked my board, restarted it and now the default program that cycles through numbers on HEX displays doesn't work anymore. Some HEX displays don't even light up and the board gets VERY hot in a very short period of time. I tried uploading some basic Verilog programs on it just to test if it works or not, it doesn't.

One of the TAs in my class suggested that flash memory is corrupted. I have searched the web but haven't found anything on how to go about fixing it, or of it's even fixable. Would appreciate any input.

Instead of executing the default program, hex display is just stuck on displaying of what's supposed to be all HEX's lighted up, except some of them aren't even working anymore. I have attached a photo. Also here is a link to the same photo: http://i.imgur.com/EEiL4kT.jpg?1

Thank you
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