Hello all, there is a way to know what entity quartus is compiling during analysis and synthesis?
My compilation is running from 13 hours..
My compilation is running from 13 hours..
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Quartus Compilation Profiling
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altera monitor problem load
hi, when I try to load the program into hps via altera monitor, it gives me this error:
/usr/bin/bash: up_hps: command not found
why?
how can I fix it?
/usr/bin/bash: up_hps: command not found
why?
how can I fix it?
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↧
Compilation step gets very slow with shift register (multiple unrolled shifts)
I just ran into this behaviour when trying to compile an unrolled loop over a shift register.
The code needs an incredible amount of time to get past the compilation step (Altera Offline Compiler on Windows).
-->The compilation step right before the logic - estimation output.
Issuing Code:
'left' and 'right' are also shift registers, the problem was the same with using 'linSums' as a 1-Dimensional shift register.
With NUM_DISPARITIES = 2 the Code needs little more than expected.
At NUM_DISPARITIES = 16 the compilation step needed over 20 mins.
Maybe this isnt a bug, but bad code or misunderstand use of shift registers ^^
However I would appreciate any help!
Regards
Steffen
The code needs an incredible amount of time to get past the compilation step (Altera Offline Compiler on Windows).
-->The compilation step right before the logic - estimation output.
Issuing Code:
Code:
#pragma unroll
for(int i = 0; i < NUM_DISPARITIES; ++i)
{
ushort sum = 0;
#pragma unroll
for(int wx = 0; wx < BM_WINDOW; ++wx)
{
sum += abs((left[wx]) - (right[wx + i]));
}
//shift register
#pragma unroll
for (int s = (BM_WINDOW * IMAGE_WIDTH - 1); s > 0; --s)
{
linSums[i][s] = linSums[i][s - 1];
}
linSums[i][0] = sum;
}With NUM_DISPARITIES = 2 the Code needs little more than expected.
At NUM_DISPARITIES = 16 the compilation step needed over 20 mins.
Maybe this isnt a bug, but bad code or misunderstand use of shift registers ^^
However I would appreciate any help!
Regards
Steffen
↧
UART alternate data missing
Hello !!!
I have been trying to send data through UART with the baud rate of 9600bps. I have coded a state machine in my verilog code, the problem am facing is that, I am able to receive the alternate data through UART. I have attached my code and the output in this thread. I'll be very thankful if anyone get me out of this problem
I have been trying to send data through UART with the baud rate of 9600bps. I have coded a state machine in my verilog code, the problem am facing is that, I am able to receive the alternate data through UART. I have attached my code and the output in this thread. I'll be very thankful if anyone get me out of this problem
↧
gate level simulation error
Hi all,
i have a problem in gate level simulation.
actually i have two kits
1- cyclone IV gx EP4CGX150DF31C7 kit
2- SDALTEVK (ti) sdi kit.
both kits can be connected through HSMC, during pin planning, i configure sdaltevk hsmc connection to cyclone iV hsma.
after that i got some error which is as.
Error (169079): Pad 325 of non-differential I/O pin 'genlock_no_ref' in pin location D29 is too close to pad 321 of differential I/O pin 'tx_d_p[1]' in pin location K26 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 325 of non-differential I/O pin 'genlock_no_ref' in pin location D29 is too close to pad 322 of differential I/O pin 'tx_d_n[2]' in pin location J26 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 325 of non-differential I/O pin 'genlock_no_ref' in pin location D29 is too close to pad 323 of differential I/O pin 'tx_d_p[2]' in pin location K25 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 325 of non-differential I/O pin 'genlock_no_ref' in pin location D29 is too close to pad 320 of differential I/O pin 'tx_d_n[1]' in pin location K27 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 324 of non-differential I/O pin 'genlock_no_lock' in pin location D30 is too close to pad 320 of differential I/O pin 'tx_d_n[1]' in pin location K27 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 324 of non-differential I/O pin 'genlock_no_lock' in pin location D30 is too close to pad 321 of differential I/O pin 'tx_d_p[1]' in pin location K26 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 324 of non-differential I/O pin 'genlock_no_lock' in pin location D30 is too close to pad 322 of differential I/O pin 'tx_d_n[2]' in pin location J26 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 324 of non-differential I/O pin 'genlock_no_lock' in pin location D30 is too close to pad 323 of differential I/O pin 'tx_d_p[2]' in pin location K25 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 329 of non-differential I/O pin 'sdi_ck_sel0' in pin location C29 is too close to pad 331 of differential I/O pin 'tx_d_n[3]' in pin location H25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 329 of non-differential I/O pin 'sdi_ck_sel0' in pin location C29 is too close to pad 332 of differential I/O pin 'tx_d_p[3]' in pin location J25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 328 of non-differential I/O pin 'sdi_ck_sel1' in pin location C30 is too close to pad 331 of differential I/O pin 'tx_d_n[3]' in pin location H25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 328 of non-differential I/O pin 'sdi_ck_sel1' in pin location C30 is too close to pad 332 of differential I/O pin 'tx_d_p[3]' in pin location J25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 328 of non-differential I/O pin 'sdi_ck_sel1' in pin location C30 is too close to pad 323 of differential I/O pin 'tx_d_p[2]' in pin location K25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.
Error (168002): Live I/O check failed
check attached schematic for both kits and then give me solution what can i do fir this ??
i have a problem in gate level simulation.
actually i have two kits
1- cyclone IV gx EP4CGX150DF31C7 kit
2- SDALTEVK (ti) sdi kit.
both kits can be connected through HSMC, during pin planning, i configure sdaltevk hsmc connection to cyclone iV hsma.
after that i got some error which is as.
Error (169079): Pad 325 of non-differential I/O pin 'genlock_no_ref' in pin location D29 is too close to pad 321 of differential I/O pin 'tx_d_p[1]' in pin location K26 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 325 of non-differential I/O pin 'genlock_no_ref' in pin location D29 is too close to pad 322 of differential I/O pin 'tx_d_n[2]' in pin location J26 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 325 of non-differential I/O pin 'genlock_no_ref' in pin location D29 is too close to pad 323 of differential I/O pin 'tx_d_p[2]' in pin location K25 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 325 of non-differential I/O pin 'genlock_no_ref' in pin location D29 is too close to pad 320 of differential I/O pin 'tx_d_n[1]' in pin location K27 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 324 of non-differential I/O pin 'genlock_no_lock' in pin location D30 is too close to pad 320 of differential I/O pin 'tx_d_n[1]' in pin location K27 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 324 of non-differential I/O pin 'genlock_no_lock' in pin location D30 is too close to pad 321 of differential I/O pin 'tx_d_p[1]' in pin location K26 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 324 of non-differential I/O pin 'genlock_no_lock' in pin location D30 is too close to pad 322 of differential I/O pin 'tx_d_n[2]' in pin location J26 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 324 of non-differential I/O pin 'genlock_no_lock' in pin location D30 is too close to pad 323 of differential I/O pin 'tx_d_p[2]' in pin location K25 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 329 of non-differential I/O pin 'sdi_ck_sel0' in pin location C29 is too close to pad 331 of differential I/O pin 'tx_d_n[3]' in pin location H25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 329 of non-differential I/O pin 'sdi_ck_sel0' in pin location C29 is too close to pad 332 of differential I/O pin 'tx_d_p[3]' in pin location J25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 328 of non-differential I/O pin 'sdi_ck_sel1' in pin location C30 is too close to pad 331 of differential I/O pin 'tx_d_n[3]' in pin location H25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 328 of non-differential I/O pin 'sdi_ck_sel1' in pin location C30 is too close to pad 332 of differential I/O pin 'tx_d_p[3]' in pin location J25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.
Error (169079): Pad 328 of non-differential I/O pin 'sdi_ck_sel1' in pin location C30 is too close to pad 323 of differential I/O pin 'tx_d_p[2]' in pin location K25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.
Error (168002): Live I/O check failed
check attached schematic for both kits and then give me solution what can i do fir this ??
↧
↧
Searching example code or manual entry regarding ACP mapping for EMAC DMA access
Hello,
we are using a Cyclone V SOC and its integrated EMAC for a high bandwidth application.
The EMAC should now
We thought, this should be possible using a well-tailored ACP window so the EMAC can differentiate between the two DDR3 locations.
For now, we have only found the register description
https://www.altera.com/content/dam/a...e-v/cv_5v4.pdf (starting at page 600).and would be happy to find a more step-by-step description ... ACP for Dummies ... more or less.
=> Is there an easy way to get a system running without too much headaches?
.... I'm doing direct register writes quite often (coming from the FPGA-side) - I would just like to exploit any possibilities for a more high-level-approach ;-)
Best regards,
Roman
PS: I didn't find a subforum where the question might have fitted any better but please move me away if you like to
we are using a Cyclone V SOC and its integrated EMAC for a high bandwidth application.
- All communication to the device are based on gigabit ethernet.
- The mass-data are processed mostly by FPGA hardware
- The control channel is done by SW
The EMAC should now
- Send mass-data from one part of the DDR3 without usage of the L2 cache
- ... so the bandwidth of the cache isn't affected by this
- Send SW generated control packets from the other part of the DDR3 with the usage of the L2 cache
- ... so our IP-Stack can stay unaware about caching effects etc.
We thought, this should be possible using a well-tailored ACP window so the EMAC can differentiate between the two DDR3 locations.
For now, we have only found the register description
https://www.altera.com/content/dam/a...e-v/cv_5v4.pdf (starting at page 600).and would be happy to find a more step-by-step description ... ACP for Dummies ... more or less.
=> Is there an easy way to get a system running without too much headaches?
.... I'm doing direct register writes quite often (coming from the FPGA-side) - I would just like to exploit any possibilities for a more high-level-approach ;-)
Best regards,
Roman
PS: I didn't find a subforum where the question might have fitted any better but please move me away if you like to
↧
Quartus II Programmer : Unable to detect hardware
Hello,
I am using Quartus II 15.0 (64 bits) and I have been using the DE0-nano board for a while, without any trouble.
I have stopped using the board for a few months until today. But today, Quartus II programmer doesn't detect any hardware anymore.
I had to install Quartus II 11.0 (32 and 64 bits) to make changes to an old project, so I have now 2 distincts versions installed. A few extra info:
I have no clue about where to start to investigate. Does anyone have experienced such case?
Thank you for your time,
Damien
I am using Quartus II 15.0 (64 bits) and I have been using the DE0-nano board for a while, without any trouble.
I have stopped using the board for a few months until today. But today, Quartus II programmer doesn't detect any hardware anymore.
- I tried 4 different boards;
- It is working perfectly on a co-worker's computer.
I had to install Quartus II 11.0 (32 and 64 bits) to make changes to an old project, so I have now 2 distincts versions installed. A few extra info:
- I have a valid Quartus II license;
- I attached an image displaying a crazy 770Go for Quartus 11.0 program.
I have no clue about where to start to investigate. Does anyone have experienced such case?
Thank you for your time,
Damien
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[TimeQuest] -> How to generate the Timing Summary Report?
Hi Al
How can I generate the Timing Summary Report in the TimeQuest (see the image below)?
![]()
Thank you!
How can I generate the Timing Summary Report in the TimeQuest (see the image below)?
Thank you!
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HPC Native to HPC II Avalon adaptors
Hi everybody, I have a HPC native interface at my DDR Controller. Now i would like to use a HPCII Avalon interface Controller.
Are there any reference designs available to convert native to Avalon MM interface?
Are there any reference designs available to convert native to Avalon MM interface?
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↧
For better simulation performance what mode of ALTPLL is recommended?
Hello,
I am working on a FPGA as functional verification engineer. We are using ALTPLL in our simulation and it is currently using more than 60% of simulator resources (altera_mf.v). Do you generally black box ALTPLL during functional verification? or Do you put it in bypass mode? Or you use it in active mode? This is the user's guide of PLL that we are using.
https://www.altera.com/content/dam/a.../ug_altpll.pdf
I am planning to blackbox PLL for functional simulation. I thought I'd check with you first and see what is the common approach in FPGA simulation regarding PLL.
a) Do folks generally run simulation with PLL model?
b) Do they generally put PLL in bypass mode? And in some occasion like weekend runs, use active pll model?
c) Do they blackbox PLL model?
d) Is there any value to run all the simulation with active PLL model and spending so much of simulation cycle?
any advice is highly appreciated.
Regards,
amir
I am working on a FPGA as functional verification engineer. We are using ALTPLL in our simulation and it is currently using more than 60% of simulator resources (altera_mf.v). Do you generally black box ALTPLL during functional verification? or Do you put it in bypass mode? Or you use it in active mode? This is the user's guide of PLL that we are using.
https://www.altera.com/content/dam/a.../ug_altpll.pdf
I am planning to blackbox PLL for functional simulation. I thought I'd check with you first and see what is the common approach in FPGA simulation regarding PLL.
a) Do folks generally run simulation with PLL model?
b) Do they generally put PLL in bypass mode? And in some occasion like weekend runs, use active pll model?
c) Do they blackbox PLL model?
d) Is there any value to run all the simulation with active PLL model and spending so much of simulation cycle?
any advice is highly appreciated.
Regards,
amir
↧
Eclipse not finding include files.
I have the University Program set up on my Windows 8 machine, working on the DE0 board. I am able to open the basic computer in Quartus and download it to the board, but once I try to build software for it, it won't compile.
The system seems unable to find the include files. I found the files there in the BSP support, but I have not been able to find where in the eclipse environment I should set the include directories.
Any advise?
The system seems unable to find the include files. I found the files there in the BSP support, but I have not been able to find where in the eclipse environment I should set the include directories.
Any advise?
↧
Design Space Explorer II crashing on Ubuntu 15.10
Design Space Explorer II in Quartus 15.1.1 on Ubuntu 15.10 keeps crashing with following message:
➜ bin ./quartus_dsew
Inconsistency detected by ld.so: dl-close.c: 764: _dl_close: Assertion `map->l_init_called' failed!
quartus_dsew: relocation error: /usr/lib/x86_64-linux-gnu/libssl.so: symbol EVP_aes_128_cbc_hmac_sha256, version OPENSSL_1.0.2 not defined in file libcrypto.so.1.0.0 with link time reference
The libssl.so apparently does contain the EVP_aes_128_cbc_hmac_sha256 function:
➜ bin readelf -s /usr/lib/x86_64-linux-gnu/libssl.so | grep EVP_aes_128_cbc_hmac_sha
37: 0000000000000000 0 FUNC GLOBAL DEFAULT UND EVP_aes_128_cbc_hmac_sha2@OPENSSL_1.0.2 (7)
72: 0000000000000000 0 FUNC GLOBAL DEFAULT UND EVP_aes_128_cbc_hmac_sha1@OPENSSL_1.0.1 (9)
It crashes a couple of seconds after opening a project. I am using Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition.
Has anybody else seen this behavior? I am not sure but I think I have managed to run DSE successfully a couple a months ago, maybe the recent updates to OpenSSL library changed something.
Quote:
➜ bin ./quartus_dsew
Inconsistency detected by ld.so: dl-close.c: 764: _dl_close: Assertion `map->l_init_called' failed!
quartus_dsew: relocation error: /usr/lib/x86_64-linux-gnu/libssl.so: symbol EVP_aes_128_cbc_hmac_sha256, version OPENSSL_1.0.2 not defined in file libcrypto.so.1.0.0 with link time reference
Quote:
➜ bin readelf -s /usr/lib/x86_64-linux-gnu/libssl.so | grep EVP_aes_128_cbc_hmac_sha
37: 0000000000000000 0 FUNC GLOBAL DEFAULT UND EVP_aes_128_cbc_hmac_sha2@OPENSSL_1.0.2 (7)
72: 0000000000000000 0 FUNC GLOBAL DEFAULT UND EVP_aes_128_cbc_hmac_sha1@OPENSSL_1.0.1 (9)
It crashes a couple of seconds after opening a project. I am using Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition.
Has anybody else seen this behavior? I am not sure but I think I have managed to run DSE successfully a couple a months ago, maybe the recent updates to OpenSSL library changed something.
↧
Need help with a VIP design like the C5G example
Hi Guys,
I put together simple LPDDR2+vip_vfr+vip_cpr+vip_itc system based on the C5G
example for the StarterKit board. To keep the system simple I removed a number
of IPs. Instead of the NIOS I use an external Avalon bus master. I have done that
before successfully. I have a number of questions regarding the video side:
- The C5G uses an additional PLL and all vip IPs run at 120Mhz from this PLL, The LPDDR runs on the 125Mhz
- What is the min freq. that I have to run the vip IPs at? is 50Mhz OK?
- Which IPs have to run on the same clock?
- I have to run the itc at 44.8Mhz
Thanks,
S.
I put together simple LPDDR2+vip_vfr+vip_cpr+vip_itc system based on the C5G
example for the StarterKit board. To keep the system simple I removed a number
of IPs. Instead of the NIOS I use an external Avalon bus master. I have done that
before successfully. I have a number of questions regarding the video side:
- The C5G uses an additional PLL and all vip IPs run at 120Mhz from this PLL, The LPDDR runs on the 125Mhz
- What is the min freq. that I have to run the vip IPs at? is 50Mhz OK?
- Which IPs have to run on the same clock?
- I have to run the itc at 44.8Mhz
Thanks,
S.
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↧
Altera Monitor Program upload Error
I have downloaded the Altera Monitor Program for use with the DE-0 board. I am able to start it and upload the computer design. I have been able to write verilog in Quartus and upload designs. However when I try and upload a program via Monitor, I get the error box shown in the attached file.
When looking at the Info & Errors window I get this
C:/altera/13.1/quartus/bin/quartus_pgm -c "USB-Blaster [USB-0]" --auto
1) USB-Blaster [USB-0]
020F20DD EP3C16/EP4CE15
C:/altera/13.1/quartus/bin/quartus_pgm -c "USB-Blaster [USB-0]" -m jtag -o P\;"C:/altera/13.1/University_Program/Computer_Systems/DE0/DE0_Basic_Computer/verilog/DE0_Basic_Computer.sof"@1
Info: ************************************************** *****************
Info: Running Quartus II 32-bit Programmer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, Altera MegaCore Function License
Info: Agreement, or other applicable license agreement, including,
Info: without limitation, that your use is for the sole purpose of
Info: programming logic devices manufactured by Altera and sold by
Info: Altera or its authorized distributors. Please refer to the
Info: applicable agreement for further details.
Info: Processing started: Tue Feb 09 09:21:09 2016
Info: Command: quartus_pgm -c "USB-Blaster [USB-0]" -m jtag -o P;C:/altera/13.1/University_Program/Computer_Systems/DE0/DE0_Basic_Computer/verilog/DE0_Basic_Computer.sof@1
Info (213045): Using programming cable "USB-Blaster [USB-0]"
Info (213011): Using programming file C:/altera/13.1/University_Program/Computer_Systems/DE0/DE0_Basic_Computer/verilog/DE0_Basic_Computer.sof with checksum 0x00364108 for device EP3C16F484@1
Info (209060): Started Programmer operation at Tue Feb 09 09:21:10 2016
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x020F20DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Tue Feb 09 09:21:11 2016
Info: Quartus II 32-bit Programmer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 192 megabytes
Info: Processing ended: Tue Feb 09 09:21:11 2016
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
nios2-elf-gcc -g -O1 -ffunction-sections -fverbose-asm -fno-inline -mno-cache-volatile -mhw-mul -mno-hw-div -I"C:/altera/13.1/nios2eds/components/altera_nios2/HAL/inc" -DSYSTEM_BUS_WIDTH=32 -DALT_SINGLE_THREADED -D_JTAG_UART_BASE=268439552 -Wl,--defsym -Wl,nasys_stack_top=0x800000 -Wl,--defsym -Wl,nasys_program_mem=0x0 -Wl,--defsym -Wl,nasys_data_mem=0x0 -Wl,--section-start -Wl,.exceptions=0x20 -Wl,--section-start -Wl,.reset=0x0 -Wl,--script="C:/altera/13.1/University_Program/Monitor_Program/build/nios_cpp_build.ld" -o "C:/731_S16/NiosIIStart/getting_started.elf" "C:/731_S16/NiosIIStart/getting_started.c" "C:/altera/13.1/University_Program/Monitor_Program/lib/jtag_uart.c"
ELF generated at C:/731_S16/NiosIIStart/getting_started.elf.
nios2-elf-objcopy -O srec "C:/731_S16/NiosIIStart/getting_started.elf" "C:/731_S16/NiosIIStart/getting_started.srec"
SREC generated at C:/731_S16/NiosIIStart/getting_started.srec.
Which doesn't say anything about an upload error.
I am on Windows 8.1 and I have tried to update all instances of cygwin.
Any ideas?
Doc Day Kansas State University.
Any ideas
When looking at the Info & Errors window I get this
C:/altera/13.1/quartus/bin/quartus_pgm -c "USB-Blaster [USB-0]" --auto
1) USB-Blaster [USB-0]
020F20DD EP3C16/EP4CE15
C:/altera/13.1/quartus/bin/quartus_pgm -c "USB-Blaster [USB-0]" -m jtag -o P\;"C:/altera/13.1/University_Program/Computer_Systems/DE0/DE0_Basic_Computer/verilog/DE0_Basic_Computer.sof"@1
Info: ************************************************** *****************
Info: Running Quartus II 32-bit Programmer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, Altera MegaCore Function License
Info: Agreement, or other applicable license agreement, including,
Info: without limitation, that your use is for the sole purpose of
Info: programming logic devices manufactured by Altera and sold by
Info: Altera or its authorized distributors. Please refer to the
Info: applicable agreement for further details.
Info: Processing started: Tue Feb 09 09:21:09 2016
Info: Command: quartus_pgm -c "USB-Blaster [USB-0]" -m jtag -o P;C:/altera/13.1/University_Program/Computer_Systems/DE0/DE0_Basic_Computer/verilog/DE0_Basic_Computer.sof@1
Info (213045): Using programming cable "USB-Blaster [USB-0]"
Info (213011): Using programming file C:/altera/13.1/University_Program/Computer_Systems/DE0/DE0_Basic_Computer/verilog/DE0_Basic_Computer.sof with checksum 0x00364108 for device EP3C16F484@1
Info (209060): Started Programmer operation at Tue Feb 09 09:21:10 2016
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x020F20DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Tue Feb 09 09:21:11 2016
Info: Quartus II 32-bit Programmer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 192 megabytes
Info: Processing ended: Tue Feb 09 09:21:11 2016
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
nios2-elf-gcc -g -O1 -ffunction-sections -fverbose-asm -fno-inline -mno-cache-volatile -mhw-mul -mno-hw-div -I"C:/altera/13.1/nios2eds/components/altera_nios2/HAL/inc" -DSYSTEM_BUS_WIDTH=32 -DALT_SINGLE_THREADED -D_JTAG_UART_BASE=268439552 -Wl,--defsym -Wl,nasys_stack_top=0x800000 -Wl,--defsym -Wl,nasys_program_mem=0x0 -Wl,--defsym -Wl,nasys_data_mem=0x0 -Wl,--section-start -Wl,.exceptions=0x20 -Wl,--section-start -Wl,.reset=0x0 -Wl,--script="C:/altera/13.1/University_Program/Monitor_Program/build/nios_cpp_build.ld" -o "C:/731_S16/NiosIIStart/getting_started.elf" "C:/731_S16/NiosIIStart/getting_started.c" "C:/altera/13.1/University_Program/Monitor_Program/lib/jtag_uart.c"
ELF generated at C:/731_S16/NiosIIStart/getting_started.elf.
nios2-elf-objcopy -O srec "C:/731_S16/NiosIIStart/getting_started.elf" "C:/731_S16/NiosIIStart/getting_started.srec"
SREC generated at C:/731_S16/NiosIIStart/getting_started.srec.
Which doesn't say anything about an upload error.
I am on Windows 8.1 and I have tried to update all instances of cygwin.
Any ideas?
Doc Day Kansas State University.
Any ideas
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square wave from cyclone 2 board
i have compiled a code to generate a square wave using Quartus2,downloaded into a cylone2 board. In simulation, the square wave was visible and accurate. How can i connect the fpga board to an oscilloscope to view the square wave?
pin diagrams in data sheet weren't that useful. can somebody please show us how to assign pins in the GPIO modules?
pin diagrams in data sheet weren't that useful. can somebody please show us how to assign pins in the GPIO modules?
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Helio board USB and UART serial interface
Hi, I am new to the forum and have been trying to communicate to my Helio board using the USB.
In the Helio reference manual, it states that the board has an OTG USB PHY (via USB3300-EZK) and a USB-to-UART bridge (via CP2103). I have traditionally used the UART, but I have found it curious that this one uses only 2 pins on the Cyclone V (B19 and C16) -- where as I would normally also use CTS and RTS as control signals.
Therefore, could someone explain to me what the best option for communicating with the board is and if there is sample Verilog/VHDL code out there for realizing this?
Thanks a lot,
Bruno.
In the Helio reference manual, it states that the board has an OTG USB PHY (via USB3300-EZK) and a USB-to-UART bridge (via CP2103). I have traditionally used the UART, but I have found it curious that this one uses only 2 pins on the Cyclone V (B19 and C16) -- where as I would normally also use CTS and RTS as control signals.
Therefore, could someone explain to me what the best option for communicating with the board is and if there is sample Verilog/VHDL code out there for realizing this?
Thanks a lot,
Bruno.
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What is HSSI_PMA_AUX (pma aux. block) in Transceiver?
I've got an error in compile due to something happening in this block.
I couldn't find this pma aux. block anywere in the documents. I am sure it is within HSSI transceiver module but what does it do? Thanks!
I couldn't find this pma aux. block anywere in the documents. I am sure it is within HSSI transceiver module but what does it do? Thanks!
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clearing SGDMA interrupt
Hi all,
I'm attempting to get a momeory-memory SGDMA desgin working, and I'm having some problems with clearing the interrupt from the SGDMA.
The system is roughly as follows:
My problem is that I can perform a single DMA transfer (with multiple descriptors in the chain) just fine, but when attemptiing a second transfer the interrupt never arrives and the driver stalls waiting for it.
On a read() request my driver performs the following actions:
The first read works fine (interrupt arrives correctly etc). The second read hangs at step 6. I suspect that I am not clearing the interrupt from the SGDMA correctly. I'm happy that the Linux driver side of the code (registering interrupts etc) is ok as if I perform a software reset after each transfer (write 1 to SW_RESET bit twice after step 10 above) everything works correctly for multiple transfers.
What am I doing wrong? What should I be doing to clear the interrupt from the SGDMA?
Thanks
Phil
I'm attempting to get a momeory-memory SGDMA desgin working, and I'm having some problems with clearing the interrupt from the SGDMA.
The system is roughly as follows:
- Arria V SoC with two banks of DDR3, one for the HPS, one for attched to the FPGA.
- SGDMA IP core reading from FPGA DDR3 (avl_0 slave port on UniPHY DDR3 controller) and writing to HPS DDR3 (f2h_sdram0_data a slave port on the multi-master DDR controller in the HPS)
- Linux image running on HPS with custom driver for the SGDMA to provide access to FPGA attached DDR3 to userspace Linux software.
- Built using Quartus 15.1 on windows 7 64-bit
My problem is that I can perform a single DMA transfer (with multiple descriptors in the chain) just fine, but when attemptiing a second transfer the interrupt never arrives and the driver stalls waiting for it.
On a read() request my driver performs the following actions:
- Builds a descriptor chain in the dedicated onchip memory attached to the sgdma descriptor ports.
- reads the SGDMA status register to confirm it is not BUSY
- Clears any previous completion bits in the status register by writing 1 to the DESCRIPTOR_COMPLETED and CHAIN_COMPLETED bits.
- sets the next_descriptor_pointer register to point at the start of the descriptor chain.
- sets the IE_CHAIN_COMPLETED, IE_GLOBAL and RUN bits in the control register.
- waits for the interrupt to arrive
- checks the status register to ensure DESCRIPTOR_COMPLETED and CHAIN_COMPLETED bits are set and BUSY is not set.
- clears the status register by writing 1 to the DESCRIPTOR_COMPLETED and CHAIN_COMPLETED bits.
- clears the IRQ by writing 1 to CLEAR_INTERRUPT.
- clears the RUN bit in the control register
The first read works fine (interrupt arrives correctly etc). The second read hangs at step 6. I suspect that I am not clearing the interrupt from the SGDMA correctly. I'm happy that the Linux driver side of the code (registering interrupts etc) is ok as if I perform a software reset after each transfer (write 1 to SW_RESET bit twice after step 10 above) everything works correctly for multiple transfers.
What am I doing wrong? What should I be doing to clear the interrupt from the SGDMA?
Thanks
Phil
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Resuming execution in HPS after FPGA execution
Hello everyone! I am new with the Cyclone V and I am trying to resume execution in HPS after FPGA execution.
I have a HW block developed that will be in the FPGA. From the HPS, this block will receive some data, the block will process it and once the execution is done, I want the FPGA indicates it to the HPS, and so the HPS resume its execution. I have read some about the possibility of used SEV and WFE/WFI ARMv7 instructions, but I don't get how to use it in implementation.
I really appreciate any insight about how to manage this in the best way possible.
Thanks in advance!
I have a HW block developed that will be in the FPGA. From the HPS, this block will receive some data, the block will process it and once the execution is done, I want the FPGA indicates it to the HPS, and so the HPS resume its execution. I have read some about the possibility of used SEV and WFE/WFI ARMv7 instructions, but I don't get how to use it in implementation.
I really appreciate any insight about how to manage this in the best way possible.
Thanks in advance!
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XAUI Tx lane reversal
Hi everyone,
I designed a board with Arria V GX on it.
I have mistakenly reversed (In relation to Rx) the XAUI Tx lanes on my new board.
The compilation fails for the current pin layout.
When I reverse the Tx lanes, compilation succeeds, as expected.
I noticed in "Altera Transceiver PHY IP Core User Guide" 7-13 that:
xgmii_tx_dc[71:0] Contains 4 lanes of data and control for XGMII. Each lane
consists of 16 bits of data and 2 bits of control.
Lane 0[7:0]/[8], [43:36]/[44]
Lane 1[16:9]/[17], [52:45]/[53]
Lane 2[25:18]/[26], [61:54]/[62]
Lane 3[34:27]/[35],[70:63]/[71]
My question is: Can I use the above mentioned fact to reverse the lanes in the xgmii_tx_dc bus and compensate for the serial Tx lanes?
Will it affect the link fault mechanism?
Thanks,
Dror
I designed a board with Arria V GX on it.
I have mistakenly reversed (In relation to Rx) the XAUI Tx lanes on my new board.
The compilation fails for the current pin layout.
When I reverse the Tx lanes, compilation succeeds, as expected.
I noticed in "Altera Transceiver PHY IP Core User Guide" 7-13 that:
xgmii_tx_dc[71:0] Contains 4 lanes of data and control for XGMII. Each lane
consists of 16 bits of data and 2 bits of control.
Lane 0[7:0]/[8], [43:36]/[44]
Lane 1[16:9]/[17], [52:45]/[53]
Lane 2[25:18]/[26], [61:54]/[62]
Lane 3[34:27]/[35],[70:63]/[71]
My question is: Can I use the above mentioned fact to reverse the lanes in the xgmii_tx_dc bus and compensate for the serial Tx lanes?
Will it affect the link fault mechanism?
Thanks,
Dror
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