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Cyclone III I/Os assignment with Pin Planner

March 1, 2016, 12:33 pm
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Hallo


I am working with my project on EP3C16Q240. 240 pins, 160 I/Os. In my project i need to connect 100buttons or knobs. I have got also 16-pin bidirectional data busbetween FPGA and ATXmega and 5-pin control bus. All I need is just100 inputs (activated by connecting with GND) and 21 bidirectionalpins (3.3V).


So I opened a Pin Planer, thinking that5 minutes and everything will be done. I did not expected all thosestrange signs (Q,C, E, diff_n, diff_p etc.). I have got somequestions.


1. Should I really pay atention if pinis dq/dqs or diffrential pin or has another sign? Or I/O is just I/Oand no matter what is its optional function?
2. If not... Could i use diff_n anddiff_p in from one differential pair, as independent inputs? Or useDQS as I/O?
3. What is dev_oe and dev_clr pin?
4. What kind of pin would you use tocreate bidirectional bus with ATXMega?.


With regards:
L.
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Running Quartus on a Blade Server

March 1, 2016, 12:56 pm
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Hello, my System Administrator says that it is possible to install Quartus on his Blade Server and then allow the engineers to remote login to the server and then compile their Quartus programs on the Blade Server instead of their local machines. He claims the compilations and ModelSim Simulations would complete faster. I would like to know if anyone has done this and if so what are the pros and cons if any?

Thanks!
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10/100 Mbps Ethernet with MAX10 device (10M08DCF256I7G)

March 1, 2016, 1:05 pm
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Hello guys,

I need to design a cost sensitive solution for an embedded system using ucLinux. The solution will be basically an IP phone, so the SIP stack must be implemented.

Since cost is very important I'm thinking in MAX10 devices.

For solving the problem I think I need to use the following IP cores:
1) NIOS II processor
2) External SDR SDRAM Controller
3) Triple Speed Ethernet IP
4) External Flash Controller

I would like to use the 10M08DCF256 device based on its cost and features, however I don't know if the resources available are enough for all the IPs I want to use. I have seen examples using the 10M50 devices for TSE but they a lot more expensive than the 10M08DCF256 which is in the target price range.

Bigger devices are too expensive and will kill the project.

If someone can shed some light on this I will be very grateful.

I'm a bit disoriented :( Please help.

Thanks again

Patrick
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[Stratix V] Capturing Eye Scan on Multiple Channels using tcl script

March 1, 2016, 2:10 pm
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Hi,

I'm trying to capture an eye scan using the EyeQ block from the Transceiver Reconfiguration controller. I have written a script and it works for logical channel 0. When I try to use the same script and capture an eye on a different channel, it does not seem to work. I have modified the code to adjust the location of the different pattern checker and to set the logical channel address for the PMA block and the EyeQ block. Does anyone have any suggestions on how to figure out why it isn't working? I am able to capture an eye using the TTK on both channels (I'm just trying to get away from using the TTK), therefore, I know my hardware set up is correct. I think there must be some register I need to set that I just don't know about it.

In my Qsys block the reconfiguration controller is at address 0x800. The data pattern checker 1 is at 0xaa0. My tcl script is attached.

Thanks!
Attached Files
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compile without upgrading IP components in Quartus

March 1, 2016, 2:12 pm
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Is there a way to compile a project without upgrading IP components in 15.0 WEB edition or 15.1 LITE version Quartus? I am recompiling an old project (compiled fine in 12.1SP1). The Quartus is forcing me to upgrade the IP components, which caused many errors.

Thanks for any suggestions!
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Adding lighttpd-fastcgi to Poky version

March 1, 2016, 6:59 pm
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Thanks in advance.

I may be going about this all wrong, so please advise.

I've got a Macnica Cyclone V board that has a Poky 8.0 (Yocto Project 1.3 Reference Distro) 1.3 socfpga.

I'm using the lighttpd that came with this distro
#] lighttpd -v
lighttpd/1.4.31 - a light and fast webserver
Build-Date: Jun 24 2014 09:52:47

I want to add fastcgi support -- when I've used the Angstrom version it's easy you just need to "opkg install lighttpd-module-fastcgi"

So, I figured I'd add opkg from the Angstrom release and do it that way. Change the lighttpd.conf file to enable fastcgi.

But when I try to start lighttpd I get.

root@socfpga:~# /etc/init.d/lighttpd start
Starting Lighttpd Web Server: 2014-06-24 05:12:11: (plugin.c.421) plugin-version doesn't match lighttpd-version for fastcgi
2014-06-24 05:12:11: (server.c.926) Initialization of plugins failed. Going down.
lighttpd.
root@socfpga:~#

SO - I figure EITHER
1. The /etc/opkg/ .conf files are not going to the correct spot to get what I need. Since these go to Angstrom sites.
2. I can't use opkg.

Can anyone EDUCATE ME?
Thanks
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Compilation Fails due to Qsys error

March 1, 2016, 8:26 pm
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Hello everyone.

I am working on a big OpenCL project. I have installed the suite, and I have been able to compile some design examples that were using single work-items kernels, so I thought that everything was working properly.

Hence I started writing my own project, modifying upon an existing structure, and including kernels with multiple work-items. But now, when I try to compile for any board, I get the following error, after some compilation steps:



Error - failed to launch '"c/altera/15.0/quartus/bin64\jre64\bin\java.exe" -Xmx1500M -XX:+UseSerialGC "com.altera.qsys.tcl.QsysScript" "--script=kernel_system.tcl" "-Xmx512M" "-XX:+UseSerialGC" '.
Error - failed to launch '"c/altera/15.0/quartus/bin64\jre64\bin\java.exe" -Xmx1500M -XX:+UseSerialGC "com.altera.qsys.tcl.QsysScript" "--script=kernel_system.tcl" "-Xmx512M" "-XX:+UseSerialGC" '.



If I try modifying the kernels to make them single work-items kernels, then the compilation proceeds and no failure occurs.
Out of curiosity, I downloaded some multiple work-items example designs from Altera website, and I obtained the same error.

Any clue on what the problem might be? I imagine there is some installation issue but I can't figure it out.

Thanks for your help!
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What is the point of Booting From FPGA?

March 1, 2016, 8:41 pm
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I'm reading all of the documentation on Cyclone V SOC and booting. Here's an Altera video: https://www.youtube.com/watch?v=yxWoFuE8gHw

Here's the Altera documentation: https://www.altera.com/content/dam/a.../a10_5400a.pdf

The video discusses the process where the second stage boot loader is loaded in FPGA RAM, which is on the other side of the HPS-FPGA bridge. But after the pre-loader is run from this RAM, the application is loaded from SD card. So why boot from the FPGA if you have an SD card? Why not just combine the preloader and app into the same SD card?

What I'm still trying to determine from all of the Altera documentation, is whether it is possible to:

1. Configure the FPGA from a QSPI attached to the FPGA Fabric (not the HPS QSPI)
2. Then have the HPS boot from the FPGA RAM which contains the pre-loader.
3. Then have the HPS load the application program from the FPGA QSPI

Any comments appreciated as I don't know where to turn to continue with this project. I'll have to move on to Xilinx or another solution (separate FPGA and processor). I've used Altera for over 20 years and the documentation continues to lack specifics.
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How to convert CPLD pin assignment from Allegro Design Entry CIS to Quartus II

March 1, 2016, 11:37 pm
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Hello,

I am using Altera MAX V device. I already have a schematic completed in Allegro Design Entry CIS (.dsn file) with the CPLD signals assignment.
My question is there a automated method to transfer all those signal pins assignment in schematic .dsn file into Quartus II for writting CPLD code?

Through Pin Planner/Pin Assignment in Quartus software, I would need to manually key in each and every signals pin. This is time consuming and more prompt to human error.

Please help.

Thanks
AnthonyT
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opencl aocl diagnose failed

March 2, 2016, 1:06 am
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hi,

I installed the opencl SDK version 15.1. my chip is arria 10(10AX115N4F40I3SGE2)
When I typed the command aocl diagnose , there are some message happended.

Code:
:: [KERNEL] Init: Bar 4, Total offset 0x4000, diff_endian is 0
:: [PLL] Init: Bar 4, Total offset 0xb000, diff_endian is 0
:: [TEMP-SENSOR] Init: Bar 4, Total offset 0xcff0, diff_endian is 0
:: [acla10_ref0] Doing PCIe-to-fabric read test ...
MMD INFO : [acla10_ref0] PCIe-to-fabric read test failed, read 0xffffffff after
1 attempts

Phys Dev Name  Status  Information
acla10_ref0  Failed  Board name not available.
                      Failed initial tests, so not working as expected.
                      Please try again after reprogramming the device.


Found no active device installed on the host machine.

Please make sure to:
      1. Set the environment variable AOCL_BOARD_PACKAGE_ROOT to the correct boa
rd package.
      2. Install the driver from the selected board package.
      3. Properly install the device in the host machine.
      4. Configure the device with a supported OpenCL design.
      5. Reboot the machine if the PCI Express link failed.

DIAGNOSTIC_FAILED
it seems somethiong wrong when when open and initialize accelerators board

Could anyone solve this problem ?

Thanks
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It is annoying the VHDL support in Quartus gets worse and worse

March 2, 2016, 1:28 am
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Why does the VHDL support from Altera keep getting worse?
I keep bumping into IP generated VHDL files that that is just poorly made and in which case I have to use the Verilog generated files.
The only VHDL files I get is wrappers for Verilog files, I really do not want this!
I just generated a DDR2 controller and specifically asked for VHDL, but I get a Verilog example design?
/Jon
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Downloading on the custom MAX10 board with USB Blaster

March 2, 2016, 3:50 am
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Hello everyone of our forum.

I have a question about interfacing to the fpga board using the usb blaster.

We designed the custom FPGA board equipped with MAX 10 chip (10M50DAF484C8G).

Meanwhile, the other custom Cyclone IV FPGA board in our lab can interface with the PC by using USB Blaster.

However, the MAX 10 FPGA board cannot do that on the same situation.

In detail, Auto decect in Altera Quartus II programmer dosen't work not at all.

I don't know well our problem.

Just to be sure, I think the cause of it is that I don't use the USB Blaster II.

I make a request to you about solving it.

Thank you.


P.S.

Designing and testing of MAX 10 FPGA board obeys the reference of Altera document.
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Quartus routing taking a long time, stuck with only 2 signals un-routed

March 2, 2016, 5:33 am
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is there a way to find out what those two signals are? Thanks.
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MAX10 damage if VCC_PLL pins not connected???

March 2, 2016, 8:38 am
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Will a MAX10 10M04DAF256C8G be damaged if the device is powered up with the 2 VCC_PLL and/or 2 VCCA voltage pins floating?

Background:
We have a PCB with a wiring error where the VCC_PLL pins were wired to 3.3V (I/O voltage) instead of 1.2V core voltage. We are not using any of the analog functions on the MAX10 and VCCA pins are connected to 3.3V I/O voltage. Each of the above VDD_PLL and VCCA pairs of pins are connected with a trace on the top layer (under the MAX10) and each pair is fed from a 3.3V via connected to the 3.3V power plane. We have isolated each of these pairs of pins from the 3.3V plane by micro drilling from the bottom at the via location. What is left is the 4 pins are floating but each VCC_PLL/VCCA pin pair is still connected with the top layer trace.

So... at this point we have one of 6 very expensive pre-production boards in this isolated state and are ready to power it up to test. We realize that the PLLs aren't going to work but can proceed to test much of the board to see if there are any more nasty errors such as this one. If we find everything is OK, there are several ways we can connect to the via barrel which is visible and accessible at the bottom of the hole drilled to isolate from the 3.3V plane and wire to a nearby 1.2V node. In that way, we can rework and save the 6 boards!

The question is then will we damage the MAX10 by powering it up with the VDD_PLL pins floating but each connected to a VCCA pin? Note: the VCCA pins are NOT bussed on the MAX10 and we are assuming that 2 of the VCCA pins connected to 1.2V and the rest to 3.3V will not be an issue since we are not using any of the analog functions.

Any advice on this will be much appreciated!


Thanks
Al
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sgDMA interrupt from FPGA to Linux User Space

March 2, 2016, 10:52 am
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Hi all,

I wondering if a Linux kernel module has been developed for the sgDMA IP. What is needed is the capability of registering an interrupt for DMA completion in Linux user space, similar to the Altera GPIO kernel module interrupt. If the kernel module has been written, does anyone know when it may be included in the mainstream kernel repo?

Thanks.
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Max10 UFM Simulation Error 0197 on Write Operation

March 2, 2016, 11:04 am
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I am testing out the Max10 User Flash Memory IP (on-chip flash block) but have run into an issue.

So far I have been able to perform multiple reads and a single write.

When I try to perform more than 1 write in a single simulation, the simulator gives me this message:

"ERROR[0197]: DIN should keep the same for the extra program pulse during smart program or after a successful smart program sequence"

I don't know what this error message is trying to tell me.

some more info:
I am performing 32-bit parallel reads and writes (burst_count=1).
The status register reads "ffffff8e" during the error-prone write.
My inputs to the IP do not change during a write operation.
I have tried waiting up to 1ms between writes, no change.


I mainly want to know why/how this error occurs.
Thanks.
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Question about exchanging the generated verilog module

March 2, 2016, 11:14 am
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Hello,

It's possible exchanging the generated verilog module for the kernel by another module developed by me or a component library?

Regards,
Paulo
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syntax error at medias_2.vhd(31) near text "in"; expecting "(",

March 2, 2016, 12:14 pm
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I've got this error in the following code, what's wrong in it? Thanks in advance.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_signed.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
--package imagens is
--type image_array is array(0 to 49, 0 to 49) of unsigned(7 downto 0);
--type image_derivadas is array(0 to 49, 0 to 49) of unsigned (8 downto 0);
--type image_19bits is array (0 to 49, 0 to 49) of unsigned (18 downto 0);
--end package imagens;


entity medias_2 is
port(


--divisor: in image_19bits;
--dividendo: in image_derivadas;
uk2: in image_19bits;
vk2: in image_19bits;
mediau2: out image_19bits;
mediav2: out image_19bits


); end medias_2;






architecture behaviour of medias_1 is


--FOR
for x in 1 to 48 loop
for y in 1 to 48 loop
--mediami[i][j] = (mi(x-1,y-1)+mi(x-1,y)+mi(x-1,y+1)+mi(x,y-1)+mi(x,y)+mi(x,y+1)+mi(x+1,y-1)+mi(x+1,y)+mi(x+1,y+1))/9;


--mediani[i][j] = (ni(x-1,y-1)+ni(x-1,y)+ni(x-1,y+1)+ni(x,y-1)+ni(x,y)+ni(x,y+1)+ni(x+1,y-1)+ni(x+1,y)+ni(x+1,y+1))/9;
mediau2(x,y) <= (uk2(x-1,y-1)+uk2(x-1,y)+uk2(x-1,y+1)+uk2(x,y-1)+uk2(x,y)+uk2(x,y+1)+uk2(x+1,y-1)+uk2(x+1,y)+uk2(x+1,y+1))/9;
mediav2(x,y) <= (vk2(x-1,y-1)+vk2(x-1,y)+vk2(x-1,y+1)+vk2(x,y-1)+vk2(x,y)+vk2(x,y+1)+vk2(x+1,y-1)+vk2(x+1,y)+vk2(x+1,y+1))/9;


end loop;
end loop;


for x in 1 to 48 loop
mediau2(0,y) <= (uk2(x-1,0)+uk2(x-1,1)+uk2(x,0)+uk2(x,1)+uk2(x+1,0)+uk2(x+1,1))/6;
mediau2(49,y) <= (uk2(x-1,48)+uk2(x-1,49)+uk2(x,48)+uk2(x,49)+uk2(x+1,48)+uk2(x+1,49))/6;
mediav2(0,y) <= (vk2(x-1,0)+vk2(x-1,1)+vk2(x,0)+vk2(x,1)+vk2(x+1,0)+vk2(x+1,1))/6;
mediav2(49,y) <= (vk2(x-1,48)+vk2(x-1,49)+vk2(x,48)+vk2(x,49)+vk2(x+1,48)+vk2(x+1,49))/6;


end loop;


for y in 1 to 48 loop
mediau2(0,y) <= (uk2(0,y-1)+uk2(0,y)+uk2(0,y+1)+uk2(1,y-1)+uk2(1,y)+uk2(1,y+1))/6;
mediau2(49,y) <= (uk2(48,y-1)+uk2(48,y)+uk2(48,y+1)+uk2(49,y-1)+uk2(49,y)+uk2(49,y+1))/6;
mediav2(0,y) <= (vk2(0,y-1)+vk2(0,y)+vk2(0,y+1)+vk2(1,y-1)+vk2(1,y)+vk2(1,y+1))/6;
mediav2(49,y) <= (vk2(48,y-1)+vk2(48,y)+vk2(48,y+1)+vk2(49,y-1)+vk2(49,y)+vk2(49,y+1))/6;


end loop;


mediau2(0,0)<= (uk2(0,0)+uk2(0,1)+uk2(1,0)+uk2(1,1))/4;
mediau2(0,49)<= (uk2(0,48)+uk2(0,49)+uk2(1,48)+uk2(1,49))/4;
mediau2(49,0)<= (uk2(48,0)+uk2(48,1)+uk2(49,0)+uk2(49,1))/4;
mediau2(49,49)<= (uk2(48,48)+uk2(48,49)+uk2(49,48)+uk2(49,49))/4;
mediav2(0,0)<= (vk2(0,0)+vk2(0,1)+vk2(1,0)+vk2(1,1))/4;
mediav2(0,49)<= (vk2(0,48)+vk2(0,49)+vk2(1,48)+vk2(1,49))/4;
mediav2(49,0)<= (vk2(48,0)+vk2(48,1)+vk2(49,0)+vk2(49,1))/4;
mediav2(49,49)<= (vk2(48,48)+vk2(48,49)+vk2(49,48)+vk2(49,49))/4;


end process;
end behaviour;
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DE1-SOC Board for Beginners

March 2, 2016, 1:10 pm
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Hi, I am currently a high school student, and I am looking to get into FPGA design. I have about five years of experience with programming, and a couple years with electronics design, but almost no experience with FPGAs. I am planning on purchasing a DE1-SOC board, mostly to design soft processors, but also for robotics projects, and experimentation. To me the board seems ideal over the alternatives because (with the academic discount), it seems to offer nearly everything the Cyclone V starter board does, plus the SOC, for about the same price. My main concern however, is if the SOC would complicate things or get in the way when not in use. For example, I would like to use the SD card in some of my FPGA only designs, and so I’m curious if that will be harder since the SD is on the HPS side. My other concern is with how much less ram the DE1-SOC has over the alternatives (64MB on the FPGA 1GB on the SOC, vs 4gb on the FPGA for the Cyclone V starter), and so I was wondering if the ram on the SOC can be made available to the FPGA, or if it is possible to extend the ram externally.

So basically what I am asking is, is the DE1-SOC a suitable board for complete beginners in FPGA, and is the ram on it limiting? Thank you for your help.
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10G MAC ip core stop working after a long time ethernet packets transmission

March 2, 2016, 3:15 pm
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Hello guys,

I encountered a problem when I was debugging the Ethernet connection between two DE5 board. The DE5 board contains one Stratix V FPGA. I instantiated one PHY_10GBASE_R ip core and one 10G MAC ip core in each FPGA to build the Ethernet interface. Assuming one board is the master board and the other is the slave board. I used the master board to transmit ethernet packets to the slave board. When slave board received packets, it just transmitted these packets back to master. Master board matched the sent and received packets and checked the ethernet connection.

At first, the Ethernet connection seems working well. Packets can be exchanged between these two boards. But when I have kept the transmission working for a long time, it would shut down automatically. I found the problem caused by the avalon_st_tx_ready signal comes from 10G MAC core. Usually, this signal is high. Sometimes it fall to low but would retrieve to high quickly. But after working for a long time, this signal fell to low and couldn't retrieve. I don't know why it can't retrieve. I was trying to reset the 10G MAC core, the avalon_st_tx_ready signal can be retrieved. But when I started the transmission again, the avalon_st_tx_ready signal fell again.

Does anyone run into the same problem? Please give me some clue or advice.

Thanks
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