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VIP Clocked Video Out Problem

March 2, 2016, 6:14 pm
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I am having some problems with the VIP CVO IP. My QSYS core frequency is 100Mhz
But my CVO IP output must run at a different frequency. Initially I used 44.8Mhz
And it seemed to work ok. However, when I doubled the CVO clock in to 89.6

It stopped working – the LPDDR2 would not calibrate, etc. etc. Again, I’m applying
An external clock to the CVO (ITC) expecting it to sync between the internal 100Mhz
And external 89.6Mhz. I did not configure for a control port and simply relying on
The width/height, etc. setting which are not standard. Does it mean that the system

Can’t keep up with to 89.6? should I increase it to 120Mhz.

Thanks,
S.
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GPIO inOut/Bidir using Qsys to read and write to the same port!

March 2, 2016, 8:11 pm
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I am willing to connect the IDE2_115 to 24bit AD7760 and I want to write to the registers and read data from the same port. I used QSYS and once defined the GPIO port as bidir and I could only read the data, and by having inOut I could only write to the port (I mapped both export_in and export_out to the same inout GPIO pins ). whether to write 0 or 1 to the port at bidir mode the output voltage remains constant at 0.97V
any suggestion to have GPIO both input and output at the same time? Do I need an external pull up resistor array?
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Quartus-II OpenCL tool support for Ubuntu

March 3, 2016, 12:58 am
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Hi,
I would like to use Ubuntu host for OpenCL development on Altera FPGA. Does Quartus-II OpenCL supports Ubuntu 14.04 Intel 64-bit support?
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Why does Quartus II not have get_all_location_assignments collection in tcl?

March 3, 2016, 12:59 am
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The set_location_assignment is used to set a port on the design to connect to a pin on the FPGA. I doubt this has any other applications.
How do I get a collection of all the pin location assignments and print them to a file since a collection cannot be obtained using the expected way.
How does one use tcl to remove all pin assignments in the pin planner so we can start over again?
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MAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example

March 3, 2016, 1:40 am
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Hello all,

I am just starting out with ethernet on the max10 development kit (10M50DAF484C6GES) and I am trying to use 'MAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example' (https://cloud.altera.com/devstore/platform/15.1.0/max-10-single-port-triple-speed-ethernet-and-on-board-phy-chip-design-example/). I program the max10 but when I to run a 'test_mac_lb' in the system console the test starts but it always says that the Phy link down (This error is from tse_marvel_phy.tcl). As mentioned I am fairly new to this and have no idea where to start debugging. Any help would be greatly appreciated.

Thanks,
Ere
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Problem with Altera ASMI Parallel IP

March 3, 2016, 1:48 am
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We are using Cyclone V SX with EPCQ256 memory. We would like to use the flash memory for user data since the FPGA is configured from the HPS. I have added the Altera's ASMI Parallel IP to our Qsys system. The ASMI Parallel is controlled by our custom IP block. I have problem with the Protect Sector command since the memory freezes after this command. The asmi_busy signal locks to high state after the sector_protect- and wren-signals are asserted. It seems that there is some problem with writing to the status register since the other memory commands work without any problems. Has anybody any ideas how to fix this problem? I have also tried to use the Altera's Generic Quad SPI Controller but the same problem occurs also with that. I have tried also to lower the clock frequency of the memory from 20 MHz to 1 MHz but it doesn't help.

best regards,
Joonas
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MAX 10 cadence symbol error

March 3, 2016, 2:40 am
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Hi,

I'm designing a board base on MAX 10 (10M04DAU324) with UBGA324 package.

I downloaded cadence symbol from https://www.altera.com/support/suppo...b-cadence.html => MAX 10 => 10M04DA => 10M04DA.OLB

I found a difference between the symbol and documentation :

When looking on pinout documentation : https://www.altera.com/content/dam/a...10/10m04da.pdf
We have this pinout :
VCCA_ADC on F4
ADC1IN1 on D4
ADC1IN6 on E5

But in the symbol :
VCCA_ADC on D4
ADC1IN6 on F4
ADC1IN1 on E5

Which one is right ? I think the documentation is, but I want to be sure =)

Thanks
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Error: Peak virtual memory when compile NIOS design file

March 3, 2016, 3:39 am
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Hi everyone,

I get a error when I compile a block diagram design file.

I think there are some error of my design, but I can't find it. How can I solve the problem?
http://imgur.com/zpUkMxy
I just connect the I/O to the correspond pin.


Many Thanks
Attached Images
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FPGA2HPS address define

March 3, 2016, 5:02 am
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I am using HWLIB and SOCAL to implement the bare metal part of an AMP (Linux + bare metal) application.

The hps.h defines quite a lot of addresses, but I can't find any define for FPGA2HPS base address. A grep for 0xC0000000 on the whole disc found nothing. Do I really have to use my own magic number?

Best Regards,
Joachim
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How to set SMP bit and enable SCU

March 3, 2016, 5:13 am
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I am implementing the bate metal part of an AMP (Linux + bare metal) application.

Before enabling caches I should set the SMP bit (because there are shared memory regions) and enable the SCU.

I can find no means in HWLIB or SOCAL to do this. The HWLIB cache.c has defines for the SMP bit and read/write functions for the ACTRL register. But all these are just static inside the c module. No access from outside.

Currently the only way to get the system running prperly is to copy code and implement my own jw_alt_cache.c.

I expected the HWLIB to give me access to every register I might need. Or to wrap all necessary bits. Or did I overlook something?

Joachim
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Issues while installing Altera Byte Blaster driver on WES-7

March 3, 2016, 5:17 am
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We are trying to install Altera Byte Blaster driver on WES-7. We have downloaded jampatch.exe from Altera, which when executed, created pgdhdlc.dll, pgdhdlc.sys & INF file. But while installing, thru add new hardware wizard, getting error as "The system cannot find specified files". Files with the same version, are installed and working fine on windows-XP.
Does the pgdhdlc supports only XP? In this case, how we can get the drivers which would support WES-7.
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swinfo2header defines no real addresses

March 3, 2016, 5:29 am
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I am implementing the HPS part of a complex appliucation. The FPGA designer send me his rbf file and the generated header of the FPGA devices I can access.

The generated header has NO information about the address of the individual devices! :confused: It just defines _BASE addresses, that need some offset. And the get the correct offset to each device I need addtional emails. If the FPGA designer changes the interface of a register (eg. from LW bridge to F2H bridge) my software has to be adapted manually!

Why does that tool lack to generate addresses of the devices? That is about all I need from the header and it's not in there.

Joachim
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ONFI nand on Arria10

March 3, 2016, 6:33 am
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I want to implement an ONFI NAND flash in asynchronous and synchronous mode on Arria 10.

For synchronous mode, I use phylite module.

But i would like to use the NAND flash in both mode (asynchronous and synchronous), I create a phylite component for synchronous and I add a register to read the data coming from NAND flash component in asynchronous because in asynchronous, dqs signal is not driven. Quartus generates an error ("Source also drive out to other destination than the buffer").

My logic:

inout [7:0] data,
inout dqs

phylite phylite_inst(
.ref_clk(clk),
.reset_n(rstn),
.interface_locked(/*OPEN*/),
.group_0_data_io(data),
.group_0_strobe_io(dqs)
);

always @(posedge clk) begin
data_in_asynchronous <= data;
end

Do you any idea to resolve my issue?

Thank in advance.
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ELF downloaded but switchers don't respond !!!

March 3, 2016, 6:55 am
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hello
I am working on niosII 13.0 web edition trying to command 2 LEDs using 2 Switchers on Cyclone III board
the niosII console shows that the elf is downloaded BUT when i click on Sw nothing happens !!
what could be the problem ?!

Downloading 00004000 ( 0%)Downloading 00004F0C (61%)Downloaded 4KB in 0.0s Verifying 00004000 ( 0%)Verifying 00004F0C (61%)Verified OK Starting processor at address 0x00004020
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Active Parallel Configuration at less than 40MHz, is it possible?

March 3, 2016, 7:12 am
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The Altera website states that:


"You can perform active parallel (AP) configuration using a supported common flash interface (CFI) parallel flash memory. During AP configuration, the Altera® device is the master and the parallel flash memory is the slave. Configuration data is transferred to the Altera device on the DATA[15:0] pins. This configuration data is synchronized to the DCLK input. Configuration data is transferred at a rate of 16 bits per clock cycle. The DCLK frequency driven out by the Altera device during AP configuration is approximately 40 MHz.
For more information, please refer to the configuration chapter of the relevant Altera device in the Configuration Handbook. "



And...



"The Active Serial (AS) configuration scheme is supported in the 1 bit data width (AS x1) or the 4 bit data width (AS x4). The AS x4 scheme is supported only in Stratix® V devices. AS configuration can be performed using an Altera® serial configuration (EPCS) device or quad-serial configuration (EPCQ) device. During AS configuration, the Altera FPGA acts as the configuration master and the EPCS or EPCQ device acts as the configuration slave. The FPGA outputs the clock on the DCLK pin and receives the configuration data from the EPCS or EPCQ device on the data pin(s).
For more information, refer to the configuration chapter of the relevant Altera device in the Configuration Handbook. "


I assume that this means the flash memory must be a "CFI" flash, regardless of who manufactures it. Besides this, it seems to imply that the configuration can only occur at 40MHz and not any lower than that.
My questions are:
(1) Why is only a CFI flash required for AP configuration? What is deficient in non-CFI flash?
(2) What is the frequency given as 40MHz? Certainly slower devices shall be cheaper and the amount of time it takes to configure the FPGA will not have changed drastically from human experience.
(3) Why is only an EPCS and EPCQ device required for AS configuration? What is deficient in normal serial flash?


On another note, which is the main reason for this question,
(4) It is quite clear that the EPCS/EPCQ devices for serial configuration are mere flash devices yet cost significantly more than a "normal" flash device. Why is this so?
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Clock generator on DE0-Nano-SoC

March 3, 2016, 7:26 am
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The Terasic DE0-Nano-SoC contains a programmable clock generator (CDCE937) which is controllable from I2C. The bundled example GHRD design has conditional FPGA port definitions (CLK_I2C_SDA/SCL), but does not assign any pins to them. When I investigate the schematics, it seems the I2C bus is not connected to the FPGA at all. So it seems that Terasic planned to connect them to the FPGA, but haven't?
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Avalon ST custom IP component

March 3, 2016, 8:23 am
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Hello,

I'm having trouble creating my own component that uses Avalon Streaming Interface in QSys. Based on the VIP demonstartion for DE1-SoC I want to have a connection between the Altera VIP Frame Reader and Alpha Blending Mixer (to process the frames that are sent). In order to do that I created a VHDL file and created a new component in QSys, specyfing the data, valid, ready, startofpacket and endofpacket signals since these are the ones used by Frame Reader and Blending Mixer. I check if the valid and ready signals are asserted and then just pass the data, startofpacket and endofpacket signals through. In QSys I also needed to add Timing Adapters before and after my component because of Ready Latency. Unfortunately, the frames flows continously and are moving through the vga screen so I believe there's something wrong with the logic in my component. I check the signals at the rising edge of the clock. I'm new to the Avalon stuff and I'm sure I'm missing something really simple in the code. I attach it below. Could you help me find what's missing in here?

Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;




ENTITY simple_avalon_interface IS
PORT (
clock, resetn : IN STD_LOGIC;


din_startofpacket : in std_logic;
din_endofpacket : in std_logic;
din_valid : in std_LOGIC;
din_ready : out STD_LOGIC;
din_data : in STD_LOGIC_VECTOR(23 DOWNTO 0);


dout_startofpacket : out std_logic;
dout_endofpacket : out std_logic;
dout_valid : out std_LOGIC;
dout_ready : in STD_LOGIC;
dout_data : out STD_LOGIC_VECTOR(23 DOWNTO 0)


);
END simple_avalon_interface;






ARCHITECTURE Structure OF simple_avalon_interface IS


BEGIN


process (clock,dout_ready,din_valid)
begin
if (rising_edge(clock)) then
    if (dout_ready ='1' and din_valid = '1') then   
        dout_valid <= '1';
        din_ready <= '1';
        dout_data <= din_data;
        dout_startofpacket <= din_startofpacket;
        dout_endofpacket <= din_endofpacket;
    else


        dout_valid <= '0';
        din_ready <= '0';
    end if;
end if;
end process;




END Structure;
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max burst size

March 3, 2016, 9:46 am
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Can you tell me why the max burst size for Altera DDR2 DRAM is set at 64?
I need to transfer 1.2Mb of data in more than 64 64 bit blocks (4096 bytes)
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Error DS-5 install

March 3, 2016, 11:59 am
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Hello, I'm having trouble installing the DS-5 on RHEL 6.7, I can not resolve this dependency:
--- Running installation platform requirement checks

/tmp/inst_temp.2994/dependency_check_linux-x86_64.sh: line 13: 3087 Segmentation fault (core dumped) ${SCRIPT_DIR}/library_checker_$2 $1 2> /dev/null
Running dependency check [failed]
*** WARNING ***
One or more of the DS-5 system dependencies are not installed, see below for a list of the missing libraries.

libGL.so.1 (32-bit)

We recommend you install the missing dependencies, otherwise the programs will not run correctly. For further information see the DS-5 readme.

When I run the embedded_command_shell.sh, I have:
WARNING: DS-5 install not detected. SoC EDS may not function correctly without a DS-5 install.
------------------------------------------------
Altera Embedded Command Shell

Version 15.1.1 [Build 60]
------------------------------------------------

Someone had the same problem? Or you can show me another OS?

Regards,
Paulo
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DE2-115 Niche Stack. Undefined reference to marvell_cfg_rgmii

March 3, 2016, 10:58 am
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Hello,

I am currently trying to create Ethernet communication from a DE2-115 board to PC. I have followed guidelines set out in this thread http://www.alteraforum.com/forum/sho...t=28837&page=6 , and have also referenced the TSE for de2-115 tutorial and Niche/Stack tutorial.

Upon building the project I encounter this error. Is anyone able to assist with this?
If there are any other files or screen shots that you require please ask.

Kind regards
Dan



18:23:16 **** Incremental Build of configuration Nios II for project socket_server ****
make all
Info: Building ../socket_server_bsp/
C:/altera/15.0/nios2eds/bin/gnu/H-x86_64-mingw32/bin/make --no-print-directory -C ../socket_server_bsp/
[BSP build complete]
Info: Linking socket_server.elf
nios2-elf-g++ -T'../socket_server_bsp//linker.x' -msys-crt0='../socket_server_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../socket_server_bsp/ -Wl,-Map=socket_server.map -O0 -g -Wall -mno-hw-div -mhw-mul -mno-hw-mulx -o socket_server.elf obj/default/SSS_DE2_115.o obj/default/alt_eeprom/alt_2_wire.o obj/default/alt_eeprom/alt_eeprom.o obj/default/alt_error_handler.o obj/default/iniche_init.o obj/default/led.o obj/default/network_utilities.o obj/default/simple_socket_server.o obj/default/tse_my_system.o -lm -msys-lib=m
obj/default/tse_my_system.o:(.data+0x44): undefined reference to `marvell_cfg_rgmii'
collect2.exe: error: ld returned 1 exit status
make: *** [socket_server.elf] Error 1


18:23:19 Build Finished (took 2s.953ms)
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