can i implement a demodulator circuit including fir filter and envelop detector in a cpld like fpga....
↧
cpld related
↧
Problem: interfacing DDR2 with Terasic DE-4 CALIBRATION FAILURE
Hi everyone!
I've spent at least 6 week trying to interface a DDR2 1GB SO-DIMM RAM (200 Pin, 800 Mbps, CAS latency 6) with my (university) board Terasic DE-4. Above this board is mounted a Stratix IV EP4SGX230KF40C3 (speed-grade 3), and we have two socket for the memory RAM on the Terasic DE-4 board.
To interface my memory I used Quartus Prime 13.0 sp1, so with Megawizard Plug-In Manager I used the Controller Uniphy 13.0 (400 MHz for memory and 100 MHz for PLL reference clock). Anyway, I wrote a verilog code and I simulated it, it looked fine, and it worked as I wanted. When I tried to compile and run my code on the Board it didn't work because of a calibration failure.
I'm sure that my code works on the board, the simulation tells me that the controller works fine, but when I see what happen with the Signal Tap Analyzer I see that the local_cal_fail signal is asserted... and I don't know why. I've obviously made a pin planning, using the tcl script that comes from the Controller Uniphy wizard, and I've manually set all pin that the FPGA use to communicate with the DDR2 (DQ, CK, DQS, DM etc...). Moreover, I set the pin for oct_rup and oct_rdn, i.e. on chip termination, at 50 Ohm parallel termination in assignment editor and I assigned two pin on the FPGA with a proper voltage standard.
With the tool: External Memory Debug Toolkit I can read that the calibration failed during the first stage: Read Guaranteed failure.
So... Is there anyone who can tell me any guideline to verify that my work chain is good? Anyone that can give me any hint? Would be my problem due to a Board Skew not considered in the Altera Standard settings?
Thanks to everybody will give me an answer,
King Regards!
Gennaro
PS: I'm an Italian student, this is my first thread, and this is my first experience in a complex project with an FPGA, sorry if my english isn't good enough! I hope I gave enough information about the issue. Don't hesitate to ask more information to solve the issue.
I've spent at least 6 week trying to interface a DDR2 1GB SO-DIMM RAM (200 Pin, 800 Mbps, CAS latency 6) with my (university) board Terasic DE-4. Above this board is mounted a Stratix IV EP4SGX230KF40C3 (speed-grade 3), and we have two socket for the memory RAM on the Terasic DE-4 board.
To interface my memory I used Quartus Prime 13.0 sp1, so with Megawizard Plug-In Manager I used the Controller Uniphy 13.0 (400 MHz for memory and 100 MHz for PLL reference clock). Anyway, I wrote a verilog code and I simulated it, it looked fine, and it worked as I wanted. When I tried to compile and run my code on the Board it didn't work because of a calibration failure.
I'm sure that my code works on the board, the simulation tells me that the controller works fine, but when I see what happen with the Signal Tap Analyzer I see that the local_cal_fail signal is asserted... and I don't know why. I've obviously made a pin planning, using the tcl script that comes from the Controller Uniphy wizard, and I've manually set all pin that the FPGA use to communicate with the DDR2 (DQ, CK, DQS, DM etc...). Moreover, I set the pin for oct_rup and oct_rdn, i.e. on chip termination, at 50 Ohm parallel termination in assignment editor and I assigned two pin on the FPGA with a proper voltage standard.
With the tool: External Memory Debug Toolkit I can read that the calibration failed during the first stage: Read Guaranteed failure.
So... Is there anyone who can tell me any guideline to verify that my work chain is good? Anyone that can give me any hint? Would be my problem due to a Board Skew not considered in the Altera Standard settings?
Thanks to everybody will give me an answer,
King Regards!
Gennaro
PS: I'm an Italian student, this is my first thread, and this is my first experience in a complex project with an FPGA, sorry if my english isn't good enough! I hope I gave enough information about the issue. Don't hesitate to ask more information to solve the issue.
↧
↧
Is it possible to implement AES-256 algorithm in Altera cyclone iv E DE2 115 board?
Hi guys,
If its not possible to implement in this board, please suggest me any board?
If its not possible to implement in this board, please suggest me any board?
↧
DEAD TIME TO CONTROL 2 SYNCHRONOUS MOSFET (BUCK CONVERTER) help!!!!!!!
HELLO.
I AM A STUDENT AND I AM TRYING TO IMPLEMENT AN STATE MACHINE TO CONTROL A BUCK CONVERTER. IN THIS PART OF CODE, I AM TRYING TO COMMUTE 2 MOSFET (HIGH SIDE AND LOW SIDE). EACH 20ms MOSFET1 (m1) IS IN "ON" AND MOSFET1 (m2) IN "OFF" AND THEN REVERSE.
UP THIS POINT, THE CODE WORKS. BUT, I NEED TO PROGRAM A DEAD TIME TO PREVENT 2 MOSFETS ARE IN STATE "ON" DURING THE COMMUTATION TO AVOID A DEAD SHORT OF THE SOURCE. I put that this dead time has to be of 60ns. It is to assure that (for example): when m1 pass from state "1" to "0" then count to 60ns and then (we are assured that m1 doesn't work) to active m2 '1'.
THE DELAY PART OF THE CODE IS NOT HERE. I DON'T KNOW HOW TO DO. IT SEEMS TO BE EASY BUT....THE condition "after" or "wait" is not permited because this code is for implementing and "after" and "wait" is only for simulation!!!
SOME HELP? THANK YOU VERY MUCH IN ADVANCE!!
entity controllerSource is
generic(timeM: integer:= 1000000); --20 ms (switching time between Mosfets)
generic(timeR: integer:= 3); --60 ns (delay to avoid being 2 MOSFETS in "on" state at the same time)
Port( clk : in std_logic;
rst : in std_logic;
m1: out std_logic; -- Mosfet HIGH side
m2: out std_logic); -- Mosfet LOW side
end entity;
architecture c1 of controllerSource is
signal counter: unsigned(23 downto 0);
signal cont: unsigned(23 downto 0);
signal y: std_logic;
begin
counter: process (clk, rst)
begin
if rst = '1' then
counter<=(others => '0');
cont<=(others => '0');
elsif (clk'EVENT and clk = '1') then -- 1 clock period each 50Mhz
counter<=counter+1;
cont<=cont+1;
if counter=timeM then -- 20ms
counter<=(others => '0');
end if;
if cont=tiempoR then -- 60ns
cont<=(others => '0');
end if;
end if;
end process;
commutation: process (clk, rst)
begin
if rst = '1' then
m1<='1';
m2<='0';
y<='0';
elsif (clk'EVENT and clk = '1') then
if counter=timeM then --every time that arrive to 20ms commute the state of mosfets
if y='0' then
y<='1';
m1<='0';
m2<='1';
else
y<='0';
m2<='0';
m1<='1';
end if;
end if;
end if;
end process;
end c1;
I AM A STUDENT AND I AM TRYING TO IMPLEMENT AN STATE MACHINE TO CONTROL A BUCK CONVERTER. IN THIS PART OF CODE, I AM TRYING TO COMMUTE 2 MOSFET (HIGH SIDE AND LOW SIDE). EACH 20ms MOSFET1 (m1) IS IN "ON" AND MOSFET1 (m2) IN "OFF" AND THEN REVERSE.
UP THIS POINT, THE CODE WORKS. BUT, I NEED TO PROGRAM A DEAD TIME TO PREVENT 2 MOSFETS ARE IN STATE "ON" DURING THE COMMUTATION TO AVOID A DEAD SHORT OF THE SOURCE. I put that this dead time has to be of 60ns. It is to assure that (for example): when m1 pass from state "1" to "0" then count to 60ns and then (we are assured that m1 doesn't work) to active m2 '1'.
THE DELAY PART OF THE CODE IS NOT HERE. I DON'T KNOW HOW TO DO. IT SEEMS TO BE EASY BUT....THE condition "after" or "wait" is not permited because this code is for implementing and "after" and "wait" is only for simulation!!!
SOME HELP? THANK YOU VERY MUCH IN ADVANCE!!
entity controllerSource is
generic(timeM: integer:= 1000000); --20 ms (switching time between Mosfets)
generic(timeR: integer:= 3); --60 ns (delay to avoid being 2 MOSFETS in "on" state at the same time)
Port( clk : in std_logic;
rst : in std_logic;
m1: out std_logic; -- Mosfet HIGH side
m2: out std_logic); -- Mosfet LOW side
end entity;
architecture c1 of controllerSource is
signal counter: unsigned(23 downto 0);
signal cont: unsigned(23 downto 0);
signal y: std_logic;
begin
counter: process (clk, rst)
begin
if rst = '1' then
counter<=(others => '0');
cont<=(others => '0');
elsif (clk'EVENT and clk = '1') then -- 1 clock period each 50Mhz
counter<=counter+1;
cont<=cont+1;
if counter=timeM then -- 20ms
counter<=(others => '0');
end if;
if cont=tiempoR then -- 60ns
cont<=(others => '0');
end if;
end if;
end process;
commutation: process (clk, rst)
begin
if rst = '1' then
m1<='1';
m2<='0';
y<='0';
elsif (clk'EVENT and clk = '1') then
if counter=timeM then --every time that arrive to 20ms commute the state of mosfets
if y='0' then
y<='1';
m1<='0';
m2<='1';
else
y<='0';
m2<='0';
m1<='1';
end if;
end if;
end if;
end process;
end c1;
↧
DEAD TIME TO CONTROL 2 SYNCHRONOUS MOSFET (BUCK CONVERTER) help!!!!!!!
HELLO.
I AM A STUDENT AND I AM TRYING TO IMPLEMENT AN STATE MACHINE TO CONTROL A BUCK CONVERTER. IN THIS PART OF CODE, I AM TRYING TO COMMUTE 2 MOSFET (HIGH SIDE AND LOW SIDE). EACH 20ms MOSFET1 (m1) IS IN "ON" AND MOSFET1 (m2) IN "OFF" AND THEN REVERSE.
UP THIS POINT, THE CODE WORKS. BUT, I NEED TO PROGRAM A DEAD TIME TO PREVENT 2 MOSFETS ARE IN STATE "ON" DURING THE COMMUTATION TO AVOID A DEAD SHORT OF THE SOURCE. I put that this dead time has to be of 60ns. It is to assure that (for example): when m1 pass from state "1" to "0" then count to 60ns and then (we are assured that m1 doesn't work) to active m2 '1'.
THE DELAY PART OF THE CODE IS NOT HERE. I DON'T KNOW HOW TO DO. IT SEEMS TO BE EASY BUT....THE condition "after" or "wait" is not permited because this code is for implementing and "after" and "wait" is only for simulation!!!
SOME HELP? THANK YOU VERY MUCH IN ADVANCE!!
entity controllerSource is
generic(timeM: integer:= 1000000); --20 ms (switching time between Mosfets)
generic(timeR: integer:= 3); --60 ns (delay to avoid being 2 MOSFETS in "on" state at the same time)
Port( clk : in std_logic;
rst : in std_logic;
m1: out std_logic; -- Mosfet HIGH side
m2: out std_logic); -- Mosfet LOW side
end entity;
architecture c1 of controllerSource is
signal counter: unsigned(23 downto 0);
signal cont: unsigned(23 downto 0);
signal y: std_logic;
begin
counter: process (clk, rst)
begin
if rst = '1' then
counter<=(others => '0');
cont<=(others => '0');
elsif (clk'EVENT and clk = '1') then -- 1 clock period each 50Mhz
counter<=counter+1;
cont<=cont+1;
if counter=timeM then -- 20ms
counter<=(others => '0');
end if;
if cont=tiempoR then -- 60ns
cont<=(others => '0');
end if;
end if;
end process;
commutation: process (clk, rst)
begin
if rst = '1' then
m1<='1';
m2<='0';
y<='0';
elsif (clk'EVENT and clk = '1') then
if counter=timeM then --every time that arrive to 20ms commute the state of mosfets
if y='0' then
y<='1';
m1<='0';
m2<='1';
else
y<='0';
m2<='0';
m1<='1';
end if;
end if;
end if;
end process;
end c1;
I AM A STUDENT AND I AM TRYING TO IMPLEMENT AN STATE MACHINE TO CONTROL A BUCK CONVERTER. IN THIS PART OF CODE, I AM TRYING TO COMMUTE 2 MOSFET (HIGH SIDE AND LOW SIDE). EACH 20ms MOSFET1 (m1) IS IN "ON" AND MOSFET1 (m2) IN "OFF" AND THEN REVERSE.
UP THIS POINT, THE CODE WORKS. BUT, I NEED TO PROGRAM A DEAD TIME TO PREVENT 2 MOSFETS ARE IN STATE "ON" DURING THE COMMUTATION TO AVOID A DEAD SHORT OF THE SOURCE. I put that this dead time has to be of 60ns. It is to assure that (for example): when m1 pass from state "1" to "0" then count to 60ns and then (we are assured that m1 doesn't work) to active m2 '1'.
THE DELAY PART OF THE CODE IS NOT HERE. I DON'T KNOW HOW TO DO. IT SEEMS TO BE EASY BUT....THE condition "after" or "wait" is not permited because this code is for implementing and "after" and "wait" is only for simulation!!!
SOME HELP? THANK YOU VERY MUCH IN ADVANCE!!
entity controllerSource is
generic(timeM: integer:= 1000000); --20 ms (switching time between Mosfets)
generic(timeR: integer:= 3); --60 ns (delay to avoid being 2 MOSFETS in "on" state at the same time)
Port( clk : in std_logic;
rst : in std_logic;
m1: out std_logic; -- Mosfet HIGH side
m2: out std_logic); -- Mosfet LOW side
end entity;
architecture c1 of controllerSource is
signal counter: unsigned(23 downto 0);
signal cont: unsigned(23 downto 0);
signal y: std_logic;
begin
counter: process (clk, rst)
begin
if rst = '1' then
counter<=(others => '0');
cont<=(others => '0');
elsif (clk'EVENT and clk = '1') then -- 1 clock period each 50Mhz
counter<=counter+1;
cont<=cont+1;
if counter=timeM then -- 20ms
counter<=(others => '0');
end if;
if cont=tiempoR then -- 60ns
cont<=(others => '0');
end if;
end if;
end process;
commutation: process (clk, rst)
begin
if rst = '1' then
m1<='1';
m2<='0';
y<='0';
elsif (clk'EVENT and clk = '1') then
if counter=timeM then --every time that arrive to 20ms commute the state of mosfets
if y='0' then
y<='1';
m1<='0';
m2<='1';
else
y<='0';
m2<='0';
m1<='1';
end if;
end if;
end if;
end process;
end c1;
↧
↧
Video IP, Frame Buffer, Triple Buffering, Frame Dropping
Hi.
I'm reading about Frame Buffer component in the triple buffering mode with frame dropping. In the Video IP manual[1], in the Triple Buffering section is written the following:
Why doesn't the component make the newly received frame clean and start writing into previously clean buffer? (Actually now when I'm writing this post I'm no longer sure why did I want it like that but it's what I would expect.) Is there any video processing or performance reason?
There seems to be no option to enable triple buffering in both Frame Buffer components (the basic one and the one supporting 4k) in Quartus Prime 15.1. There's only "Frame dropping" option which increases required memory by rougly one third so I assume this is the option that turns it on. Am I correct? The documentation is silent about this.
Thank you.
[1] UG-VIPSUITE, 2015.11.02
I'm reading about Frame Buffer component in the triple buffering mode with frame dropping. In the Video IP manual[1], in the Triple Buffering section is written the following:
Quote:
- If the spare buffer is already clean when the writer completes writing the current input frame:
- If dropping frames is allowedthe writer drops the newly received frame and overwrites its buffer with the next incoming frame.
There seems to be no option to enable triple buffering in both Frame Buffer components (the basic one and the one supporting 4k) in Quartus Prime 15.1. There's only "Frame dropping" option which increases required memory by rougly one third so I assume this is the option that turns it on. Am I correct? The documentation is silent about this.
Thank you.
[1] UG-VIPSUITE, 2015.11.02
↧
integer'image(some_int) results in "Expression is not constant" error
What is the correct way to convert an always changing integer variable to a string (to be displayed on a VGA monitor)? I have a series of if statements that take care of padding (so that the resulting string is always a certain length but as soon as I change:
to:
I get an "Expression is not constant" error. What is the correct way to convert an always changing integer variable (that could be any int within the integer limits) to a string?
Code:
resulting_string <= integer'image(87465);Code:
resulting_string <= integer'image(some_int_var);I get an "Expression is not constant" error. What is the correct way to convert an always changing integer variable (that could be any int within the integer limits) to a string?
↧
Video Out/VGA Display Skipping Every Other X Pixel
Hey, so I'm using a De1-SoC and programming in Assembly using the the Nios II instruction set found here: https://www.altera.com/content/dam/a...u_nii51017.pdf
So I was just experimenting with the video out pixel buffer (at memory located 0x8000000) and tried to create a screen that was just entirely white. I looped through each pixel and coloured each one white but I am getting vertical lines that are not being coloured in. I have provided pictures as well as screenshots of the documentation I used to create the image, my source code, and the output on my VGA monitor.
![]()
Vertical columns not being printed white
![]()
Video Out Documentation - 1
![]()
Video Out Documentation - 2
![]()
Video Out Documentation - 3
Any help is greatly appreciated! Cheers
So I was just experimenting with the video out pixel buffer (at memory located 0x8000000) and tried to create a screen that was just entirely white. I looped through each pixel and coloured each one white but I am getting vertical lines that are not being coloured in. I have provided pictures as well as screenshots of the documentation I used to create the image, my source code, and the output on my VGA monitor.
Any help is greatly appreciated! Cheers
↧
Endless trouble with HDMI output (Bitec IP core)
Good evening from Japan,
I'm having endless trouble getting HDMI output to work on my Arria10 ALARIC (ReflexCES) development board, Bitec HDMI output FMC card and Bitec HDMI IP core.
I'm generating a test image at 1920x1080 using Altera VIP IP and outputting it via a CVO to the HDMI IP core.
My pixel clock is running at 74.25MHz (1/2 x 148.5MHz) in TMDS 2-symbol mode, in order to output at a frame rate of 60Hz.
DVI compatibility mode is ON, scrambling and all other HDMI 2 features are OFF.
My transceivers are running at 3712.5MHz and I'm oversampling the data from the HDMI IP core to the transceivers 10 times to get the right clock rate.
The scope output for my clock signal (top) and red channel (bottom) below is the result:
![]()
In principle that looks alright to me, but..
When feeding the output into another development board with a Bitec HDMI RX core, the receiver PLL locks and I get a RX ready signal, but no image (via Quartus debug monitor).
If I connect directly to a monitor, I get no signal.
If I double the transceiver rate, I get a warning from my test display that I'm outputting at 120Hz, which is not supported.
Correct wiring and signal output of clock, r, g, b have been verified.
This is probably not enough information for anyone to find concisely what is wrong, but in case anyone has a hint or some experience with this, it is highly appreciated.
Also I was wondering, if maybe my base PLL clock generation is not accurate enough. E.g. as pixel clock I'm not generating exactly 74.25MHz, but rather 74.24Mhz. Is that off too much so that the monitor doesn't detect correct timing anymore?
Thank you,
Klaus
I'm having endless trouble getting HDMI output to work on my Arria10 ALARIC (ReflexCES) development board, Bitec HDMI output FMC card and Bitec HDMI IP core.
I'm generating a test image at 1920x1080 using Altera VIP IP and outputting it via a CVO to the HDMI IP core.
My pixel clock is running at 74.25MHz (1/2 x 148.5MHz) in TMDS 2-symbol mode, in order to output at a frame rate of 60Hz.
DVI compatibility mode is ON, scrambling and all other HDMI 2 features are OFF.
My transceivers are running at 3712.5MHz and I'm oversampling the data from the HDMI IP core to the transceivers 10 times to get the right clock rate.
The scope output for my clock signal (top) and red channel (bottom) below is the result:
In principle that looks alright to me, but..
When feeding the output into another development board with a Bitec HDMI RX core, the receiver PLL locks and I get a RX ready signal, but no image (via Quartus debug monitor).
If I connect directly to a monitor, I get no signal.
If I double the transceiver rate, I get a warning from my test display that I'm outputting at 120Hz, which is not supported.
Correct wiring and signal output of clock, r, g, b have been verified.
This is probably not enough information for anyone to find concisely what is wrong, but in case anyone has a hint or some experience with this, it is highly appreciated.
Also I was wondering, if maybe my base PLL clock generation is not accurate enough. E.g. as pixel clock I'm not generating exactly 74.25MHz, but rather 74.24Mhz. Is that off too much so that the monitor doesn't detect correct timing anymore?
Thank you,
Klaus
↧
↧
En5364qi
Hi,
I have used
EN5364QI for getting a 3.3V from 5V input, the schematic is attached. I see no voltage on Vout, may the problem be about the SS pin connected to GND?
Thanks for advance.
I have used
EN5364QI for getting a 3.3V from 5V input, the schematic is attached. I see no voltage on Vout, may the problem be about the SS pin connected to GND?
Thanks for advance.
↧
DE0-Nano-SoC Pin Location
Pin Information Setting
where is the full list???????![]()
where is the full list???????
↧
Expand Partition of Angtrom Linux on Altera Board
Hello All,
I am new to using Altera Board and have Angstrom Linux intalled on it.
Problem that I am facing :
1. I am trying to install python on the system, but gave me an error that "gcc" was not installed on the linux.
2. I proceeded with installation of "gcc" but it gave me an error that there was not sufficient space on the board. I have a 32 GB card so space issue was not a valid problem .
3. I searched the net and found that I need to expand the partition of the board and tried doing that but ended up deleting the partition and couldn't find any other way of doing so.
If anyone can give some pointers based on their experiences or have resolved such problem, then do let me know.
Thanks,
Aditya
I am new to using Altera Board and have Angstrom Linux intalled on it.
Problem that I am facing :
1. I am trying to install python on the system, but gave me an error that "gcc" was not installed on the linux.
2. I proceeded with installation of "gcc" but it gave me an error that there was not sufficient space on the board. I have a 32 GB card so space issue was not a valid problem .
3. I searched the net and found that I need to expand the partition of the board and tried doing that but ended up deleting the partition and couldn't find any other way of doing so.
If anyone can give some pointers based on their experiences or have resolved such problem, then do let me know.
Thanks,
Aditya
↧
Device "5CSEBA2u23C8S" does not support "channel PLL"(cyclone v se)
I use cycloneV chip (se, 5CSEBA2U23C8S)) to design a transceiver, FPGA clock input is used clk0p, can not be synthesised, the following error message.
11661 Design uses HSSI PLLs that are not supported in the seleted device.
11666 Device "5CSEBA2U23C8S" does not support "Channel PLL"
For this error, I tested, the cascade clock, use FPLL there are mistakes, what should I do?thanks
11661 Design uses HSSI PLLs that are not supported in the seleted device.
11666 Device "5CSEBA2U23C8S" does not support "Channel PLL"
For this error, I tested, the cascade clock, use FPLL there are mistakes, what should I do?thanks
↧
↧
Reset the fpga from Linux using /dev/mem/
Hello,
I'm building a project in Quartus II for my board DE1_SoC.
I created an IP and then connected it with HPS using Qsys via AXI4-lite interface, then, I launched Linux Yocto in HPS to program the FPGA.
I used dd or cat to the port /dev/fpga0 when programming the FPGA with my project.
Do I have to reset the FPGA part after programming using my method above?
In similar platform from Xilinx, I am able to reset the FPGA by sending a value to Register Reset.
Can I do that in Altera? For example by sending a certain value with /dev/mem in a program.
Anybody with similar experience is welcome to give his/her opinion.
Thanks a lot!
I'm building a project in Quartus II for my board DE1_SoC.
I created an IP and then connected it with HPS using Qsys via AXI4-lite interface, then, I launched Linux Yocto in HPS to program the FPGA.
I used dd or cat to the port /dev/fpga0 when programming the FPGA with my project.
Do I have to reset the FPGA part after programming using my method above?
In similar platform from Xilinx, I am able to reset the FPGA by sending a value to Register Reset.
Can I do that in Altera? For example by sending a certain value with /dev/mem in a program.
Anybody with similar experience is welcome to give his/her opinion.
Thanks a lot!
↧
Configuring Nallatech device settings
Hi,
Is it possible to set device settings such as CL_DEVICE_MAX_COMPUTE_UNITS for a given device? I am using Nallatech P385 D5. I would like to set the device information. Is this even possible?
Is it possible to set device settings such as CL_DEVICE_MAX_COMPUTE_UNITS for a given device? I am using Nallatech P385 D5. I would like to set the device information. Is this even possible?
↧
DE0-CV How to do "RUN" by EPCS64(POF file)
Hell,
I bega to use a DE0-CV (P0192) board (5CB4F2C7N).
I can programmed DE0_CV_Default.pof" to EPC64 on"PROG" mode by SW10 on the board.
Demo execute "RUN" mode by SW10 on the board.
In the same way,
I desiged original program, and I made the SOF and POF file.
The SOF file execut on"RUN" mode. It is the correct behavor.
Next,
I programmed POF file to EPCS64 on "PROG" mode, verify is Successful.
But, I can not execute it on "RUN" mode. It does not work at all.
I used Quatus2 13.1.
My questin is
When I generate a POF file, is it need a special setting or something add?
I want to run the original program on the DE0-CV board.
Please, I want to help.
kirari
I bega to use a DE0-CV (P0192) board (5CB4F2C7N).
I can programmed DE0_CV_Default.pof" to EPC64 on"PROG" mode by SW10 on the board.
Demo execute "RUN" mode by SW10 on the board.
In the same way,
I desiged original program, and I made the SOF and POF file.
The SOF file execut on"RUN" mode. It is the correct behavor.
Next,
I programmed POF file to EPCS64 on "PROG" mode, verify is Successful.
But, I can not execute it on "RUN" mode. It does not work at all.
I used Quatus2 13.1.
My questin is
When I generate a POF file, is it need a special setting or something add?
I want to run the original program on the DE0-CV board.
Please, I want to help.
kirari
↧
Universal Shift register help( in structrual)
Hi everyone!
I've got an assignment about writing the VHDL code for a universal shift register(using structural), and i was given a diagram of the circuit to replicate. So far I've made this, the only errors i'm getting is when i'm trying to display the outputs.
"Multi-source in Unit <Uni_reg> on signal <Qas>; this signal is connected to multiple drivers." (i get this error for all three outputs)
(i'm fairly new to vhdl, so any tip would help)
here's the code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Uni_reg is
port( LR,SP,clk,clear,shL,shR: in std_logic; -- shL = shift left shR= shift right
Da,Db,Dc : in std_logic; --inputs for load
Qa,Qb,Qc : out std_logic); --out puts from the flipflops
end Uni_reg;
architecture Structural of Uni_reg is
signal lr1,lr2,sp1,sp2,R1,R2,R3 : std_logic;
signal L1,L2,L3,LOAD1,LOAD2,LOAD3:std_logic;
signal c1,c2,c3 : std_logic;
signal Qas,Qbs,Qcs : std_logic;
component andgate
port(a,b,c : in std_logic; z : out std_logic);
end component;
component orgate
port(a,b,c : in std_logic; z : out std_logic);
end component;
component notgate
port(a: in std_logic; z : out std_logic);
end component;
component Dflipflop
port(D,clk: in std_logic; Q: out std_logic);
end component;
begin
NOTGATE1: notgate port map (LR,lr1);--1st notgate for LEFT/RIGHT
NOTGATE2: notgate port map (lr1,lr2);--2nd notgate for LEFT/RIGHT
NOTGATE3: notgate port map (SP,sp1);--1st notgate for SERIAL/PARRALLEL
NOTGATE4: notgate port map (sp1,sp2);--2nd notgate for SERIAL/PARRALLEL
ANDGATE1: andgate port map (shR,sp2,lr2,R1); --for right shift of 1st bit
ANDGATE2: andgate port map (sp2,lr1,Qbs,L1); --for left shift of 1st bit
ANDGATE3: andgate port map (lr2,sp1,Da,LOAD1);--for load of 1st bit
ANDGATE4: andgate port map (Qas,sp2,lr2,R2); --for right shift of 2nd bit
ANDGATE5: andgate port map (sp2,lr1,Qcs,L2); --for left shift of 2nd bit
ANDGATE6: andgate port map (lr2,sp1,Db,LOAD2);--for load of 2nd bit
ANDGATE7: andgate port map (Qbs,sp2,lr2,R3); --for right 3rd bit
ANDGATE8: andgate port map (sp2,lr1,shL,L3); --for left 3rd bit
ANDGATE9: andgate port map (lr2,sp1,Dc,LOad3);--for loading 3rd bit
ORGATE1: orgate port map (R1,L1,LOAD1,c1);--for the 1st flipflop
ORGATE2: orgate port map (R2,L2,LOAD2,c2);--for the 2nd flipflop
ORGATE3: orgate port map (R3,L3,LOAD3,c3);--for the 3rd flipflop
FLIPFLOP1: Dflipflop port map (c1,clk,Qas);
FLIPFLOP2: Dflipflop port map (c2,clk,Qbs);
FLIPFLOP3: Dflipflop port map (c3,clk,Qcs);
process(clk,clear)
begin
if clear ='1' then
Qas<='0';
elsif (clk'event and clk = '1') then
Qas<=Qas;
Qa <= Qas;
end if;
end process;
process(clk,clear)
begin
if clear ='1' then
Qbs<='0';
elsif (clk'event and clk = '1') then
Qbs<= Qbs;
Qb <= Qbs;
end if;
end process;
process(clk,clear)
begin
if clear ='1' then
Qcs<='0';
elsif (clk'event and clk = '1') then
Qcs<=Qcs;
Qc <= Qcs;
end if;
end process;
end Structural;
I've got an assignment about writing the VHDL code for a universal shift register(using structural), and i was given a diagram of the circuit to replicate. So far I've made this, the only errors i'm getting is when i'm trying to display the outputs.
"Multi-source in Unit <Uni_reg> on signal <Qas>; this signal is connected to multiple drivers." (i get this error for all three outputs)
(i'm fairly new to vhdl, so any tip would help)
here's the code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Uni_reg is
port( LR,SP,clk,clear,shL,shR: in std_logic; -- shL = shift left shR= shift right
Da,Db,Dc : in std_logic; --inputs for load
Qa,Qb,Qc : out std_logic); --out puts from the flipflops
end Uni_reg;
architecture Structural of Uni_reg is
signal lr1,lr2,sp1,sp2,R1,R2,R3 : std_logic;
signal L1,L2,L3,LOAD1,LOAD2,LOAD3:std_logic;
signal c1,c2,c3 : std_logic;
signal Qas,Qbs,Qcs : std_logic;
component andgate
port(a,b,c : in std_logic; z : out std_logic);
end component;
component orgate
port(a,b,c : in std_logic; z : out std_logic);
end component;
component notgate
port(a: in std_logic; z : out std_logic);
end component;
component Dflipflop
port(D,clk: in std_logic; Q: out std_logic);
end component;
begin
NOTGATE1: notgate port map (LR,lr1);--1st notgate for LEFT/RIGHT
NOTGATE2: notgate port map (lr1,lr2);--2nd notgate for LEFT/RIGHT
NOTGATE3: notgate port map (SP,sp1);--1st notgate for SERIAL/PARRALLEL
NOTGATE4: notgate port map (sp1,sp2);--2nd notgate for SERIAL/PARRALLEL
ANDGATE1: andgate port map (shR,sp2,lr2,R1); --for right shift of 1st bit
ANDGATE2: andgate port map (sp2,lr1,Qbs,L1); --for left shift of 1st bit
ANDGATE3: andgate port map (lr2,sp1,Da,LOAD1);--for load of 1st bit
ANDGATE4: andgate port map (Qas,sp2,lr2,R2); --for right shift of 2nd bit
ANDGATE5: andgate port map (sp2,lr1,Qcs,L2); --for left shift of 2nd bit
ANDGATE6: andgate port map (lr2,sp1,Db,LOAD2);--for load of 2nd bit
ANDGATE7: andgate port map (Qbs,sp2,lr2,R3); --for right 3rd bit
ANDGATE8: andgate port map (sp2,lr1,shL,L3); --for left 3rd bit
ANDGATE9: andgate port map (lr2,sp1,Dc,LOad3);--for loading 3rd bit
ORGATE1: orgate port map (R1,L1,LOAD1,c1);--for the 1st flipflop
ORGATE2: orgate port map (R2,L2,LOAD2,c2);--for the 2nd flipflop
ORGATE3: orgate port map (R3,L3,LOAD3,c3);--for the 3rd flipflop
FLIPFLOP1: Dflipflop port map (c1,clk,Qas);
FLIPFLOP2: Dflipflop port map (c2,clk,Qbs);
FLIPFLOP3: Dflipflop port map (c3,clk,Qcs);
process(clk,clear)
begin
if clear ='1' then
Qas<='0';
elsif (clk'event and clk = '1') then
Qas<=Qas;
Qa <= Qas;
end if;
end process;
process(clk,clear)
begin
if clear ='1' then
Qbs<='0';
elsif (clk'event and clk = '1') then
Qbs<= Qbs;
Qb <= Qbs;
end if;
end process;
process(clk,clear)
begin
if clear ='1' then
Qcs<='0';
elsif (clk'event and clk = '1') then
Qcs<=Qcs;
Qc <= Qcs;
end if;
end process;
end Structural;
↧
↧
sof2flash, elf2flash and bin2flash returning 255
sof2flash, elf2flash and bin2flash returns 255, without printing anything to stdout or stderr or doing anything useful for Quartus version 12.1 and 13.1 on my computer. I am running Quartus on OpenSuse 13.2 x86_64. Previous this was working and I do not think anything with the Quartus installation has changed, but I reinstalled Quartus 13.1 to be sure and I still get the same behavior. I also have version 15.1 installed and in that version the *2flash programs are working. I have done system updates to OpenSuse since last it was working. Do anyone know what may be wrong or how to further investigate the problem? Is it safe to use the *2flash programs from version 15.1 for projects using version 13.1 until this problem get resolved?
↧
Nios2-flash-programmer can't find EPCQ512 of Statix V
Hi,
I have a Statix V & EPCQ512 in my design,
the Nios(Gen2) image locating in the EPCQ @ offset 0x3000000
I've connected Altera Serial Flash Controller to the Nios.
the clock sink of the Flash controller is 20MHz (less than 25MHz as requested), and the Nios Processor is running on 110MHz. as shown below:
![]()
My Nios software locate in EPCQ offset 0x300000 and the vectors set to :
![]()
I've create JIC file with the follow settings:
![]()
When I'm Burning the EPCQ by using JIC, everything is Normal
the default bootloader of the Nios, copy the image from the EPCQ to the DDR and run the application, so far so good.
Now, I'm trying to burn only the Nios image in the EPCQ, for FW upgrade.
I'm using nios2-flash-programmer command line or Nios II Flash Programmer Tool.
I'm converting the elf to flash file by using:
elf2flash --input="D:/app.elf" --output="D:/app.flash" --boot="nios2eds/components/altera_nios2/boot_loader_cfi.srec" --base=0x10000000 --end=0x14000000 --reset=0x13000000 --verbose
and programming the the flash by using:
nios2-flash-programmer "D:/app.flash" --base=0x10000000 --accept-bad-sysid --device=1 --instance=0 '--cable=USB-Blaster on torenpc [USB-1]' --program --verbose
I'm getting the follow error: No CFI table found at address 0x10000000
Do I missing something?
I also follow the application note AN-736 (Nios II Processpr Bootoing From Serial Flash (EPCQ)
I have a Statix V & EPCQ512 in my design,
the Nios(Gen2) image locating in the EPCQ @ offset 0x3000000
I've connected Altera Serial Flash Controller to the Nios.
the clock sink of the Flash controller is 20MHz (less than 25MHz as requested), and the Nios Processor is running on 110MHz. as shown below:
My Nios software locate in EPCQ offset 0x300000 and the vectors set to :
I've create JIC file with the follow settings:
When I'm Burning the EPCQ by using JIC, everything is Normal
the default bootloader of the Nios, copy the image from the EPCQ to the DDR and run the application, so far so good.
Now, I'm trying to burn only the Nios image in the EPCQ, for FW upgrade.
I'm using nios2-flash-programmer command line or Nios II Flash Programmer Tool.
I'm converting the elf to flash file by using:
elf2flash --input="D:/app.elf" --output="D:/app.flash" --boot="nios2eds/components/altera_nios2/boot_loader_cfi.srec" --base=0x10000000 --end=0x14000000 --reset=0x13000000 --verbose
and programming the the flash by using:
nios2-flash-programmer "D:/app.flash" --base=0x10000000 --accept-bad-sysid --device=1 --instance=0 '--cable=USB-Blaster on torenpc [USB-1]' --program --verbose
I'm getting the follow error: No CFI table found at address 0x10000000
Do I missing something?
I also follow the application note AN-736 (Nios II Processpr Bootoing From Serial Flash (EPCQ)
↧
use printf in niosii
I can use "printf("Hello from Nios II!\n");" to print "Hello from Nios II!\n " when I run the code on FPGA board.
However when I try to print a int, the compiler(Eclipse) doesn't generate the elf file and there is a error...
How can i solve it?
However when I try to print a int, the compiler(Eclipse) doesn't generate the elf file and there is a error...
How can i solve it?
Code:
int test = 10;
printf("test = %d\n", test);↧