I am using ModelSim PE Student Edition 10.4. After launching the application when I double click a verilog file included in the current project to edit it, the application started to launch repeatedly. How to solve this. Can anybody help me out please.
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Problem with ModelSim
↧
Memory DDR3
Hello ,
The problem I have with DDR3 memory .I have Cyclone V and memory MT41K128M16-107 , it is an external system with a different processor .
With Semiconductor intellectual property core utilizes a block DDR3 . Dating I set parameters according to the Documentation.
PLL_REF_CLK - 100
MHzMemory clock speed - 300 MHz
PLL reference clock frequency - 100 MHz
Here I have a question I have a problem because I get the data from the frequency of 80 MHz , but Controller moments together draws me because waitrequest filled TO buffer .
I have to use FIFO with a record of 80 MHz and read to do a level of 45 MHz - then the IS OK.
mp_cmd_clk - set to 45 MHz .
Why I can not write / read at a frequency of 80 MHz ?
The problem I have with DDR3 memory .I have Cyclone V and memory MT41K128M16-107 , it is an external system with a different processor .
With Semiconductor intellectual property core utilizes a block DDR3 . Dating I set parameters according to the Documentation.
PLL_REF_CLK - 100
MHzMemory clock speed - 300 MHz
PLL reference clock frequency - 100 MHz
Here I have a question I have a problem because I get the data from the frequency of 80 MHz , but Controller moments together draws me because waitrequest filled TO buffer .
I have to use FIFO with a record of 80 MHz and read to do a level of 45 MHz - then the IS OK.
mp_cmd_clk - set to 45 MHz .
Why I can not write / read at a frequency of 80 MHz ?
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AES-256 Encryption and Decryption on ALTERA
Hi,
Is there any ALTERA device on which I can implement AES-256 algorithm?
Is there any ALTERA device on which I can implement AES-256 algorithm?
↧
Ds-5 debug on Arria 10 Reflex Alaric board.
Hi,
I appreciate that this my not be the right place for this post as its not technically an Altera product.
I did try Reflex first but they just said they do not support Bare-Metal development & pointed me back at Altera.
I have recently taken delivery of this board & I thought I'd start with a simple Bare-metal Hello World test.
I took the same project that I had used on the Arria V SOC but built using the aria-10dk-oc-ram-hosted.ld linker script.
I then updated the DS-5 debug config to use Arria 10 SOC/BareMetalDebug/Debug Cortex-A9 0.
On trying to load the image over the USB-Blaster I got the following error:
Stopping running target Altera - Arria 10 SoC on TCP:localhost on connection
Connected to running target Altera - Arria 10 SoC on TCP:localhost
Execution stopped in SVC mode at S:0xC0021788
S:0xC0021788 BX lr
cd "C:\Users\gnewman\Documents\DS-5 Workspace"
Working directory "C:\Users\gnewman\Documents\DS-5 Workspace"
Execution stopped in SVC mode at S:0xC0021788
S:0xC0021788 BX lr
loadfile "C:\Users\gnewman\Documents\DS-5 Workspace\Hello\Debug\Hello.axf"
Target Message: Memory access caused precise abort.
Debug Precise Abort Registers : DFSR = 0x00000817, DFAR = 0xFFE0AC00
ERROR(CMD16-TAD11-NAL18):
! Failed to load "Hello.axf"
! Failed to write 8 bytes to address S:0xFFE0AC00
! Bus error on memory operation.
set debug-from main
start
WARNING(CMD399-COR168):
! Failed to start the target
! No function named "main" could be found
WARNING(CMD407): Trying the entry point instead
ERROR(CMD426): Cannot find symbol to start or entrypoint, the file or load commands may be used to set the entrypoint
wait
In fact Ds-5 cant read any addresses in the oc-ram space.
On checking further the only memory I seem to be able to access is 0xC0000000 0xEF7EFFFF (HPS-to-FPGA).
Could this be a BootRom issue?
Any help would be gratefully received.
I appreciate that this my not be the right place for this post as its not technically an Altera product.
I did try Reflex first but they just said they do not support Bare-Metal development & pointed me back at Altera.
I have recently taken delivery of this board & I thought I'd start with a simple Bare-metal Hello World test.
I took the same project that I had used on the Arria V SOC but built using the aria-10dk-oc-ram-hosted.ld linker script.
I then updated the DS-5 debug config to use Arria 10 SOC/BareMetalDebug/Debug Cortex-A9 0.
On trying to load the image over the USB-Blaster I got the following error:
Stopping running target Altera - Arria 10 SoC on TCP:localhost on connection
Connected to running target Altera - Arria 10 SoC on TCP:localhost
Execution stopped in SVC mode at S:0xC0021788
S:0xC0021788 BX lr
cd "C:\Users\gnewman\Documents\DS-5 Workspace"
Working directory "C:\Users\gnewman\Documents\DS-5 Workspace"
Execution stopped in SVC mode at S:0xC0021788
S:0xC0021788 BX lr
loadfile "C:\Users\gnewman\Documents\DS-5 Workspace\Hello\Debug\Hello.axf"
Target Message: Memory access caused precise abort.
Debug Precise Abort Registers : DFSR = 0x00000817, DFAR = 0xFFE0AC00
ERROR(CMD16-TAD11-NAL18):
! Failed to load "Hello.axf"
! Failed to write 8 bytes to address S:0xFFE0AC00
! Bus error on memory operation.
set debug-from main
start
WARNING(CMD399-COR168):
! Failed to start the target
! No function named "main" could be found
WARNING(CMD407): Trying the entry point instead
ERROR(CMD426): Cannot find symbol to start or entrypoint, the file or load commands may be used to set the entrypoint
wait
In fact Ds-5 cant read any addresses in the oc-ram space.
On checking further the only memory I seem to be able to access is 0xC0000000 0xEF7EFFFF (HPS-to-FPGA).
Could this be a BootRom issue?
Any help would be gratefully received.
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Deo Nano Beginer problem
Dear All,
I am new to FPGA (also to vhdl), and altera deo nano is my first board.
I tried to generate pwm to some pins, and I generated 4 pwms using this core https://eewiki.net/pages/viewpage.ac...ageId=20939345
in my state machine I used something like this. (there are 4 in total, i showed one here)
----------------------------------------------------------------------
Motor1CCW_task2: pwm
GENERIC MAP(sys_clk => sys_clk1, pwm_freq=> pwm_freq1, bits_resolution => bits_resolution1, phases => phases1)
PORT MAP(clk => clk_main, reset_n => '1', ena => '1', duty =>"10000000" , pwm_out=> Motor1_CCW --, pwm_n_out => Motor1_CW
);
-------------------------------------------------------------------------
I used l293d ic to drive two motors. At the beginning, I able to change duty cycle and direction and motors. But after working for 30 min, the motors stared weird behavior and I noticed pwms are wrongly generated.
Now doing plenty of permutations I cant figure out what is going on. It seems some times, some pins not working. for example If I try to use GPIO_131 (k15) it seems broken and the attempt to use it also affect other pins. and also some pins cant generate pwm as expected. Again if i changed "Motor1_CCW" to different specific pins, it works.
---I changed to all unused pins as tri-stated
---the voltage level i selected 3.3 lvttl
Later I started with a new deo nano, the exact thing happened. works perfectly at the beginning and then started weird behavior. The motor circuit is simple and motors were run at 6 volt. I suspect that some pins of deo nano are broken both cases. But the control panel(deo_nano_controlpanel.exe) works perfectly for the boards.
Any suggestion?
Thank you very much
I am new to FPGA (also to vhdl), and altera deo nano is my first board.
I tried to generate pwm to some pins, and I generated 4 pwms using this core https://eewiki.net/pages/viewpage.ac...ageId=20939345
in my state machine I used something like this. (there are 4 in total, i showed one here)
----------------------------------------------------------------------
Motor1CCW_task2: pwm
GENERIC MAP(sys_clk => sys_clk1, pwm_freq=> pwm_freq1, bits_resolution => bits_resolution1, phases => phases1)
PORT MAP(clk => clk_main, reset_n => '1', ena => '1', duty =>"10000000" , pwm_out=> Motor1_CCW --, pwm_n_out => Motor1_CW
);
-------------------------------------------------------------------------
I used l293d ic to drive two motors. At the beginning, I able to change duty cycle and direction and motors. But after working for 30 min, the motors stared weird behavior and I noticed pwms are wrongly generated.
Now doing plenty of permutations I cant figure out what is going on. It seems some times, some pins not working. for example If I try to use GPIO_131 (k15) it seems broken and the attempt to use it also affect other pins. and also some pins cant generate pwm as expected. Again if i changed "Motor1_CCW" to different specific pins, it works.
---I changed to all unused pins as tri-stated
---the voltage level i selected 3.3 lvttl
Later I started with a new deo nano, the exact thing happened. works perfectly at the beginning and then started weird behavior. The motor circuit is simple and motors were run at 6 volt. I suspect that some pins of deo nano are broken both cases. But the control panel(deo_nano_controlpanel.exe) works perfectly for the boards.
Any suggestion?
Thank you very much
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ALT PLL Megawizard aborts
in qsys ALTPLL component aborts at starting.the component flashes in to qsys and then disappears.
I used it properly till yesterday.all of a sudden, ALT PLL is not opening in qsys. i tried re installing quartus subscription package.still it remains the same.
I used it properly till yesterday.all of a sudden, ALT PLL is not opening in qsys. i tried re installing quartus subscription package.still it remains the same.
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Multi-processor aoc compilation
I am currently compiling a rather hardware-intensive kernel. The compilation time just got over 24 hours and it is still running.
I know Quartus can use multiple processors when compiling, but when I look at the Windows task manager, I only see one processor with one core active.
Can I use multi-processor compilation only from Quartus' gui or is there a way to let it use multiple cores?
(I have Quartus set to use all available processors.)
I have read something about this here:http://www.alteraforum.com/forum/sho...ht=multithread,
but that did not help.
I know Quartus can use multiple processors when compiling, but when I look at the Windows task manager, I only see one processor with one core active.
Can I use multi-processor compilation only from Quartus' gui or is there a way to let it use multiple cores?
(I have Quartus set to use all available processors.)
I have read something about this here:http://www.alteraforum.com/forum/sho...ht=multithread,
but that did not help.
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ALTPLL not getting added
I am trying to create a new Qsys and i want to add "Avalon ALTPLL" to the Qsys .But i am not able to do so.
Its not allowing to edit or display any contents related to ALTPLL.Why is it so?
I am using Cyclone IV device .
Please suggest how to get rid of this.
Its not allowing to edit or display any contents related to ALTPLL.Why is it so?
I am using Cyclone IV device .
Please suggest how to get rid of this.
↧
ACP port setup
Hello guys,
Does somebody know how to setup the ACP port so I can use a FPGA master to access the SDRAM data with cache coherency?
I have a FPGA module which does something like a DMA transfer, I have it working by using the FPGA-SDRAM ports, but I would like to use the FPGA-HPS with the ACP port.
Someone told me to pass the RAM physical address of the data I want to handle "| 0x80000000" so I can access the ACP window, but after doing that I got a kernel panic,
I am not sure if I need to do some initial setup for that ACP port, the FPGA master module is connected via the FPGA-HPS bridge and I have changed the AW[AR] Cache attributes of the AXI port to enable the cache for both writes and reads.
I have a DE1-SoC boad, with Linux 3.10 LTSI, it was built using Yocto and a guide from rocketboards.org.
I am using some ideas from the project: http://rocketboards.org/foswiki/view/Projects/Datamover. There is an axi_conduit_merger module which allowed me to changes the AXI attributes from the Linux application.
Not sure what I am missing.
Any help would be appreciated.
Thanks.
Does somebody know how to setup the ACP port so I can use a FPGA master to access the SDRAM data with cache coherency?
I have a FPGA module which does something like a DMA transfer, I have it working by using the FPGA-SDRAM ports, but I would like to use the FPGA-HPS with the ACP port.
Someone told me to pass the RAM physical address of the data I want to handle "| 0x80000000" so I can access the ACP window, but after doing that I got a kernel panic,
I am not sure if I need to do some initial setup for that ACP port, the FPGA master module is connected via the FPGA-HPS bridge and I have changed the AW[AR] Cache attributes of the AXI port to enable the cache for both writes and reads.
I have a DE1-SoC boad, with Linux 3.10 LTSI, it was built using Yocto and a guide from rocketboards.org.
I am using some ideas from the project: http://rocketboards.org/foswiki/view/Projects/Datamover. There is an axi_conduit_merger module which allowed me to changes the AXI attributes from the Linux application.
Not sure what I am missing.
Any help would be appreciated.
Thanks.
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↧
differential DQS pin DDR3 in ARRIAV stater kit
I have a problem with the connection differential DQS pin for DDR3 in ARRIAV stater kit
after adding in the project bidir ALTIOBUF megafunction IP core differential mode I'm getting the below error message:
Error (15852): Output port "OBAR" of PSEUDO_DIFF_OUT primitive "altiobuf:altiobuf|altiobuf_iobuf_bidir_lnp:altiob uf_iobuf_bidir_lnp_component|pseudo_diffa_0" must drive only one OBUF primitive on the I port and cannot drive anything else
Error (21207): "OEBOUT" port of the single-ended output buffer "altiobuf:altiobuf|altiobuf_iobuf_bidir_lnp:altiob uf_iobuf_bidir_lnp_component|pseudo_diffa_0" is not connected
pin assigned correct
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to dqs[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to dqs[1]
set_location_assignment PIN_F23 -to dqs[1]
set_location_assignment PIN_F22 -to dqs[0]
set_location_assignment PIN_G23 -to "dqs[1](n)"
set_location_assignment PIN_G22 -to "dqs[0](n)"
How to solve this problem?
after adding in the project bidir ALTIOBUF megafunction IP core differential mode I'm getting the below error message:
Error (15852): Output port "OBAR" of PSEUDO_DIFF_OUT primitive "altiobuf:altiobuf|altiobuf_iobuf_bidir_lnp:altiob uf_iobuf_bidir_lnp_component|pseudo_diffa_0" must drive only one OBUF primitive on the I port and cannot drive anything else
Error (21207): "OEBOUT" port of the single-ended output buffer "altiobuf:altiobuf|altiobuf_iobuf_bidir_lnp:altiob uf_iobuf_bidir_lnp_component|pseudo_diffa_0" is not connected
pin assigned correct
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to dqs[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to dqs[1]
set_location_assignment PIN_F23 -to dqs[1]
set_location_assignment PIN_F22 -to dqs[0]
set_location_assignment PIN_G23 -to "dqs[1](n)"
set_location_assignment PIN_G22 -to "dqs[0](n)"
How to solve this problem?
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problem with simulation waveform editor
hello to everyone! i am a quartus II newbie. My first exercise on this program is to build an EXOR port. After having connected everything i started compilation which was succefully completed. After this i started simulation waveform editor and i create a waveform. Saved everithing and started a functional simulation. It cannot be finished due to two errors. IMPORTANT: i'm running quartus II on parallel Desktop because i have a Macbook pro and a 32bit win-7 pc which doesn't allow me to work with quartus II. Here attached the simulation flow progress:
Determining the location of the ModelSim executable...
Using: c:/altera/14.1/modelsim_ase/win32aloem/
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off uno -c uno --vector_source="//psf/Home/Desktop/università/Digilab/1/uno.vwf" --testbench_file="//psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.vwf.vt"
Info: ************************************************** *****************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
Info: Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, the Altera Quartus II License Agreement,
Info: the Altera MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Altera and sold by Altera or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Wed Mar 09 18:21:18 2016
Info: Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off uno -c uno --vector_source=//psf/Home/Desktop/università/Digilab/1/uno.vwf --testbench_file=//psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.vwf.vt
Warning (201007): Can't find port "y" in design
Warning (201005): Ignoring output pin "y" in vector source file when writing test bench files
Info (201000): Generated Verilog Test Bench File //psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.vwf.vt for simulation
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 599 megabytes
Info: Processing ended: Wed Mar 09 18:21:19 2016
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation --tool=modelsim_oem --format=verilog --output_directory="//psf/Home/Desktop/università/Digilab/1/simulation/qsim/" uno -c uno
Info: ************************************************** *****************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
Info: Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, the Altera Quartus II License Agreement,
Info: the Altera MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Altera and sold by Altera or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Wed Mar 09 18:21:20 2016
Info: Command: quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=//psf/Home/Desktop/università/Digilab/1/simulation/qsim/ uno -c uno
Info (204019): Generated file uno.vo in folder "//psf/Home/Desktop/università/Digilab/1/simulation/qsim//" for EDA simulation tool
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 603 megabytes
Info: Processing ended: Wed Mar 09 18:21:21 2016
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
**** Generating the ModelSim .do script ****
//psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
c:/altera/14.1/modelsim_ase/win32aloem//vsim -c -do uno.do
Reading C:/altera/14.1/modelsim_ase/tcl/vsim/pref.tcl
# 10.3c
# do uno.do
# ** Warning: (vlib-34) Library already exists at "work".
#
# Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
# Start time: 18:21:22 on Mar 09,2016
# vlog -work work uno.vo
# init_dbinfo() DATABASE ERROR: (sqlite3_open //psf/Home/Desktop/università/Digilab/1/simulation/qsim/work/_lib.qdb): unable to open database file
# mtilibWrite(): Unexpected null object encountered
# ** Fatal: (vlog-9) Problem while writing token file "//psf/Home/Desktop/università/Digilab/1/simulation/qsim/work/_temp/vlog9ttz2d".
#
# The system cannot find the path specified. (GetLastError() = 3)
# ** Error: uno.vo(32): Verilog Compiler exiting
# End time: 18:21:22 on Mar 09,2016, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0
# ** Error: c:/altera/14.1/modelsim_ase/win32aloem/vlog failed.
# Executing ONERROR command at macro ./uno.do line 3
Error.
Determining the location of the ModelSim executable...
Using: c:/altera/14.1/modelsim_ase/win32aloem/
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off uno -c uno --vector_source="//psf/Home/Desktop/università/Digilab/1/uno.vwf" --testbench_file="//psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.vwf.vt"
Info: ************************************************** *****************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
Info: Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, the Altera Quartus II License Agreement,
Info: the Altera MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Altera and sold by Altera or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Wed Mar 09 18:21:18 2016
Info: Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off uno -c uno --vector_source=//psf/Home/Desktop/università/Digilab/1/uno.vwf --testbench_file=//psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.vwf.vt
Warning (201007): Can't find port "y" in design
Warning (201005): Ignoring output pin "y" in vector source file when writing test bench files
Info (201000): Generated Verilog Test Bench File //psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.vwf.vt for simulation
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 599 megabytes
Info: Processing ended: Wed Mar 09 18:21:19 2016
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation --tool=modelsim_oem --format=verilog --output_directory="//psf/Home/Desktop/università/Digilab/1/simulation/qsim/" uno -c uno
Info: ************************************************** *****************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
Info: Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, the Altera Quartus II License Agreement,
Info: the Altera MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Altera and sold by Altera or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Wed Mar 09 18:21:20 2016
Info: Command: quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=//psf/Home/Desktop/università/Digilab/1/simulation/qsim/ uno -c uno
Info (204019): Generated file uno.vo in folder "//psf/Home/Desktop/università/Digilab/1/simulation/qsim//" for EDA simulation tool
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 603 megabytes
Info: Processing ended: Wed Mar 09 18:21:21 2016
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
**** Generating the ModelSim .do script ****
//psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
c:/altera/14.1/modelsim_ase/win32aloem//vsim -c -do uno.do
Reading C:/altera/14.1/modelsim_ase/tcl/vsim/pref.tcl
# 10.3c
# do uno.do
# ** Warning: (vlib-34) Library already exists at "work".
#
# Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
# Start time: 18:21:22 on Mar 09,2016
# vlog -work work uno.vo
# init_dbinfo() DATABASE ERROR: (sqlite3_open //psf/Home/Desktop/università/Digilab/1/simulation/qsim/work/_lib.qdb): unable to open database file
# mtilibWrite(): Unexpected null object encountered
# ** Fatal: (vlog-9) Problem while writing token file "//psf/Home/Desktop/università/Digilab/1/simulation/qsim/work/_temp/vlog9ttz2d".
#
# The system cannot find the path specified. (GetLastError() = 3)
# ** Error: uno.vo(32): Verilog Compiler exiting
# End time: 18:21:22 on Mar 09,2016, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0
# ** Error: c:/altera/14.1/modelsim_ase/win32aloem/vlog failed.
# Executing ONERROR command at macro ./uno.do line 3
Error.
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How to View GIC Registers in Debugger?
Hi!
Is there a way to view the General Interrupt Controller (GIC) registers in the debugger? They don't show up in the registers view.
Joachim
Is there a way to view the General Interrupt Controller (GIC) registers in the debugger? They don't show up in the registers view.
Joachim
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FIFO filling up after 2 writes
Hi,
I'm using a 32 bit FIFO set to show-ahead, to cross clock domains from a fast clock to a slower clock.
The FIFO is empty and i clock in two 32 bit words, i invert the rdempty signal and use this as the read request .However after the 2 word have been written to the FIFO the wrusedw indicates that the fifo now has 1023 words of data.
I have attached a screen shot of signal tap. The signaltap is clocked from the FIFO Write clock so the width of the signals are wrong but it shows the FIFO filling up.
any ideas to why this is happening?
![]()
I'm using a 32 bit FIFO set to show-ahead, to cross clock domains from a fast clock to a slower clock.
The FIFO is empty and i clock in two 32 bit words, i invert the rdempty signal and use this as the read request .However after the 2 word have been written to the FIFO the wrusedw indicates that the fifo now has 1023 words of data.
I have attached a screen shot of signal tap. The signaltap is clocked from the FIFO Write clock so the width of the signals are wrong but it shows the FIFO filling up.
any ideas to why this is happening?
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Design Unit Not Found
Hello all,
I'm still trying to get my *first* simulation running with ModelSim, and my progress is quite limited. I think I have my license issues worked out finally, after talking directly to Altera support.
Currently, I am trying to run simulations on my project, but am getting errors. whenever I try to simulate anything (right click on module in my work dir and select simulate), I get the following:
I found a lot of threads with similar problems, but haven't figure out the solution. I am not sure where the library for 'altpll' is. I do have a huge list of libraries in the library pane. Is there an easy way to know what library my cores are from? Once I figure out what library altpll is in, when do I use the include directory command? Should that go in my .do file? Not a single one of my modules will simulate- I am using:
ROM: 1-Port
LPM_COUNTER
ALTDIDO_OUT
ALTPLL
I am using a Stratix IV device.
Sorry if this is a very easy question to answer, I have never used this tool (or hardly any Altera tools) before. Right now, I have nothing set up and working. I'd like to get to the point where I have a testbench.
Thank you,
FrenchyRaoul
I'm still trying to get my *first* simulation running with ModelSim, and my progress is quite limited. I think I have my license issues worked out finally, after talking directly to Altera support.
Currently, I am trying to run simulations on my project, but am getting errors. whenever I try to simulate anything (right click on module in my work dir and select simulate), I get the following:
Code:
ModelSim> vsim work.TX_PLL# vsim work.TX_PLL
# Start time: 17:52:30 on Mar 09,2016
# Loading work.TX_PLL
# ** Error: (vsim-3033) D:/Users/Nicholai/Desktop/Research/QuartusII/March2016/DACSimulation/TX_PLL.v(75): Instantiation of 'altpll' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TX_PLL File: D:/Users/Nicholai/Desktop/Research/QuartusII/March2016/DACSimulation/TX_PLL.v
# Searched libraries:
# D:/Users/Nicholai/Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/rtl_work
# Error loading design
# End time: 17:52:31 on Mar 09,2016, Elapsed time: 0:00:01
# Errors: 1, Warnings: 0ROM: 1-Port
LPM_COUNTER
ALTDIDO_OUT
ALTPLL
I am using a Stratix IV device.
Sorry if this is a very easy question to answer, I have never used this tool (or hardly any Altera tools) before. Right now, I have nothing set up and working. I'd like to get to the point where I have a testbench.
Thank you,
FrenchyRaoul
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Vertical White Lines problem on Altera NEEK (Video tutorial)
I am a beginner with FPGA's and have a lot of software engineering experience. By following the Altera VIP tutorial http://www.alterawiki.com/wiki/Alter...mo_on_the_NEEK I encountered a problem.
My LCD screen shows a black screen with vertical white lines in it. This is the case with the .flash files and also if I generate and build the qsys system myself.
Anyone knows why it shows white/black vertical stripes? I am expecting to see my video input or at least a blue screen.
My LCD screen shows a black screen with vertical white lines in it. This is the case with the .flash files and also if I generate and build the qsys system myself.
Anyone knows why it shows white/black vertical stripes? I am expecting to see my video input or at least a blue screen.
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Can't create a VHDL file in Quartus
Hi,
I have been trying to create a VHDL file for block diagram. The project compiles without problems, but when trying to create a HDL file for current file it shows an error. Hence I cannot progress further since I can't create symbol form file either.
![]()
Here is the screenshot of my file with errors.
Could someone help me please?
Thank you
Tom
I have been trying to create a VHDL file for block diagram. The project compiles without problems, but when trying to create a HDL file for current file it shows an error. Hence I cannot progress further since I can't create symbol form file either.
Here is the screenshot of my file with errors.
Could someone help me please?
Thank you
Tom
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how to pass a pointer or array name to the interrupt function?
hi
i register a interrupt in nios, and it works well
alt_ic_isr_register (NIOS_FT245_INTERFACE_0_IRQ_INTERRUPT_CONTROLLER_I D,
NIOS_FT245_INTERFACE_0_IRQ,
ft245_interrupt,
NULL,
NULL);
i want to pass a pointer or array name to the interrupt function ft245_interrupt, how can i do it?
thanks!
i register a interrupt in nios, and it works well
alt_ic_isr_register (NIOS_FT245_INTERFACE_0_IRQ_INTERRUPT_CONTROLLER_I D,
NIOS_FT245_INTERFACE_0_IRQ,
ft245_interrupt,
NULL,
NULL);
i want to pass a pointer or array name to the interrupt function ft245_interrupt, how can i do it?
thanks!
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Stratix V Native Phy
Hi all
i'm working on "Transceiver Signal Integrity Development Kit" with strativ V GX.
i'v already worked with 10Gbase-R Transceiver phy with no problem, and i tested my design with an Ethernet analyzer Device.
but i need to use Native Phy in PMA Direct mode, to use the line data for mapping in another protocol.
in first step i tried to loop the rx data to tx data, to test the design with Ethernet analyzer, but it doesn't work, when tx data rate is 10Gbit/s, the rx data rate is approx. 8Gbit/s. indeed, rx data rate is always less than tx data rate.
something is wrong, but i can't understand what is.
i'v studied all altera documents about Transceivers and i'v reviewed the altera online training in this field.
has anybody no idea about that.
i can present more details about my design in case of need. even attach the project here.
thanks a lot
i'm working on "Transceiver Signal Integrity Development Kit" with strativ V GX.
i'v already worked with 10Gbase-R Transceiver phy with no problem, and i tested my design with an Ethernet analyzer Device.
but i need to use Native Phy in PMA Direct mode, to use the line data for mapping in another protocol.
in first step i tried to loop the rx data to tx data, to test the design with Ethernet analyzer, but it doesn't work, when tx data rate is 10Gbit/s, the rx data rate is approx. 8Gbit/s. indeed, rx data rate is always less than tx data rate.
something is wrong, but i can't understand what is.
i'v studied all altera documents about Transceivers and i'v reviewed the altera online training in this field.
has anybody no idea about that.
i can present more details about my design in case of need. even attach the project here.
thanks a lot
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How to know the code size ?!
hey mates
My questions are :
I need to use the OnCMemo for another purpose so I should know the space occupied by the code !
How do I know my code size after building ?
How to know the beginning and end @ of the code downloaded in the OnCMemo?
thnx
My questions are :
I need to use the OnCMemo for another purpose so I should know the space occupied by the code !
How do I know my code size after building ?
How to know the beginning and end @ of the code downloaded in the OnCMemo?
thnx
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How to Define the slow part of my code ?
Hey
I am coding using niosII 13.0 web edition ... Obviously I need to optimize the execution time in the end in order to define the part that will be reconsidered HW.
So how can I know the time of every part or function of my code ?!:confused:
thnx
I am coding using niosII 13.0 web edition ... Obviously I need to optimize the execution time in the end in order to define the part that will be reconsidered HW.
So how can I know the time of every part or function of my code ?!:confused:
thnx
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