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Decimal Point on Seven Segment Display for DE2-115

March 12, 2016, 1:40 am
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Hi everyone,

On the DE2-115 development board's 8 7-segment-displays, there are decimal points. There are, however, no FPGA pin numbers to access these decimal points--at least I can't find them when looking at pages 37-39 of the DE2_115_User_manual.pdf

Does anyone using this board know if it is possible to turn the decimal points on the seven-segment-displays on and off?

Thanks very much,
Nate
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altera cyclonevgt dev kit license

March 12, 2016, 5:26 am
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Hi to all.
In the Development Kit Edition (DKE) cyclonevgt are included licenses for ip megacore?(fir, crc, ethernet,dspbuilder,fft... and others?)
Where can i find informations of the feautures included in the license?
Regards
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Connection between Cyclone III with ATXmega or HC series logic device

March 12, 2016, 11:43 am
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Hello
I'd like to connectCyclone III FPGA with ATXmega, powered with 3.3V (data bus). I have two questions:


1. Can i connect it directly or i have to use resistor or bus transceiver (for example74HC245)?


2. I saw a schematic ofCyclone III DE0 development board. There is a connection betweenbuttons and cyclone through 74HC245 bus transceiver. 74HC245 isconnected to cyclone through 120 Ohm resistor. Is this resistor necessary?


With regards
L.
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EDS QSPI programming problem

March 12, 2016, 8:38 pm
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Hi, i’m using my custom Cyclone V SoC(5cseba5u19i7n) board in combination with QSPI flash (Micron 512Mbit).
I want to program the NOR flash via USB blaster with SoC EDS Command Shell version 15.0.

When I start up the “SoC EDS Command Shell version 15.0”and type “quartus_hps.exe –c 1 –o PV ”.

After programming done ,I get the following
"1.send_access_data() error while accessing DP Register. 2.Debug Port Read Buffer reading failure, read_dp_buff() error while accessing AP Register.3.Failed to READ ACCESS to the Physical Reg. 4. Failed to read MPU Module Reset Register."
I was wondering the JTAG was not nomally working.

Thank you.
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Can't use testbench in Modelsim - error loading design

March 13, 2016, 12:25 am
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Hi everyone,

First I want to say that I searched all the threads here, and while this is a common problem, I could not figure out how to solve it.

I am trying to use a small testbench I wrote using the Quartus testbench template writer, but I am getting this error:
Code:
** Error: (vsim-3170) Could not find 'C:/Users/nettek/QuartusProjects/Final Project - 11.3.16 - par/test/simulation/modelsim/rtl_work.tb_test1'.
#
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./Test_run_msim_rtl_vhdl.do PAUSED at line 14
Steps I took:
1. Created a BDF file with two components in it, obviously it has input/output ports and some internal signals.
2. Created an HDL file from the BDF file. Added it to project. Removed the BDF file from project (did not delete it).
3. Created a testbench using the Quartus template writer.
4. Added the VHT file to project.
5. Took to Assignments -> Settings -> EDA tool settings -> Simulation ->
Chose compile test bench and chose the VHT file.
6. Tools -> Run simulation tool -> RTL simulation which opened Modelsim.

Of course I always made sure to compile whenever I needed to.

I don't understand this problem, just two days ago it didn't happen and now it does. What could be the problem?

Also, I would appreciate if you could tell me how to test internal signals of a BDF file in Modelsim using a testbench. I know that I can give the signals names, turn the BDF file into a HDL file and then compile it in Modelsim, and then force the signals, but I want to use a testbench to make this be automatic. Problem is, using a testbench, I only see the input/outputs.

Thank you!
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Have any tool can check bottleneck of AOCL?

March 13, 2016, 1:33 am
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I want use lookup table to enhance performance. Like the following example,

myCos = cos(); ---------Converted into--------> myCos = checkLutCos();

Change original cosine function into check Lut, but “Performance does not improve”,

Even if Converted cos() into constant zero

myCos = cos(); ---------Converted into--------> myCos = 0;

also not improve

So I think this cosine function isn't in bottleneck.Have any tools can see bottleneck of AOCL?
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how to connect FPGA to bluetooth module

March 13, 2016, 4:18 am
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hi, i need some help here. well i'am doing my final year project, i'am going to do a wireless communication between FPGA and a bluetooth module using an android application, i'am wondering how can i implement this,i can't get any idea can you help me please (i'am using altera de2 fpga). a point i want to add i won't to add either arduina or pic microcontroller i want another solutions
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Strange Large IC delay in CycloneV

March 13, 2016, 7:19 am
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Hi, community,
I am using 5CGTFD5C5F27C7 in my project to receive synchronous data from a 12-bit ADC.
the data rate is 480Mbps, for i need to use dynamic io delay to compensate for the fixed delay caused by ADC itself, i could not use ALTLVDS_RX core.
so I instantiated DDIO_IN ip core to latch data from ADC with 240MHz clock.

For CycloneV FPGA, DDIO_IN is directly implemented in its IOE unit and it is great.

After Fittting, TQ reported timing violation.
I checked the data arrival path and found that there was a large IC delay(3.452ns) caused by signal routing from IOE to LAB.
I made serial-to-parralel conversion in LAB unit.

In order to decrease such a large IC delay, i use logiclock feature to constrain the LAB to be adjacent to the relevant IOE.
In fact, the LAB and the relevant IOE are next to each other after constraintion.
However, after fitting, TQ still reported timing violation and the large IC delay was still there(around 3.4ns)!

This is interesting, for two physically adjacent unit would have such a large IC delay, i do not know the way Quartus routing signal, but it looks unreasonable to me.

i think 3.4ns is a large delay in nowadays design, especailly in a 28-nm FPGA.
I basically think that Quartus should prevent that large IC delay, even after TQ has reported that violation(i think it is what timing-driven synthesis should do).

Please help, how can i decrease such a large IC delay in CycloneV?
Even put them physically together won't help? I am puzzled, or did i miss something obvious?

Best Wishes,
ingdxdy
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Ability to quickly integrate IPs in OpenCL

March 13, 2016, 9:58 am
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hello,

I'm MESSELKA Mohamed Student at University Polytechnic of Valencia, I'm working on my final project and I need a document about ''Ability to quickly integrate IPs in OpenCL'' to insert a Verilog Code in OpenCL, so please I need your help to write my memory and I hope you will contact me as soon as possible, my email: m14m@live.fr.


thank you in advance.


kind regards
MESSELKA Mohamed
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any way to workaround "Error deleting "msim_transcript": permission denied problem?

March 13, 2016, 7:24 pm
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I'm new at Altera products. When I'm writing a code in Quartus-II, I'm constantly re-writting and testing, after making a correction in the code I launch Modelsim simulator but then I'm forced to closed it, then re-writting code in Quartus-II and launch Modelsim again, and again and again.

Otherwise I receive the windows warning, Nativelink Error: "msim_transcript" Permission denied. Check the NativeLink log file.

What is the solution or workaround for this?

ANOTHER QUESTION: I sometimes want to try an Idea over a current project code which is already working good, is there any way to "save the game" option, so I can freely mess with the code without consequences? What I do in this case is to create a totally new project and copy-page the code which is cumbersome.
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Interfacing of Modelsim and MATLAB

March 14, 2016, 2:57 am
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I am trying to interface MATLAB 2012b 32 bit with Modelsim PE student edition 10.4a.
When I am writing vsim in MATLAB command window it is showing following error.

Error using hdlsim/l_GetModelSimLibInfo (line 527)
Could not find ModelSim executable vsim. Make sure that ModelSim is installed on this
machine and its executables are on the system path.


Error in hdlsim (line 123)
libInfo = l_GetModelSimLibInfo;


Error in vsim (line 106)
hdlsim(pvpairs{:});

My Modelsim is working properly when I am using it with different code only the interfacing is not working.I have also added Modelsim in my system path. Please tell me what to do with this.
Thanks and regards.
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Image processing on altera de2_70 interfacing with trdb_d5m camera

March 14, 2016, 3:08 am
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Hi,
I am doing my final year project on DE2-70 to capture the real time image and trying to implement various image processing techniques.I have captured the image using TRDB-D5M camera but I don't know to set photo taking mode and to save the image. Please guide me.
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High Bandwidth LVDS interface with Altera Dev. Kits

March 14, 2016, 4:30 am
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Hi,

I would like to connect 16 ADCs with LVDS interface to FPGA. Each ADC will use 600Mbps data rate. I am looking for a development kit that is capable of handling this much data. Also I need at least 2GB RAM for continuous data acquisition. I check datasheets of Arria 10 and V FPGAs they all have support 1.6Gbps data rate for LVDS. They have at least 120 LVDS pairs.

Q: 1.6Gbps is total bandwidth or each individual LVDS can handle this much speed?

I also checked development kits for Arria boards I couldn't find information about how many LVDS pairs are available for interfacing. Datasheets states that It has LVDS but for chip to chip communication between 2 FPGA pairs inside Board.

Q: My question is which FPGA Dev. Kit of Altera suitable for interfacing this much (16) LVDS pairs and each of them will consume 600Mbps data rate? Also board should have fast enough memory interface to collect data (2GB).


I checked many of Altera's solutions and confused about it. I have experience with FPGA but never with this much requirements.


Kind Regards,
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In-system memory content editor cannot read/write to RAM

March 14, 2016, 4:51 am
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The In-system memory content editor cannot read or write a RAM that was instantiate for the IP core library.
The RAM (altsyncram) concerns a single port configuration. Read and write commands from other (own) blocks is going well, but the content editor gives a depth of 0 addresses of the RAM.

I have already added the default parameter: CYCLONEIV_SAFE_WRITE RESTRUCTURE, but it didn't work out anything.

In the RTL and technology viewer, the RAM block is connected to the JTAG logic.

Used soft- and hardware:
Quartus II Version 14.1.0 Build 186 12/03/2014 SJ web edition
DE0-nano / FPGA: EP4CE22F17C6

VHDL code:
Code:
altsyncram_component : altsyncram
    GENERIC MAP (
        clock_enable_input_a => "BYPASS",
        clock_enable_output_a => "BYPASS",
        intended_device_family => "Cyclone IV E",
        lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=RAM",
        lpm_type => "altsyncram",
        numwords_a => 32,
        operation_mode => "SINGLE_PORT",
        outdata_aclr_a => "NONE",
        outdata_reg_a => "UNREGISTERED",
        power_up_uninitialized => "FALSE",
        read_during_write_mode_port_a => "DONT_CARE",
        widthad_a => 5,
        width_a => 8,
        width_byteena_a => 1
    )
    PORT MAP (
        address_a => address,
        clock0 => clock,
        data_a => data,
        wren_a => wren,
        q_a => sub_wire0
    );
Anyone an idea why I cannot read/write with the in-system memory content editor?
Thank you in advance,

Rutger
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How to call external library with OpenCL on FPGA?

March 14, 2016, 9:42 am
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Hi,
I have existing program which is computation intensive. That is why I want to try with FPGA using OpenCL for acceleration.
The program is my computations are all done through certain libraries such as MKL, LAPACK/ARPACK.
How do I call these libraries through OpenCL? Is it possible? Any suggestion?

Thank you!!
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Timing Analysis Report

March 14, 2016, 10:50 am
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I have done a static timing analysis using TimeQuest Timing Analyzer for 100 MHz clock frequency for my design. I have got the following reports:

  1. Info (332140): No Setup paths to report
  2. Info (332140): No Hold paths to report
  3. Info (332140): No Recovery paths to report
  4. Info (332140): No Removal paths to report
  5. Info (332146): Worst-case minimum pulse width slack is 3.889

Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 3.889 0.000 clk




What does it means? Does my design meets the clock requirement of 100 MHz?
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QSys doesn't create all output files during generation

March 14, 2016, 5:00 pm
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I'm trying to build system for DE0_Nano board using Qsys (QuartusII, 11.1 SP2).
System preparation and generation by Qsys are passed without errors,
but Quartus Analysis&Elaboration give fatal errors (12006):
Node instance "XX" instantiates undefined entity "DE0_N_QSys_XX"
only for some included entities.
More details below.

Project setting:
Device: Cyclone IV E device EP4CE22F17C6;
Files : ProjDir/Test_0 // Top-Level entity
ProjDir/DE0_N_QSys/synthesis/DE0_N_QSys.qip
/DE0_N_QSys.v
/submodules/......


System consist of the following components:
1. clock Source (nameed as clk_50)
2. Nios II/e CPU (cpu)
3. JTAG UART (jtag_uart)
4. On-Chip Memory RAM (onchip_memory2)
5. System ID (sysid)
6. Parallel i/O [7:0] (led) //8 LED's
7. Parallel I/o [3:0] (sw) //4 switches
8. Parallel I/o [1:0] (key) //2 keys

Qsys generation passed with 0 errors and 2 warnings:
Warning: system: "No matching role found for jtag_uart:avalon_jtag_slave:dataavailable (dataavailable)"
Warning: system: "No matching role found for jtag_uart:avalon_jtag_slave:readyfordata (readyfordata)"


After creating the system named as DE0_N_QSys and closing Qsys Quartus starts Analysis&Elaboration.
Everything going smoothly but then errors appear:
Error: Quartus II 32-bit Analysis & Elaboration was unsuccessful. 5 errors, 5 warnings
Error: Peak virtual memory: 311 megabytes
Error: Processing ended: Mon Mar 14 23:50:20 2016
Error: Elapsed time: 00:00:47
Error: Total CPU time (on all processors): 00:00:09
Error (12006): Node instance "sw" instantiates undefined entity "DE0_N_QSys_sw"
Shortly (the same for all 5 errors (12006)):
1. sw -> "DE0_N_QSys_sw"
2. onchip_memory2 -> "DE0_N_QSys_onchip_memory2"
3. led -> "DE0_N_QSys_led"
4. key -> "DE0_N_QSys_key"
5. jtag_uart -> "DE0_N_QSys_jtag_uart"


Looking at directory DE0_N_QSys/synthesis/submodules, corresponding verilog files
(DE0_N_QSys_sw.v,...) are missing. I gues that is reason of errors.


Even using Demontration example from CD included in development Terasic DE0-Nano board, if I recompile it,
the same situation happens.


Please, help me to solve this problem of undefined entity!
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Wrong logic synthesis when call function named .

March 14, 2016, 7:19 pm
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I am in trouble in VHDL analyze & synthesis.

I use "Quartus Prime Verion 15.1.0 Build 185 10/21/2015 SJ Lite Edition".

It defines the no argument function in the package.

sample.vhd
Code:
library ieee;
use    ieee.std_logic_1164.all;
package Sample is
    subtype  Code_Type  is std_logic_vector(3 downto 0);
    function  New_Code_0 return Code_Type;
    function  New_Code_1 return Code_Type;
    function  New_Code_2 return Code_Type;
    function  New_Code_3 return Code_Type;
end Sample;
package body Sample is
    function  New_Code_0 return Code_Type is begin
        return std_logic_vector'("0001");
    end function;
    function  New_Code_1 return Code_Type is begin
        return std_logic_vector'("0010");
    end function;
    function  New_Code_2 return Code_Type is begin
        return std_logic_vector'("0100");
    end function;
    function  New_Code_3 return Code_Type is begin
        return std_logic_vector'("1000");
    end function;
end Sample;
I call no-argment function by <package_name>.<function_name>

sample_ng.vhd
Code:
library ieee;
use    ieee.std_logic_1164.all;
use    ieee.numeric_std.all;
use    work.Sample;
entity  Sample_NG is
    port (CLK: in  std_logic;
          CLR: in  std_logic;
          O  : out Sample.Code_Type
    );
end    Sample_NG;
architecture RTL of Sample_NG is
    signal count : integer range 0 to 3 := 0;
begin
    process(CLK) begin
        if (CLK'event and CLK = '1') then
            if (CLR = '1' or count >= 3) then
                count <= 0;
            else
                count <= count + 1;
            end if;
        end if;
    end process;
    O <= Sample.New_Code_3 when (count = 3) else
        Sample.New_Code_2 when (count = 2) else
        Sample.New_Code_1 when (count = 1) else
        Sample.New_Code_0;
end RTL;
Analyze & Synthesis

Code:
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
    Info: Processing started: Tue Mar 15 00:50:13 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 0020 -c sample_ng
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 2 design units, including 1 entities, in source file sample_ng.vhd
    Info (12022): Found design unit 1: Sample_NG-RTL
    Info (12023): Found entity 1: Sample_NG
Info (12021): Found 2 design units, including 0 entities, in source file sample.vhd
    Info (12022): Found design unit 1: Sample
    Info (12022): Found design unit 2: Sample-body
Info (12127): Elaborating entity "sample_ng" for the top level hierarchy
Warning (10873): Using initial value X (don't care) for net "O" at sample_ng.vhd(8)
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "O[0]" is stuck at GND
    Warning (13410): Pin "O[1]" is stuck at GND
    Warning (13410): Pin "O[2]" is stuck at GND
    Warning (13410): Pin "O[3]" is stuck at GND
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 2 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "CLK"
    Warning (15610): No output dependent on input pin "CLR"
Info (21057): Implemented 6 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 2 input pins
    Info (21059): Implemented 4 output pins
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Peak virtual memory: 870 megabytes
    Info: Processing ended: Tue Mar 15 00:50:38 2016
    Info: Elapsed time: 00:00:25
    Info: Total CPU time (on all processors): 00:00:56
Why "warning(10873): Using initial value X (don't care) for net "O" at sample_ng.vhd(8)" ???

As a result , the output signals(O) are all connected to GND.

I think this is a bug in the logic synthesis , how about you do you think ?
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How to hide structure of a DSP Builder model

March 14, 2016, 8:00 pm
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Hi guys.

I am trying to hide a subsystem that is constructed by DSP Builder Advanced Blockset.

Does anyone have any good ideas?
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Pipe to quartus_asm broken but process still running, terminating quartus_asm

March 15, 2016, 12:38 am
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Hi,

I am facing a issue while running a design on QUARTUS 15.0 version.

The error comes after the assembler stage while compiling the design. Following is the log -


Info: Total CPU time (on all processors): 00:13:54
Info: ************************************************** *****************
Info: Running Quartus II 64-Bit Assembler
Info: Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Info: Processing started: Mon Mar 14 17:40:52 2016
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off system -c system
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 7081 megabytes
Info: Processing ended: Mon Mar 14 17:42:34 2016
Info: Elapsed time: 00:01:42
Info: Total CPU time (on all processors): 00:01:41
Error (112002): Pipe to quartus_asm broken but process still running, terminating quartus_asm
Error (293007): Current module quartus_asm ended unexpectedly
------------------------------------------------
ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.

while executing
"execute_flow -compile"
(file "synthesis_tcl.tcl" line 21)
------------------------------------------------
Error (23031): Evaluation of Tcl script synthesis_tcl.tcl unsuccessful
Error: Quartus II 64-Bit Shell was unsuccessful. 3 errors, 122 warnings
Error: Peak virtual memory: 935 megabytes
Error: Processing ended: Mon Mar 14 17:42:37 2016
Error: Elapsed time: 00:09:04
Error: Total CPU time (on all processors): 00:15:03


PS - there is enough memory space and OS used is linux.

Any help would be worth.

Regards,
Anmag
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