Linux LXDE updates

March 15, 2016, 2:22 am

≫ Next: Expression has 8 elements, but must have 9 elements, and also, else null

≪ Previous: Pipe to quartus_asm broken but process still running, terminating quartus_asm

hi,
I'm still a newbie with Linux and the DE1-Soc. I'm running the "normal" version of Linux/LXDE: Linaro 13.04, quantal, Linux 3.12
The first problem is one I already solved: had to update /etc/apt/sources.list from
ports.ubunto.com/ubuntu-ports/ quantal main universe
to
old-releases.ubuntu.com/Ubuntu/ quantal main universe

Running the normal "apt-get update" fixed the immediate issue. Now I am attempting to load several PPAs, but am somewhat stumped by the "missing" add-apt-repository command by:
# apt-get install add-apt-repository
I get the error of "Unable to locate package add-apt-repository

Since the only way I know how to add a PPA is add-apt-repository, I am somewhat stuck. I see Linaro Maintainers overlay ppa at: ppa:linaro-maintainers/overlay but cannot figure out how to install it.

Many thanks!
Steve

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Expression has 8 elements, but must have 9 elements, and also, else null

March 15, 2016, 3:14 am

≫ Next: How can I generate time limited sof file?

≪ Previous: Linux LXDE updates

Hi,

I have this variable, X, which is an std_logic_vector(8 downto 0).
I have inputs A,B,C which are std_logic_vector(7 downto 0). Also, a signal D which is also std_logic_vector(7 downto 0).
I also have a signal Z which is std_logic_vector(7 downto 0).

I need to add all the inputs and the signal into X and invert, so:

Code:

X := not(A+B+C+D);

At the end, I need to take the lower byte of X, so:

Code:

Z <= (X'length-2 downto 0);

I am getting an error with the X variable, but I'm not sure why. I understand that they both have different sizes, but when adding all these inputs/signals, it is very possible that due to the addition X will grow to 9 bits (maybe even more, thinking about it).

Anyway to solve this problem?

And a completely unrelated question... if I do something like:

Code:

if (condition) then

     do something;

else null;

Does it make the design more efficient/better or is it redundant and it's best to not use an else at all and just end the if statement?

Thanks!

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How can I generate time limited sof file?

March 15, 2016, 7:24 am

≫ Next: Memory type for variables

≪ Previous: Expression has 8 elements, but must have 9 elements, and also, else null

Hi,
My design is not uses cores without licence, but I need to generate "time limited" file to demonstrate. Can I do it?

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Memory type for variables

March 15, 2016, 7:34 am

≫ Next: SOC CyV ARM and ethernet connection

≪ Previous: How can I generate time limited sof file?

I am modifying the sobel example to find out how to describe the behaviour I want of the system/program. The sobel example has a shift register that holds some of the pixels to be processed. When I change

Code:

<type> rows[<size>]

Code:

<type> local rows[<size>]

I get a kernel that is too large to compile. I am doing further tests on performance but this caused me to wonder about the memory types the variables are stored in. I know global resides in external ram and local in on-chip ram, but what about the variables that have no memory-space identifier (if this is the correct term) as the first piece of code?

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SOC CyV ARM and ethernet connection

March 15, 2016, 7:58 am

≫ Next: New Fitter Error

≪ Previous: Memory type for variables

i've TERASIC NANO/ATLAS DE0 KIT,

how can i assume a connection to send UDP data packets from FPGA throught HPS ETHERNET connecion?

Ethernet PHy is connected to HPS, no to FPGA.

some approach?
I'm using LINUX NANO IMAGE, "POKY" with framebuffer.
Thanks.

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New Fitter Error

March 15, 2016, 8:44 am

≫ Next: Seriallite II C2C Issue

≪ Previous: SOC CyV ARM and ethernet connection

Hi!

I develop a DSP project on Terrasic DE1 board based on Cyclone V GX. My project occupies something about 50% of resources.

I added some functions and got a fitter error during compilation:

Error (170025): Fitter requires that more entities of type LAB be placed in a region than are available in the region
Error (170026): Region "lower-left" corner: X1_Y9; Region "upper-right" corner: X25_Y34

And the reason for this is "bitslip" net from control block to gigabit transceivers (the transceiver control module was designed a few monthes ago and worked well).

Basing on google and altera I tried to solve the error by setting the as GLOBAL SIGNAL in assignment editor, but it was't succesfull.

Thanks for helping me!

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Seriallite II C2C Issue

March 15, 2016, 8:52 am

≫ Next: Gated clocks

≪ Previous: New Fitter Error

Hi,

I'm working on setting up the seriallite II ip to send data collected on one FPGA to another on the arria v dual FPGA development board. I have a transmitting seriallite core on one FPGA and a receiving one on the other, they are sending and receiving data in streaming mode. The transmitting core seems to be working correctly, however the receiving core doesn't lock onto the incoming data (rx_is_lockedtoref does not get asserted). Any idea why this lock is not being established? I've attached some waveforms and rtl viewer screenshots to this message.

Regards,
Arash

Attached Images

rx_post_reset.jpg (20.6 KB)
tx_post_reset.PNG (19.2 KB)

Attached Files

tx_rtl.pdf (25.0 KB)
rx_rtl.pdf (20.7 KB)

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Gated clocks

March 15, 2016, 9:05 am

≫ Next: I get a big noise when I echo the audio data from microphone

≪ Previous: Seriallite II C2C Issue

Hi folks. I have noticed in an Altera help page that gated clocks are not recommended:
-----> http://quartushelp.altera.com/15.1/i...f_gatedclk.htm
In another page, Altera provides guidelines for implementing a gated clock:
-----> http://quartushelp.altera.com/15.1/i...ules_clock.htm
It seems convenient to do this for generating a SPI clock, for example, using the chip select signal as a clock enable. Is there a better alternative? Here are my code and resulting RTL snapshot for reference.
This example incorporates both methods outlined in the help page.
Any comments greatly appreciated!

Code:

clock_enable_n : process(clk, reset_n)

begin

  if (reset_n = '0') then

    clk_enable_n    <= '0';

  elsif rising_edge(clk) then

    clk_enable_n    <= clock_en_n;

  end if;

end process clock_enable_n;

clock_out_n    <= clk or clk_enable_n;





clock_enable : process(clk, reset_n)

begin

  if (reset_n = '0') then

    clk_enable      <= '0';

  elsif falling_edge(clk) then

    clk_enable      <= not(clock_en_n);

  end if;

end process clock_enable;

clock_out  <= clk and clk_enable;

Attached Images

gated_clock.jpg (89.0 KB)

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I get a big noise when I echo the audio data from microphone

March 15, 2016, 10:25 am

≫ Next: Can't Recognize USB Blaster II - Quartus 13 Programmer

≪ Previous: Gated clocks

I designed a audio system in Qsys. I read the fifo data from the microphone input and write it to the audio write fifo. Although I can hear the microphone echo, it also generate a very big noise. I can't figure out why it will generate so much noise. Dose anyone have any idea why it is happened? I am not sure the setting of the audio codec is correct or not. Another problem is that how can I generate the sound with specific frequency?

I think the design in Qsys is correct. I generate the correct clock frequency to the audio and av_config core. I am using de2-115 board.

I use these functions :
alt_up_audio_read_fifo
alt_up_audio_write_fifo

Here is my c code to achieve the echo system.

Code:

int main(){

    alt_up_audio_dev * audio_dev = alt_up_audio_open_dev ("/dev/audio");

    alt_up_av_config_dev* av_config_dev = alt_up_av_config_open_dev("/dev/audio_and_video_config");





    /* used for audio record/playback */

    unsigned int l_buf ;

    unsigned int r_buf ;





    // initialize the audio core

    alt_up_av_config_write_audio_cfg_register(av_config_dev, 0x00, 0b000011000);

    alt_up_av_config_write_audio_cfg_register(av_config_dev, 0x01, 0b000011000);

    alt_up_av_config_write_audio_cfg_register(av_config_dev, 0x02, 0b000111100);

    alt_up_av_config_write_audio_cfg_register(av_config_dev, 0x03, 0b000111100);

    alt_up_av_config_write_audio_cfg_register(av_config_dev, 0x04, 0b000010100);

    alt_up_av_config_write_audio_cfg_register(av_config_dev, 0x05, 0b000000110);

    alt_up_av_config_write_audio_cfg_register(av_config_dev, 0x06, 0b000000000);

    alt_up_av_config_write_audio_cfg_register(av_config_dev, 0x07, 0b001001101); 

    alt_up_av_config_write_audio_cfg_register(av_config_dev, 0x08, 0b000000000);

    alt_up_av_config_write_audio_cfg_register(av_config_dev, 0x09, 0b000000001);









    while(1)

    {

            // read audio buffer

            alt_up_audio_read_fifo (audio_dev, &(r_buf), 80, ALT_UP_AUDIO_RIGHT);

            alt_up_audio_read_fifo (audio_dev, &(l_buf), 80, ALT_UP_AUDIO_LEFT);





            // write audio buffer

            alt_up_audio_write_fifo (audio_dev, &(r_buf), 80, ALT_UP_AUDIO_RIGHT);

            alt_up_audio_write_fifo (audio_dev, &(l_buf), 80, ALT_UP_AUDIO_LEFT);

        }

    }

}

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Can't Recognize USB Blaster II - Quartus 13 Programmer

March 15, 2016, 11:15 am

≫ Next: Serial Console Connection for Arria 10

≪ Previous: I get a big noise when I echo the audio data from microphone

Sometimes when I use the Programmer on the Quartus II v13, it does not recognize the USB Blaster II cable. It just states No Hardware. When I go to the pull-down menu, the USB Blaster II cable is not on the list. However, the Window software recognize the cable. I read there were problems in version 11. Are there problems in v13.? Sometimes rebooting work. Others times pulling the cable out of the USB port and putting it back in helps. I need it to be consistent because when I try to program a part, It comes back as Device Not Found. Even when the Programmer does recognize the Blaster, it still say Device Not Found. When it doesn't work, I don't know if it is the hardware or the software.

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Serial Console Connection for Arria 10

March 15, 2016, 11:38 am

≫ Next: Quartus License

≪ Previous: Can't Recognize USB Blaster II - Quartus 13 Programmer

I am trying to run a Linux kernel on the Arria 10 GX Dev Kit with a console window though a serial connection and I don't know how to connect it. I have a UART in my Qsys system to allow for communication between the host computer and the board but I'm not sure which pins to connect to allow data movement out of and into the FPGA fabric. Is it possible to reroute the NIOS Linux kernel console to the system console that is used by the NIOS II command shell?

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Quartus License

March 15, 2016, 12:13 pm

≫ Next: Quartus freezes when compiling and compilation takes very long.

≪ Previous: Serial Console Connection for Arria 10

Hi,

How can I get the evaluation license for Quartus?

I need evaluation Quartus License for Stratix V(5) GX devices.

I don't see any option in Altera Web Site for Evaluation Licences for Stratix V devices.

Thanks and best regards,

↧

Quartus freezes when compiling and compilation takes very long.

March 15, 2016, 4:08 pm

≫ Next: Cyclone V SX SoC Development Board serial for HPS

≪ Previous: Quartus License

Quartus II, which has worked perfectly up to now, started freezing for some minutes every time I click the compile button.
The compilation, after un-freezing, also takes ca 6 instead of 3 minutes. The performance seemed to plunge after I started
using SignalTap II in the project, although it seemed fine at first. The overall performance has also been degraded.

Is there any way of clearing cache or similar?

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Cyclone V SX SoC Development Board serial for HPS

March 15, 2016, 8:08 pm

≫ Next: about reset vector address

≪ Previous: Quartus freezes when compiling and compilation takes very long.

Hi,
I have a couple of Cyclone V SX SoC Development Board. 5CSXFC6D6F31C6N The one with the LED display.

I am using the 15.1 SOC install with the blasterii usb to serial with windows 7.
I have successfully ported apps etc to the arm linux with ds-5 with the gnu gcc cross compiler.
I am trying to get 4 serial channels to talk to an app on the arm9 processor but for now I would like to just get 1. I would like to stay on the HPS but if I have to go to the FPGA and quartus prime I guess thats ok.
I noticed that there are no devices /dev/a_16550_uart_0,1.
I am using the stock install that comes on the ssd card.
I see a sample app in the Embedded Peripherals IP User Guide for a loopback serial.
I saw the example in the ds-5 arm cross compiler the uart 16550 that creates a hwlib.xfe and a u-boot-spl.xfe when I run the hwlib.xfe it segment faults probably because the devices are missing. Is the u-boot-spl.xfe a u-boot.img? I am guessing not because the format of the file looks different.
I ran the bsp-editor and recompiled the preloader and u-boot but the serial was already checked.
I did a lsmod and the only module was altera-something.
So is the uart the best approach for the serial?
How do I get it into the bsp-editor and linux to include this device?
Thanks,
Piglet

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about reset vector address

March 16, 2016, 12:31 am

≫ Next: Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU example

≪ Previous: Cyclone V SX SoC Development Board serial for HPS

hi everybody

I want to know If I debug use the JTAG , does the reset vector address have any influence ? I set the reset vector address on ext flash.
where do the code start to run ？

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Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU example

March 16, 2016, 1:58 am

≫ Next: Is it necessary to exit a kernel in order to transfer data to host?

≪ Previous: about reset vector address

Hello.
I am engaged in software development for the ARM core board Cyclone V SoC Development Kit. I am interested in an example of Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU, which loads firmware FPGA from DMA and launches baremetall application on ARM (FPGA toogle LEDs). This project is built using Makefile. In turn, we have made the project among DS-5, setting all options for the assembly of the Makefile, and copying everything you need to build the source code into a single folder. In the original example declares two external variables:
extern char _binary_soc_system_dc_rbf_start;
extern char _binary_soc_system_dc_rbf_end;
they point to the compressed firmware file for FPGA soc_system_dc.rbf. But this advertisement, we never found ourselves variables _binary_soc_system_dc_rbf_start and _binary_soc_system_dc_rbf_end. The original example is compiled and in debug mode works well. Can you clarify how these variables can be properly used in our project. Thank you.

My project:

Attached Files

blink_fpga.zip (766.9 KB)

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Is it necessary to exit a kernel in order to transfer data to host?

March 16, 2016, 3:57 am

≫ Next: Cyclone V PLLs don't lock

≪ Previous: Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU example

Hello everyone!

I recently got my hands on an OpenCL board and so far it's been really nice to work with it.

Question: I want to send regular updates up to the host and down to the kernel, while my kernel is still running (it runs in an infinite loop). For sending data up to the host, I've found that the only way is to have two "communication kernels" which take data from my "infinite loop kernel" by using channels, and write to a global memory buffer. When the buffer is full, the "communication kernel" exits, which the host can see this event and proceeds to read from the global buffer. In this time, the second "communication kernel" starts filling its own buffer.

Writing to the kernel involves the host filling up a buffer, and starting a "host-to-FPGA-kernel" which passes the data to the "infinite kernel" through a channel.

Is this the only way to have host to running kernel communications? It seems like a very clumsy system, but I guess it could work.

Happy coding!
Monstrumus

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Cyclone V PLLs don't lock

March 16, 2016, 3:57 am

≫ Next: OpenCL SDK 15.0 not opening

≪ Previous: Is it necessary to exit a kernel in order to transfer data to host?

Hello,
we are developing a board with 2 Cyclone V FPGA

5CEBA4F23C7N
5CGXBC4C6F27C7N

at the moment we have 3 copies of the board produced in december and 3 copies produced in october.

None of the board have all PLLs working. The number of PLLs that lock vary from board to board and moreover PLLs that lock on one board don't lock on another one. We are this issues on both FPGA.

Originally the power supply was provided by switching regulators. The measured power noise was in the limit of +-5% of the 2.5V rail. Now we disconnected all switching power supply and replaced with linear power supply but nothing change.

One of the four PLLs of the 5CEBA4F23C7N starts to lock if we set the bandwidth to high.

The clock is generated by a 50MHz 3.3v oscillator 50R terminated close to the FPGA PIN.

The clocks generated by the locked PLLs have a stong jietter.

We are looking for a solution. We can not redesign the board without understanding where is the problem

Thanks

↧

OpenCL SDK 15.0 not opening

March 16, 2016, 6:23 am

≫ Next: Comparison between old value and new value

≪ Previous: Cyclone V PLLs don't lock

I have downloaded 15.0 FPGA design and SDK for openCL.
Istallation process done, but just quartus is working and for OpneCL SDK terminal open for a second and close by it self. I am not able to open it.
anyone can help me?:(

↧

Comparison between old value and new value

March 16, 2016, 6:49 am

≫ Next: qsys-script hangs forever

≪ Previous: OpenCL SDK 15.0 not opening

Hi All,

Its a very simple question but I am unable to do that. Below is my code. I want to store signal data_o_new to signal data_o_old and then compare these signals with each other and do increment or decrement until these two signals become same. data_o_new is coming from an ip. Please help me... thanks

Architechture starts here:
Begin

data_o_old <= data_o_new;
data_o <= data_o_old;

fading: PROCESS(clk)
Begin
if rising_edge(clk) then
if data_o_new > data_o_old then
data_o_old <= data_o_old + 1;
elsif data_o_new < data_o_old then
data_o_old <= data_o_old - 1;
else
data_o_old <= data_o_new;
end if;
end if;
end process;

end Architecture;

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