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GPIO on LTC for de0_nano_soc and sockit

March 17, 2016, 12:35 pm
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Hi,

I need a GPIO point accessible by a pin (that I can hang a scope probe onto) that is connected to the HPS. I need this on both the de0_nano_soc and sockit boards.

I thought I found such a pin on the LTC connector. On the de0 it is signal HPS_LTC_GPIO shown coming into Bank 7C, HPS_GPIO40 on the schematic.

I've used the Linux GPIO user space interface successfully to toggle the HPS_LED (HPS_GPIO53) and read HPS_KEY (HPS_GPIO54) signals on the board. For example, to toggle the LED:

# cd /sys/class/gpio
# echo 222 > export
# cd gpio222
# echo "out" > direction
# echo 1 > value # LED ON
# echo 0 > value # LED OFF


If I try the same thing with HPS_LTC_GPIO (GPIO40 - which maps to gpio209), and then measure the pin on the LTC connector, the voltage does not change (low milli-volts).

It looks like all the gpio ports are enabled in my device tree (the LED, KEY, and LTC_GPIO are on the same port anyway so if the LED and KEY work, would expect the LTC_GPIO to work too).

I've also tried to configure the pin as an input and connected it (through a resistor) to both 3.3v and GND and the input state doesn't change...


Can anybody suggest what I'm missing??

Thanks,
--George Broz

Moog Industrial Group
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Example showing multiple compute units providing speedup

March 17, 2016, 2:51 pm
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Hi,


Is there an example of a kernel that performs better with the use of multiple compute units? I have experimented on various kernels, the simplest of all is a floating point multiplication of an array of double precision floats. I haven’t obtained any kernel that actually improves in terms of execution time from __attribute((num_compute_units(N))). My profiler tells me that my global memory bandwidth is severely affected after using this OpenCL attribute but my access patterns aren’t too complex. Does Altera have a working example of a kernel that benefits from multiple compute units? Has anyone gotten it to work before? Appreciate any feedback or examples that show performance benefits from __attribute((num_compute_units(N))).


This is an example of what I tried to run on AOCL. This code’s global memory access is 2200MB/s with a single compute unit. When I use two compute units, my bandwidth drops to 480MB/s. Why is there such a vast difference?


__attribute__((num_compute_units(CU)))
__kernel void vector_add(__global double * restrict x)
{
// get index of the work item
int id = get_global_id(0);
x[id] = x[id] * x[id];
}


I have tried the SIMD option, which improves performance, but I want to test the performance of multiple compute units, which thus far has been unsuccessfully.
Would appreciate a simple and straightforward working example to build/investigate on.

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SD Card DE2I150

March 17, 2016, 3:57 pm
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What is the Clockmargin?

March 17, 2016, 6:17 pm
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Hi all,

I am a new Quartus and DSP Bulder User. And I want to ask a simple question.
When using DSP Builder Advaned Blokst , we shold set 'Clock Margin(MHz)' that is in a 'Signals' Block.
But, I don't know what it is. Please tell me the meaning of the 'Clock Margin(MHz)'.

Thank you for reading my funny English !
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Gate Level Simulation Error

March 17, 2016, 6:27 pm
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Hi all, I have written some code for a basic and gate with a test bench, which works just fine when I run it in the RTL simulation, however whenever I try and run it in the Gate Level simulation I keep getting these error:

Loading work.tb_and_4bit
# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".
# No such file or directory. (errno = ENOENT)
# Loading work.and_4bit
# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) 4bit_ALU_7_1200mv_0c_slow.vo(74): Instantiation of 'cycloneive_io_obuf' failed. The design unit was not found.
# Region: /tb_and_4bit/DUT
# Searched libraries:
# c:\altera\90\modelsim_ase\altera\verilog\altera
# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".
# No such file or directory. (errno = ENOENT)
# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work
# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work
# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work
# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) 4bit_ALU_7_1200mv_0c_slow.vo(84): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found.
# Region: /tb_and_4bit/DUT
# Searched libraries:
# c:\altera\90\modelsim_ase\altera\verilog\altera
# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".
# No such file or directory. (errno = ENOENT)
# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work
# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work
# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work
# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) 4bit_ALU_7_1200mv_0c_slow.vo(94): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found.
# Region: /tb_and_4bit/DUT
# Searched libraries:
# c:\altera\90\modelsim_ase\altera\verilog\altera
# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".
# No such file or directory. (errno = ENOENT)
# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work
# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work
# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work
# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) 4bit_ALU_7_1200mv_0c_slow.vo(111): Instantiation of 'cycloneive_lcell_comb' failed. The design unit was not found.
# Region: /tb_and_4bit/DUT
# Searched libraries:
# c:\altera\90\modelsim_ase\altera\verilog\altera
# ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver".
# No such file or directory. (errno = ENOENT)
# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work
# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work
# C:\Users\simon\Documents\Uni Year2\alu_4bit\simulation\modelsim\gate_work
# Error loading design

I have the cyclone_iv library's downloaded and installed.

Many thanks.
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Can't use 'numeric_std_unsigned' package in Quartus prime lite edition v15.1

March 17, 2016, 10:42 pm
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I'm using quartus prime lite edition v15.1, trying to write a register file in vhdl. In my code i need to use ' numeric_std_unsigned' package, but an error pops up saying :
Quote:
Error (10481): VHDL Use Clause error : design library "IEEE" does not contain primary unit "NUMERIC_STD_unsigned". Verify that the primary unit exists in the library and has been successfully compiled.
I checked VHDL'08 in compiler settings but the error is still there.I think that quartus prime has incomplete support for VHDL'08 and i cann't use some packages

So, It'd be great help if any one can tell me what to do to be able to use 'numeric_std_unsigned' package.

Here's my code:

Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std_unsigned.all;


 entity regfile is

 port(        clk: in STD_LOGIC;
              regwrite: in STD_LOGIC; 
              rs, rt, rd: in STD_LOGIC_VECTOR(1 downto 0);
              data_in: in STD_LOGIC_VECTOR(15 downto 0);
              rd1, rd2: out STD_LOGIC_VECTOR(15 downto 0));
 end;


 architecture behave of regfile is type registerFile is
    array (3 downto 0) of STD_LOGIC_VECTOR(15 downto 0);
    signal registers: registerFile;

 begin
 process(clk) begin

    if rising_edge(clk) then
      if regwrite='1' then
      registers(to_integer(rd)) <= data_in;
      end if;
    end if;
 end process;
 
process(all)
 begin
      if (to_integer(rs)=0)
        then rd1 <= X"0000";
          else rd1 <= registers(to_integer(rs));
    end if;


  if (to_integer(rt)=0)
    then rd2 <= X"0000";
    else rd2 <= registers(to_integer(rt));
  end if;
 end process;


end;
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[Configuration Related] Cyclone III AP Configuration

March 18, 2016, 12:17 am
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Dear Host,
I am designing Cyclone III EP3C120 Board. On this board, i am configuring FPGA with AP configuration. In this configuration, i am using Micron P33 Parallel NOR Flash Memory.I will program the configuration through JTAG interfacing.
For VCCIO banks 1,6,7 and 8, i will use 3.3V.

Please provide additional information, if necessary.

Regards,
Mohsin Hayat
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Slip Ring Timing Recovery, PLL Question

March 18, 2016, 7:16 am
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I'm working on the design of a rotating camera whose frame valid and pixel clock go through slip rings. We've found that there can be glitches ranging from 10 ns to 10 us on both signals. The processor peripheral that the camera interfaces to can not handle abnormal (dropped) clock signals, so the signals have to contact the exact number of pixels / line and lines / frame else the video will be corrupted. One thought was to have a small FPGA use a PLL to maintain the 10.519 MHz clock, even if the pixel clocked dropped out for 10 us. Since frame valid could also have glitches, we could just use the first rising edge on frame valid to start internal counting and just count the PLL's output clock to recreate frame valid and generate a line valid.




I created a project based around a MAX10, added an ALTPLL module, set up the PLL for source synchronous mode (so 10 bits of camera data would be phase synchronized with the PLL clock), and added a 12 MHz oscillator as a secondary clock that the PLL could use to (at least I hoped) generate the 10.519 MHz output if the PLL couldn't maintain lock on the pixel clock. Unfortunately, when I simulated this, it behaved nothing like I expected. I don't know how well the simulation attachment will show up, but what I end up getting is just the inclk1 input on the PLL output all the time.

My assumptions are clearly wrong about what the PLL can do, so I'd appreciate any recommendations on the best way to solve this problem. Thanks in advance for the help.
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CVO II and genlock

March 18, 2016, 8:26 am
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I have a video processor design built using the VIP suite and everything is working as expected using a free-running CVO clock. However, my attempts to genlock the CVO to an external pll do not seem to be working.

I'm using the CVO II module and I have enabled the "Accept Synchronization Outputs" parameter in the qsys GUI. The CVO clock is derived from an external PLL and the PLL also provides a top of frame (TOF) signal which I have attached to the CVO SOF input and the CVO SOF_LOCKED input has been tied high. I have written 0x0019 to the CVO control register (Go bit, Enable Sync Output, Enable Frame Lock).

The CVO generates valid video but I do not see any attempt to align the output frame with the SOF input signal. The Status register reads 0x0005 - the frame locked bit never changes.

What am I missing here?

Michael
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Slip Ring Timing Issue, MAX10 PLL Problem

March 18, 2016, 8:29 am
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I'm working on the design of a rotating camera whose frame valid and pixel clock go through slip rings. We've found that there can be glitches ranging from 10 ns to 10 us on both signals. The processor peripheral that the camera interfaces to can not handle abnormal (dropped) clock signals, so the signals have to contact the exact number of pixels / line and lines / frame else the video will be corrupted. One thought was to have a small FPGA use a PLL to maintain the 10.519 MHz clock, even if the pixel clocked dropped out for 10 us. Since frame valid could also have glitches, we could just use the first rising edge on frame valid to start internal counting and just count the PLL's output clock to recreate frame valid and generate a line valid. (See clock recovery attachment)

I created a project based around a MAX10, added the ALTPLL, set up the PLL for source synchronous mode (so 10 bits of camera data would be phase synchronized with the PLL clock), and added a 12 MHz oscillator as a secondary clock that the PLL could use to (I hoped) generate the 10.519 MHz output if the PLL couldn't maintain lock for 10 us if the pixel clock went away. Unfortunately, when I simulated this, it behaved nothing like I expected. I don't know how well the simulation attachment will show up, but what I end up getting is just the inclk1 input on the PLL output all the time.

My assumptions are clearly wrong about what the PLL can do, so I'd appreciate any recommendations on the best way to solve this problem. Thanks in advance for the help.
Attached Images
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The expected Stdout device name does not match the selected target byte stream device

March 18, 2016, 10:44 am
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I've been working on a project using Quartus and we've been getting this error (The expected Stdout device name does not match the selected target byte stream device name.) in the 'Run Configurations' for a while now. We are not sure what's going wrong. We have recompiled and regenerated everything. We have also made sure STDOUT is selected in the settings. Has anyone had this error before or any suggestions what might be wrong? :cry:
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LVDS Rx/Tx Issue

March 18, 2016, 11:34 am
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I need to interface a TI's time measuring unit (TMU) THS788 with an FPGA to get data from this TMU. The TMU has LVDS serial peripheral interface. It has Data (16 bit valid data, 1 start bit to indicate following valid data, and 2 end bits to indicate end of valid data), Clock (min speed 75MHz), and Strobe. All these signals are LVDS. Data is transmitted at the rising edge of Clock and when Strobe is logic 0. Its a classic SPI with LVDS standards. I wish to use a dedicated State Machine to read the data serially and put it in a register. I wish to possibly use the mega function ALTLVDS_Rx. I d not have a target FPGA, wish to use a small one (Max/cyclone). If this is possible, I request some directions to figure this out. I am back in this type of design after sometime. I am versed in Verilog, and have Quartus II 12.1. My development PC has no internet connection.

I will also need to develop similar interface for serial Tx module to command THS788.

Thank you for your help.
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How to set to 0 value unconnected input pin?

March 18, 2016, 2:49 pm
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Hi!

In my design, some FPGA inputs could be left unconnected. But the value of this unconnected pins must be 0.
I've found out that by default this pins are set to 1. So it is force me to connect output source to all pins, otherwise it won't work properly.

The question is, how could I set this temporary unused pins to 0? I use Quartus II.

Thank you!
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Question on Arria NAND flash compatibility on page and block sizes

March 18, 2016, 4:19 pm
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We're considering using Arria V or 10 SOC to interface a CPU to an ONFI 4.0 compliant NAND. The particular NAND that must be supported has 1024 pages/block (arria max is 512) and page size 16384 (plus ECC bits) (arria is up to 8KBytes).

Is there any possibility of mating these devices, or no? We could consider "wasting" space in the blocks or pages because it's capacity is much more than we need....

Reason for having this issue: We are new to using NAND flash; we like the Arria because we would not have to ceritify IP, which is an issue in our industry (com'l Aerospace).

Thanks for any comments on this!
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nco v13.0 megacore problem

March 19, 2016, 12:39 am
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Hi i need seting-up a nco at 100MHz clock and 10 MHz output sine vawe.
I use nco megacore v13.0, but if i put desired output frequency 10 Mhz
the real output frequency is 1 Mhz.
Why?
Regards, Luca
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Altera Dual Port RAM

March 19, 2016, 7:15 am
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Hi Guys,

I've written a program in VHDL to access CIS and get data and transfer the data over USB using cypress USB transceiver CY7C68013A.

CIS : 1728 Pixels/Line, Output in three parts of 576 bytes.
CIS clock speed : 6.25Mhz, Max 8 Mhz.

FPGA : Cyclone III-EP3C25Q240C8N.

ADC : AD9200, 1st sample appears on the 5th clock hence first 4 clocks cycles are skipped for every line read.

Am using altera Dual Port RAM to get datas from the three outputs simultaneously and storing the datas in to 3 DPRAMs once this operation is done then I read the datas from DPRAM sequentially 1, 2, 3 and write the datas into cypress USB transceiver.

Problem:
When the image is created in the GUI, last four bytes (573,74,75,76) of the output is shifted to the first four bytes(1, 2, 3, 4). This four byte shift happens in all the three outputs.

I couldn't figure out what is the problem in my code.

Please Help. Thanks in advance.
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DE1-SoC HPS SDRAM memory mapping

March 19, 2016, 8:55 am
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Hi,
I've been using the demo1_axi reference project for DE1-SoC to display bmp image read from the Linux on the VGA screen. The QSys design is really simple because it just uses the Frame Reader component to read the frame from memory (using SDRAM controller) and streams it to the Mixer to display it on the screen. Now I wanted to add the second Frame Reader to read another image and display it alongside the first one. I added new Frame Reader in QSys, mapped the addresses for both frame readers, added the code i c part of the program to configure and display the second image, but it doesn't work.

Let me tell you the settings for the project. In QSys, the first Frame Reader was mapped to 0x0000_0100-0x0000_017f on h2f_lw_axi_master. After adding the second one I mapped it to 0x0000_0180-0x0000_01ff. I generated the QSys system and after compiling the project in Quartus generated new hps_0.h header file.

After that in C code I configured the second frame reader address (h2p_vip_frame_reader1_addr pointer) the same way as the first one was configured, added another layer in the mixer, mapped the address of the frame reader. The only thing I'm wondering about is the FR0_FRAME0_OFFSET value. For the first frame reader it is zero and I set the FR1_FRAME0_OFFSET to 0x01800000 as this is the base for the second frame reader. I'm not sure if I map everything correctly.

I post the code of the C part to make my pproblem more understandable. I tried to analyze the code and understand it and for now I don't know where the problem lies. Any help would be really appreciated. Thank you in advance.
Code:
#include <stdio.h>
#include <memory.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <dirent.h>
#include <inttypes.h>
#include <sys/time.h>
#include <stdbool.h>
#include <pthread.h>
#include  "hps_0.h"
#include "math.h"
#include "hwlib.h"
#include "socal/socal.h"
#include "socal/hps.h"   
#include "socal/alt_gpio.h"
#include  "disp_config.h"
#include  "lib_bitmap.h"




#define SDRAM_BASE_ADDR 0
#define ALT_VIP_SOFTWARE_RESET_N_BASE 0x00000200  //


//#define ALT_STM_OFST (0xfc000000)
//#define ALT_LWFPGASLVS_OFST (0xff200000)  // axi_lw_master


#define ALT_AXI_FPGASLVS_OFST (0xC0000000)  // axi_master
#define HW_FPGA_AXI_SPAN (0x40000000)  // Bridge span
#define HW_FPGA_AXI_MASK ( HW_FPGA_AXI_SPAN - 1 )


#define ALT_GPIO1_BASE_OFST  (0xFF709000)


#define HW_REGS_BASE (ALT_STM_OFST )
#define HW_REGS_SPAN (0x04000000 )
#define HW_REGS_MASK (HW_REGS_SPAN - 1 )




#define DEMO_VGA_FRAME0_ADDR                                    0x00000000//0x00080000 //0x00100000  //on chip memory base
#define FR0_FRAME0_OFFSET                            (0x00000000)




#define FR1_FRAME0_OFFSET                            (0x01800000)


static volatile unsigned long *h2p_lw_axi_addr=NULL;
static volatile unsigned long *h2p_vip_frame_reader0_addr=NULL;
static volatile unsigned long *h2p_vip_frame_reader1_addr=NULL;
static volatile unsigned long *h2p_memory_addr=NULL;
static volatile unsigned long *h2p_vip_mix_addr=NULL;










/////////////////////////////////////////////////////////
// VIP Frame Reader: configure


void    VIP_FR_Config(int Width, int Height){
    int word = Width*Height;
    int cycle = Width*Height;
    int interlace = 0;
   
    // stop
    h2p_vip_frame_reader0_addr[0]=0x00; // stop
    printf("Width=%d\r\n",Width);
    printf("Width=%d\r\n",Height);
    // configure frame 0
    h2p_vip_frame_reader0_addr[4]=DEMO_VGA_FRAME0_ADDR+FR0_FRAME0_OFFSET; // // frame0 base address
    h2p_vip_frame_reader0_addr[5]=word; // frame0 word
    h2p_vip_frame_reader0_addr[6]=cycle; //  The number of single-cycle color patterns to read for the frame
    h2p_vip_frame_reader0_addr[8]=Width; // frame0 width 
    h2p_vip_frame_reader0_addr[9]=Height; // frame0 height
    h2p_vip_frame_reader0_addr[10]=interlace; // frame0 interlace


    h2p_vip_frame_reader0_addr[0]=0x01; //start


    // select active frame
    h2p_vip_frame_reader0_addr[3]=0; // active frame 0 was set




// stop
    h2p_vip_frame_reader1_addr[0]=0x00; // stop
    printf("Width=%d\r\n",Width);
    printf("Width=%d\r\n",Height);
    // configure frame 0
    h2p_vip_frame_reader1_addr[4]=DEMO_VGA_FRAME0_ADDR+FR1_FRAME0_OFFSET; // // frame0 base address
    h2p_vip_frame_reader1_addr[5]=word; // frame0 word
    h2p_vip_frame_reader1_addr[6]=cycle; //  The number of single-cycle color patterns to read for the frame
    h2p_vip_frame_reader1_addr[8]=Width; // frame0 width 
    h2p_vip_frame_reader1_addr[9]=Height; // frame0 height
    h2p_vip_frame_reader1_addr[10]=interlace; // frame0 interlace


    h2p_vip_frame_reader1_addr[0]=0x01; //start


    // select active frame
    h2p_vip_frame_reader1_addr[3]=0; // active frame 0 was set
       
}


/////////////////////////////////////////////////////////
// VIP MIX
void    VIP_MIX_Config(void){
    h2p_vip_mix_addr[0]=0x00; //stop     
    // din0 is layer 0, background, fixe   
    // layer 2 (log)
    h2p_vip_mix_addr[2]=0;
    h2p_vip_mix_addr[3]=0;
    h2p_vip_mix_addr[4]=0x01;
   
    h2p_vip_mix_addr[5]=0;//(SCREEN_WIDTH-VIDEO_WIDTH)/2;//layer1 x offset
    h2p_vip_mix_addr[6]=500;//(SCREEN_HEIGHT-VIDEO_HEIGHT)/2;//layer1 y offset
    h2p_vip_mix_addr[7]=0x01;//set layer 1 active   
   
    h2p_vip_mix_addr[0]=0x01; //start
}








void  VIP_MIX_Move(int nLayer, int x, int y){
    h2p_vip_mix_addr[0]=0x00; //stop     
   
    h2p_vip_mix_addr[nLayer*3-1]=x;//layer1 x offset
    h2p_vip_mix_addr[nLayer*3]=y;//layer1 y offset


        h2p_vip_mix_addr[0]=0x01; //start
}




static int fr0_x = 0;
static int fr0_y = 0;


//static int fr1_x = (SCREEN_WIDTH );//-VIDEO_WIDTH
//static int fr1_y = (SCREEN_HEIGHT-VIDEO_HEIGHT );   


static int fr1_x = 0;//-VIDEO_WIDTH
static int fr1_y = 500;


void PIC_Move(void){


    static bool bX_Add = true;
    static bool bY_Add = true;
    const int nDelta = 5;
    const int nlayer = 1;
    /*
   
    int abs_x,abs_y;
   
    abs_x = abs(fr1_x - fr0_x);
    abs_y = abs(fr1_y - fr0_y);


    if( abs_x <= VIDEO_WIDTH && abs_y <= VIDEO_HEIGHT){
        if(abs_x == abs_y){
                if (bX_Add)        bX_Add = false;
                else            bX_Add = true;
                if (bY_Add)        bY_Add = false;
                else            bY_Add = true;


        }else if (abs_x < abs_y)
        {
                if (bY_Add)        bY_Add = false;
                else            bY_Add = true;
        }else{
                if (bX_Add)        bX_Add = false;
                else            bX_Add = true;
       
        }
    }
   


    // X direction
    if (bX_Add){
        if ((fr0_x + nDelta) >= SCREEN_WIDTH){ //+VIDEO_WIDTH
            fr0_x = SCREEN_WIDTH-1;//-VIDEO_WIDTH
            bX_Add = false;
        }else{
            fr0_x += nDelta;
        }   
    }else{
        if ((fr0_x-nDelta) < 0){
            fr0_x= 0;
            bX_Add = true;
        }else{
            fr0_x -= nDelta;
        }
    }
   
    // Y direction
    if (bY_Add){
        if ((fr0_y + nDelta)+VIDEO_HEIGHT >= SCREEN_HEIGHT){
            fr0_y = SCREEN_HEIGHT-VIDEO_HEIGHT-1;
            bY_Add = false;
        }else{
            fr0_y += nDelta;
        }   
    }else{
        if ((fr0_y-nDelta) < 0){
            fr0_y= 0;
            bY_Add = true;
        }else{
            fr0_y -= nDelta;
        }
    }
        */
fr0_x = 0;
fr0_y = 0;
  VIP_MIX_Move(nlayer, fr0_x, fr0_y);
}
   




int main(int argc,char ** argv) {
    void *lw_axi_virtual_base;
    void *axi_virtual_base;
    int fd;
    unsigned char pixbitcount;
    unsigned int width,height;
    if( ( fd = open( "/dev/mem", ( O_RDWR | O_SYNC ) ) ) == -1 ) {
        printf( "ERROR: could not open \"/dev/mem\"...\n" );
        return( 1 );
    }
    lw_axi_virtual_base = mmap( NULL, HW_REGS_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd, HW_REGS_BASE );   
    if( lw_axi_virtual_base == MAP_FAILED ) {
        printf( "ERROR: mmap() failed...\n" );
        close( fd );
        return( 1 );
    }
    axi_virtual_base  = mmap( NULL, HW_FPGA_AXI_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd,ALT_AXI_FPGASLVS_OFST  );   
    if( axi_virtual_base == MAP_FAILED ) {
        printf( "ERROR: axi mmap() failed...\n" );
        close( fd );
        return( 1 );
    }
    h2p_lw_axi_addr=lw_axi_virtual_base + ( ( unsigned long  )( ALT_LWFPGASLVS_OFST) & ( unsigned long)( HW_REGS_MASK ) );;
    h2p_vip_frame_reader0_addr= lw_axi_virtual_base + ( ( unsigned long  )( ALT_LWFPGASLVS_OFST + ALT_VIP_VFR_0_BASE ) & ( unsigned long)( HW_REGS_MASK ) );
h2p_vip_frame_reader1_addr= lw_axi_virtual_base + ( ( unsigned long  )( ALT_LWFPGASLVS_OFST + ALT_VIP_VFR_1_BASE ) & ( unsigned long)( HW_REGS_MASK ) );   
    h2p_memory_addr=axi_virtual_base + ( ( unsigned long  )( DEMO_VGA_FRAME0_ADDR) & ( unsigned long)( HW_FPGA_AXI_MASK ) );
    h2p_vip_mix_addr=lw_axi_virtual_base + ( ( unsigned long  )( ALT_LWFPGASLVS_OFST + ALT_VIP_MIX_0_BASE ) & ( unsigned long)( HW_REGS_MASK ) );       
   
    VIP_MIX_Config();
    VIP_FR_Config(VIDEO_WIDTH, VIDEO_HEIGHT);
   
        usleep(500*1000);
   


    GetBmpData(&pixbitcount,&width,&height, "demo1.bmp",h2p_memory_addr+FR0_FRAME0_OFFSET);
 usleep(500*1000);
    GetBmpData(&pixbitcount,&width,&height, "demo2.bmp",h2p_memory_addr+FR1_FRAME0_OFFSET);
    while(1)
    {
        //PIC_Move();
//usleep(50000);


    }   
    if( munmap( axi_virtual_base, HW_REGS_SPAN ) != 0 ) {
        printf( "ERROR: munmap() failed...\n" );
        close( fd );
        return( 1 );
    }
    if( munmap( lw_axi_virtual_base, HW_REGS_SPAN ) != 0 ) {
        printf( "ERROR: munmap() failed...\n" );
        close( fd );
        return( 1 );
    }
    close( fd );
    return( 0 );
}
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↧

Avalon-ST video conversion from 2-symbols per beat to 2-symbols per beat

March 19, 2016, 11:10 am
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Good evening,

I`m having trouble converting the output from an HDMI video input core to a suitable signal for my video pipeline.

If I keep all components in 2 pixels per beat mode (1 pixel = 24 bit RGB = 3 x 8-bit symbols), everything is working fine.
However some components like the Scaler only work with 1 pixel per beat.

I tried two solutions to convert my 2 beats per clock stream to a one clock per beat stream.


Solution 1: QSYS component that uses the following components

clocked video data from HDMI ->
clocked video input (2 pixels per beat) ->
avalon-st timing adapter (ready latency 1 to 0) ->
avalon-st data format adapter (6 symbols per beat to 3 symbols per beat) ->
timing adapter (ready latency 0 to 1) ->
video monitor component 1 ->
frame buffer ->
video monitor 2

Result: data arrives at monitor 1, but most of it is invalid. error: waiting for sink. but downstream framebuffer is verified to be working alright.


Solution 2:

Verilog component that puts the 2-pixels-per-clock clocked video input with dual clock frame buffer:

2-1-symbol.v is attached.

Result: works in some cases (e.g. direct output to monitor or direct loop-back to HDMI output,butnot reliably. especially if i try to apply scaling after this module, the whole pipeline pretty much stops working.


This should be a pretty common problem, maybe it's trivial and I just don't see it. Any idea is highly appreciated.

Thank you!
Klaus
Attached Files
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LP6 PC Card

March 19, 2016, 1:05 pm
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0
0
Hi,

can anyone tell me where/if I might be able to get hold of an LP6 PC card?

edit: Or, failing that, is there another way to program older, non-JTAG, CPLDs like the MAX7000 ( that is, not the S models) ?

regards
Dave
↧

Unable to write on SDRAM on DE0- Nano Cyclone IV E - waitrequest

March 19, 2016, 2:54 pm
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0
0
Hi,

I have a problem on a project on De0-Nano eval board (Cyclone IV E).
I have no idea where look or what I'm wrong.

I design a system made by: a I2S receiver connected to a fifo and the fifo to a Master Avalon-MM (Qsys System).

The strange behaviour is: I cannot write on SDRAM when I use the signals generated by I2S signals instead works correctly with the below piece of VHDL

Code:
        process(clk, rstN)
                variable cnt : integer range 0 to 255 := 0;
        begin
                if (rstN = '0') then
                        count <= (others => '0');
                        ready <= '0';
                                               
                elsif rising_edge(clk) then


                        if count =  0 then                               

                                ready <= '1';
                                left_channel_in        <= x"1234" & std_logic_vector ( to_unsigned( cnt, 16)  );
                                right_channel_in        <= x"ABCD" & std_logic_vector ( to_unsigned( cnt, 16)  );


                                cnt := cnt +1;
                        else
                                ready <= '0';
                        end if;
                       
                        count <= count + 1;
                       
                       
                end if;
        end process;

Below, the signals on avalon bus, in the case of usage of above vhdl


If I connect the I2S Reciever to rest of system, it doesn't work, see the image (the waitrequest after the first write never goes low)



I don't understand why : in both tests the code which manages the SDRAM is the same and I write in both case to a fifo.

Has Anyone an idea?
Attached Images
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