Input conduit with clock and Avalon-ST source clock

March 19, 2016, 6:47 pm

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I have implemented a series of custom audio IPs, that I've later come to realize resembles Avalon-ST. So I'm going to attempt to port them to Avalon-ST be able to use them from Qsys. One of those IPs is a data receiver which gets its data from a (external) conduit and sends out on an Avalon-ST source port.

The clock for the input data is asynchronous of the (faster) system clock and is among the conduit signals. What is the best approach for setting up the clock system for this?

I) Should I use the input data clock as the only clock source in the IP, and thus setup assosciated clock with both conduit and avalon-ST port?

Because Qsys can and will automatically handle cross clock domain crossings?

II) or, will it be better to accept two clocks into my IP; the conduit data clock and the avalon-ST clock, and handle clock domain crossing myself in the IP?

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Beginner ? Creating IP from VHDL code using Qsys

March 19, 2016, 9:40 pm

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Delete Found a solution

nios2-flash-override

March 20, 2016, 7:10 am

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Hello,
Could anyone please confirm, that nios2-flash-override.txt method does not work in Quartius 15.1.2 neither in the gui nor in the command line untill indicated directly with the --override option.

Thanks,
NJ

Best demodulation method

March 20, 2016, 7:36 am

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Hi,
I have to transmit data modulated with 250Hz carrier and bit time of 12ms (3 period of carrier). Obviously i need to demodulate that message on receiver side.

The problem is that on the transmission channel 60Hz and 180Hz signals are present. So that two frequencies could be added to the transmitted signal @ 250Hz.

Now i don't know witch kind of modulation/demodulation method is the best suitable for my purpose and if i use a classical one (ask or bpsk) is there a technique to filter out undesired frequencies?

Thanks let me know.

Unable to download the .SOF file onto DE1 SoC board

March 20, 2016, 12:16 pm

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Hi guys,

I have a DE1 SoC board with Cyclone V FPGA. I am trying to run the Count Binary template on the NIOS II processor. I have constructed a QSYS system with all the necessary components. However when I try to download the .SOF file, I get the following error:

Error (209015): Can't configure device. Expected JTAG ID code 0x02D120DD for device 2, but found JTAG ID code 0x00000000. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).

I am pretty sure that I am using the correct device and settings. I have successfully run Hello from NIOS program using the same technique and it works fine.

Thanks for the help.

Power On VCCIO before VCCINT

March 20, 2016, 6:45 pm

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HI,

What will happen to IO pins voltage if the VCCIO supply is powered ON before VCCINT supply during initial board Power-UP? Take note that during initial power-UP the FPGA is in unknown state.
Does it cause some voltage glitch of several milliseconds across I/O pins during initial power up?

Regards,

I can't register an account myAltera

March 20, 2016, 2:48 pm

≫ Next: Altera SDK license for OpenCL

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Hello people, I tried to register an account myAltera but I couldn't. I filled all the gaps correctly but the system responded with this:

:cry:What am I doing wrong? Where is the error?

I live in San Juan, Argentina. I'm a student at Universidad Nacional de San Juan (UNSJ). I'm starting a course about FPGA and I need register to download the software Quartus Prime Lite Edition.

Attached Images

• 1.jpg (11.3 KB)

Altera SDK license for OpenCL

March 21, 2016, 2:52 am

≫ Next: [Arria V] ALTPLL: how to use second counter output

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Hi All,

I am getting an Eroor for aoc command.
Error : aoc : cant find valid License for Altera SDK for OpenCL.

Please note: I alreday gave all Licenses.

What to do now? How can I check wether, I have my licenses executed or not?

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[Arria V] ALTPLL: how to use second counter output

March 21, 2016, 4:01 am

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Hi,

I'm still new in using the Quartus II software. May I know how to select/use the second counter output for pll from the Megawizard Plug-In Manager?
Prompt reply from you guys would be greatly helpful. Thanks!

PIO base address constant, defined on design

March 21, 2016, 5:24 am

≫ Next: Altera Stratix III and ALtera-Terasic HSMC Board: Access Audio ports

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Hi,


I have made some experiments on NIOS2 core with the Avalon PIO and it’s working fine.

However, differently from some examples found on the Web, e.g IORD(PIO_0_BASE,0) - I had to manually paste the numerical base address of the pio_0 which was generated by Qsys. I had to do this way for the sake of Eclipse underlined this parameter warning that it was not recognized by compiler. Although I made a deep search on the content of all files of the design by Windows search tool, seeking some occurence of the partial word “PIO_0” assigned to something related to it current address “3030” ( actually, 0x0000_3030 ), could not find anything.

Correct me if I’m wrong, but should I manually create my own assignments, or are there a better way ?
I fear that after performing eventual updating on base addresses on Qsys this could change the value already defined

Code:

---

#define        PIO_0_BASE        0x00003030

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Altera Stratix III and ALtera-Terasic HSMC Board: Access Audio ports

March 21, 2016, 6:40 am

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Hi!

I am working on a project titled, 'Melody Extraction from Polyphonic Music Signals'. For that I am using a Stratix III EP3SL150 board manufactured by Altera and a HSMC Daughter Card co-manufactured by terasic and Altera. I am having problems in accesing the audio ports, both mic and headphone. Could someone please help me out with this. I previously have not much of an experience working with Altera boards.

Thanks in advance for helping.

NIOS II gen 2 not starting when code compiled with O0 optimization

March 21, 2016, 10:10 am

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Hi,

My code simply does not run if in the BSP settings I leave the default O0 compiler optimization. With O1 and Os it works I have tried.

The code starts like this:

Code:

---

  *leds = 0xFF;
  printf("\n hello world1");

  fp = fopen("/dev/uart", "rb+");
  printf("\n after fopen");
  fprintf(fp, "hello world2");
  printf("\n after fprintf");

---

When I debug the the debug view in eclipse shows that the program is running immediately i.e. it is not waiting at the first line of the code as usual. This also is resolved by using O1 or Os optimization.

What is wrong?!?

I use Quartus Prime lite 15.1.

Mitko

CIC IP Core in Quartus 15.1 for 5CSEBA5U23

March 21, 2016, 11:29 am

≫ Next: What is the function of hps_reset?

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I develop project for SOC 5CSEBA5U23I7 in Quartus 15.1. I use CIC IP Core. When I choose in IP Core settings "Number or interfaces" >1 (more than one) in decimation mode, I can't get signals "out_startofpacket" and "out_endofpacket". Can anyone help me with it?

What is the function of hps_reset?

March 21, 2016, 1:20 pm

≫ Next: ALTDDIO : both high and low outputs are at flat rate

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I am working on a DE0-Nano-SoC kit from Terasic, based on a Cyclone V. In several of the the GHRD and examples the following construct is used:

Code:

---

wire [2:0] hps_reset_req;

hps_reset hps_reset_inst (
  .source_clk (fpga_clk1_50),
  .source (hps_reset_req)
);

---

then each of the three bits are fed into 3 altera_edge_detector and then fed into the *_reset_req_reset_n ports in the HPS.

What is the function of hps_reset? I can't find any useful docs for this (could not find it in the Cyclone V handbook, in the Quartus II handbooks nor on Alteras website).

ALTDDIO : both high and low outputs are at flat rate

March 21, 2016, 8:34 pm

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Hi,

Per title. Why does the outputs (HI and LO) for the DDIO have to be always at flat rate?
I don't have enough information to explain the situation, but quick answer from you guys would be very much appreciated :)

Thanks!

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any way to control turn on/off LSU embedded cache?

March 21, 2016, 8:53 pm

≫ Next: Identifier "UNSIGNED" is not directly visible

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Hi,

Currently the aoc compiler will decide if the embedded cache in the LSU will be used according the the size/type etc.

But is there any way to control it manually?

Any advice and suggestion is appreciated. Thanks in advance.

Identifier "UNSIGNED" is not directly visible

March 22, 2016, 12:10 am

≫ Next: Modelsim SE code coverage error

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i have used the following libaries


LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;


still the error in modelsim shows :


** Error: G:/vhdl code/vhdl code/dwt_main.vhd(30): (vcom-1078) Identifier "UNSIGNED" is not directly visible.


Potentially visible declarations are:
ieee.NUMERIC_STD.UNSIGNED (subtype declaration)
ieee.std_logic_arith.UNSIGNED (type declaration)


** Error: G:/vhdl code/vhdl code/dwt_main.vhd(31): (vcom-1078) Identifier "SIGNED" is not directly visible.


Potentially visible declarations are:
ieee.NUMERIC_STD.SIGNED (subtype declaration)
ieee.std_logic_arith.SIGNED (type declaration)


how to solve it

Modelsim SE code coverage error

March 22, 2016, 1:27 am

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Hi all.

I use modelsim SE 10.4c (not Altera edition).
I have a problem when use code coverage mode. Below i descript the problem:

I compile (using .do file) lot of sources:

Code:

---

vlog -work $prjworklib -novopt -lint -cover bcsxf +incdir+$incdir+$rtldir $rtldir/preprocess/filter/filter_mult.v
...
...

---

After this, i run the simulation from Modelsim console (using .do file):

Code:

---

vsim -L altera_mf -coverage $prjsimlib/work.tb

quietly WaveActivateNextPane {} 0

add wave -noupdate -divider {system}
add wave -noupdate -format Logic -radix unsigned {/tb/reset}
add wave -noupdate -format Logic -radix unsigned {/tb/sys_clk}

...
...

TreeUpdate [SetDefaultTree]
update

run -all

---

Next, in modelsim i got coverage reports with some coverage results.

The problem:
When i try to open coveraged file using double click on non-coveraged code section or using file--open menu (see screenshot) - modelsim cannot open the file and i get error Numeric coverage display disabled.

Уменьшено до 77% 1363 x 766 (129.53 килобайт)

Please help me to solve it.
Thanks! :)

de4_pcie_tutorial

March 22, 2016, 2:16 am

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Hello everyone, i have been trying to go through the tutorial on pcie for the de4 board. I got my qsys_system.qsys files done and have my .sof. I have also compiled my drivers and have loaded them in linux which detects the de4 board upon loading. However, if i download the bit stream of the tutorial onto the board, and perform a reboot on the linux computer, the device is no longer listed. I don't seem to have an idea where the problem lies but hoping i can get some solution here. thank you.

burn two max 10 in 2 hours, someone please tell me the power on/off secquence

March 22, 2016, 3:10 am

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burn two max 10 in 2 hours, someone please tell me the power on/off secquence of the altera fpga and jtag
i use 5 years xilinx and recently i want to use altera
i think may be my bad habits make me burn two max10 in 2 hours
1. the usb blaster is connected with the computer, but is not connected with the PCB
2. the pcb is power off
3. i connect the usb blaster with the pcb(maybe that why i burn the fpga)
4. i power on the pcb
then i can not download the sof file to the fpga....
someone please tell me:
1.what is the sequence of power on?
2.what is the sequence of power off?
3.when the usb blaster is connected both with the PCB and computer, can i power off the PCB and then POWER on it?