Quantcast
Channel: Altera Forums
Viewing all 19390 articles
Browse latest View live
↧

Profiler error: Incompatible AOCX

March 22, 2016, 3:13 am
$
0
0
I am trying to run the profiler on a kernel but I get the error:
Incompatible AOCX file, quartus report information not available
Please regenerate your AOCX file with the latest version of the aoc compiler.

First I compiled the kernel with QII 15.0. Then I loaded the .sof file and rebooted the computer.
Then I ran my host program and that worked just fine. This also generated the profile.mon file.
Then, when running the aocl report some_name.aocx profile.mon

Do I have a setting incorrect or am I doing something wrong?
↧
Search

OpenCL Licence

March 22, 2016, 5:59 am
$
0
0
Hi,

How can I verify that I have valid licence for OpenCL SDK?

Is there any command or setting? I am using windows 7.
↧
↧

Help to understand PCIe Host PC frequency

March 22, 2016, 6:11 am
$
0
0
Hi people,

I need some help to understand the PCIe clock frequency on host PC's.

According to PCIe Sig, the PCIe clock frequency should be 100 MHz +- 300 ppm. Then, to follow this recommendation, i configured a SIlabs 5338 to synthesise precisely 100 MHz and used it to feed the FPGA Transceivers of Altera PCIe Hard IP, i'm using local clock reference on my project.
The result was that my project do not worked! I could not establish a communication with my board and linux do not recognized it.
After make a lot of tests, i found that the PC was generating 99,7~ MHz as a reference to PCIe, i measured it in the motherboard, what is out of 300 ppm range. I measured 3 diferente PC's and all of then had the same value .
After i configure silabs with this value the system started to work.

The question is: why PC's use this frequency and do not PCI Sig recommendation?

Thank you,
↧

Arria 10 GSRD board - unable to write reg or mem via Linux

March 22, 2016, 6:33 am
$
0
0
I've got the Arria 10 GSRD board. I'm running from a pre-built SD card image created by following instructions on the rocketboards site for the A10 GSRD, which I can't link here.
The page here shows where some things are mapped in memory:

https://rocketboards.org/foswiki/vie...U_Address_Maps

I tried to write memory at 0xc0000000, but I got the following error:

Unhandled fault: external abort on non-linefetch (0x818) at 0x76fcb000
Bus error

I did some searching and found this:

https://lists.rocketboards.org/piper...st/003271.html

This guy got around a similar problem by rebooting, stopping in uboot, and doing what he called "Setting privilege filter at U-Boot and non-privilege access from Linux App". This is done by writing 0xffffffff to location 0xffd11004 while in uboot, then booting Linux. I copied more or less what he did:

mw.l 0xFFD11004 0xFFFFFFF
run bootcmd

I tried this, and it worked one time only. I can't make this work again, and I can't find any reliable way to write either some area of memory or a register without the exception noted above.
What am I missing? Thanks.


↧

Fitter Report - Caret character - what does it mean?

March 22, 2016, 7:18 am
$
0
0
Compiling for a C 5 SOC chip and in the fitter reports, "All package Pins" section, there is a '^' (caret) character that precedes signals. What does it mean? See below example:

V4 36 3A ^DCLK Weak Pull Up -- On 402
C1 437 9A ^GND -- -- -- 403
F15 304 7A ^GND -- -- -- 404
F17 295 7A ^GND -- -- -- 405
G17 294 7A ^GND -- -- -- 406
C16 306 7A ^HPS_CLK1 -- -- -- 407
↧
↧

MAX 10 - ADC pins as GPIO

March 22, 2016, 7:59 am
$
0
0
Hi.

I've a doubt about MAX 10 dual supply. To use the both AD converters, it's necessary to put 2.5V on bank 1A and on bank 1B. But, if only the ADC1 is necessary, the bank 1B can be GPIO in 3.3V?


I did not find this information clearly.

Thanks in advance.
↧

Why do the number of VCCIO and GNDIO pairs more than number of banks in a device?

March 22, 2016, 8:02 am
$
0
0
I assumed that there is a VCCIO for each bank. However, it seems that a single bank can have multiple VCCIO and GNDIO connections.
As far I understand a single bank shall have a single IO voltage which can be different from another bank but must be within the specified device limits.
Why does a singe bank need multiple VCCIO and GNDIO connections?
↧

Creating Video Output

March 22, 2016, 8:03 am
$
0
0
Hello guys!

I know, there is a bunch of threads around, speaking of how to create a basic video output, but none of the templates/instructions worked for me. Also I'm quite new to FPGA, Verilog and the whole thing, so I hope you can help me a little further.

First thing: I'm using a Cyclone V GX Starter Kit Devboard.

What I'm supposed to do is creating a video output, based on data from the LPDDR2 RAM, which gets written there by a Nios2 processor.

But let's focus first on a much smaller goal, which I would like to achieve first:

Creating a Testpattern and forwarding the video data to a Clocked Video Output, which sends the data over the onboard HDMI interface. Assuming the onboard AD-whatever HDMI controller is already initialized, I would just have to open QSYS, add those two components with the given parameters, export the conduit of the output and connect it with HDMI data lanes.
But nope, it's not that easy! :( First of all, the clocked video output gives me an error about wrong ready latency. Source is 0 and sink 1... Ok, I would insert an Avalon-ST timing adapter and everything is fine, but nope again! There is no timing adapter for video streams :evil: What then?
Next to that, how do I connect the conduit of the CVO properly to the HDMI data lanes? I'm assuming that vid_clk is the pixel clok, vid_data is video data as rgb, vid_datavalid is data enable, h/v_sync is h/v sync. But what is vid_h and vid_v for? Where do I need to connect them? I figured out what vid_f is, and since it determines if the video is interlaced or progressive I assume I can leave it unconnected, but the other two?

I would appreciate your help very much, since this is driving me mad for about two weeks now, and I have to come to some results...

Best regards,
Migsi
↧
Search

QSYS Comments?

March 22, 2016, 9:19 am
$
0
0
Hello,

I am a beginner Quartus user, and I've been playing around with some example projects for the MAX 10 Deca Kit.

One thing about QSYS I've found so far, is that aside from the names, there is not much information about what seperate IP blocks in a QSYS project are Meant to do for the project (ie multiple PIO blocks, for example).

Is there a better way to document, or leave/find comments on the IP blocks so users can understand what the block is meant to do, project wise?

Thanks for any advice.
↧
↧

Program FPGA from EPCS, and boot Linux from SDCard?

March 22, 2016, 3:15 pm
$
0
0
Given a Cyclone V SoC (HPS) with a EPCS and SD-Card. Is it possible to setup FPGA to load config from EPCS, while booting Linux from the SD Card without reprogramming the FPGA?
↧

IOPLL rst input

March 22, 2016, 3:35 pm
$
0
0
I instantiated an IOPLL in an Arria 10 SoC design and tried to tie the rst input to logic 0. Quartus Prime won't let me do that. I don't want to reset the PLL and the user guide does not say that a reset is required (although the pin has to be there). Why can't rst just be tied off to the inactive state?

Thanks,
Bob
↧

Where is the PWM core/ip?

March 22, 2016, 3:38 pm
$
0
0
Hi all,

I thought there will be a PWM core/ip in Quartus Lite 15.1 (Qsys) but I think I'm wrong. Unless it has a weird name that I can't figure out. Is there one?

Thanks
↧

Accessing individual nodes in a bus

March 22, 2016, 8:22 pm
$
0
0
Hi
How can the individual nodes on a bus be accessed? Is using LPM_DECODE the only way?
Thanks
↧
↧

DE1 - checking SRAM?

March 22, 2016, 10:29 pm
$
0
0
Hello,

I own a DE1 board and would like to test the onboard SRAM. I'm using the board for learning/hobby, and having issues with the SRAM use I'm currently split between bad design or faulty chip. (I'm experiencing data consistency issues)

Can anyone point me to a trusted SRAM test bench for this board?

I've tried the DE1 control panel, lastest versions don't include SRAM access anymore.
Found out the old 1.00 version on the web, and doing a write/read cycle on the SRAM bring me back an altered file. It's different on each read tho and that isn't the same issue i'm experiencing on my own project (altered data but consistent across multiple readings).
Can this old panel be trusted?


Thanks! :)
↧

A synchronous clear enable conter RTL

March 23, 2016, 1:43 am
$
0
0
I have issues with RTL of simple counter: a synchronous clear enable counter.
I use Altera template to be confident as much as possible.
http://quartushelp.altera.com/14.1/m...o_counters.htm
https://www.altera.com/en_US/pdfs/li...s-handbook.pdf HDL guides for counters on 12-57


I expect such counter to consist of one adder, one mux and one register, but I get two muxes if using provided template. Instead of using EN input of register second mux is implemented. How do I specify to use EN input of register?
Can someone provide information on this issue? Maybe I don't understand something.


I've tried to change synthesis options and it did't work.
I can implement my vision of RLT with one MUX using d = a?b:c operand. But I find it kind of akward.
See code below.

Code:
module counter
(
input en, clk, rst,
output reg [3:0] count,
output reg [3:0] count2);


// One MUX RTL
wire [3:0] new_count = rst ? 4'd0 : count + 1;
always @(posedge clk) begin
 if (en) count <= new_count;
end


// Two MUX RTL (using altera template)
always @(posedge clk) begin
if (rst) count2 <= 0;
else if (en) count2 <= count2 + 1;
end


endmodule
↧
Search

LPDDR2 Interfacing to CycloneV

March 23, 2016, 3:00 am
$
0
0
Hi,

In general, from Board design perspective,
What is the process (with quartus SW) for planing LPDDR2 interface on CycloneV?
For example how to determine which BANK/IO to use


Thanks
↧

Max 10 Development Kit DAC

March 23, 2016, 3:19 am
$
0
0
Hey all,

first of all, I'm new to programming with Quartus. I want to sample a signal with one of the ADCs on the Max 10 Development kit. After that, I want to convert the descrete signal again to an anolog one with the DAC and put it on an oscilloscope. I managed to configure the ADCs but I failed to configure the DAC. Can anyone help?
↧
↧

UART Examples for MAX10M 50 DA F 484 C 6 GES

March 23, 2016, 4:43 am
$
0
0
Hi All,

Am learning FPGA. So far, I have done blinking LED with uC OS tasks switching. [ from Qsys->Quartus->Nios II]. It is working fine. I took help from materials from altera site.

Now, am trying to do UART. So far, I dont see any examples in altera site or in internet.
Can anyone please suggest some hints or share some materials/guide for UART use in MAX10M 50 DA F 484 C 6 GES, with uC RTOS.

Thank you
↧

Possible virus BoardTestSystem32.exe

March 23, 2016, 5:02 am
$
0
0
Hello,

We have stopped an application from running called BoardTestSystem32.exe. The binary was located in the directory:
C:\altera\14.1\kits\arriaVST_5astfd5kf40_soc_orig\ examples\board_test_system\BoardTestSystem32.exe

The reason why we blocked this binary is because the SHA256 value of this binary matches a common virus on virus total
SHA256:05bb1b4d1f53c8bb737fb03904a2b04822bdabd9ba1 7c4c240f408432a7d9a5f

https://www.virustotal.com/en/file/0...9a5f/analysis/

We know that we have several users using Altera and we wanted to double check that this binary is indeed your binary as it is unsigned and has a poor reputation on virus total.

Can someone validate that this is indeed a trusted payload? I will be analyzing this in a sandbox environment, but would like some input from the community here.

Cordially,

Tim
↧

Fitter error: can't place fractional PLL in Cyclone V ST.

March 23, 2016, 6:06 am
$
0
0
Hi,
I have a design that uses the Hard Memory interface for the HPS and for the FPGA DDR memory. If I add a regular PLL to this design from an I/O pin in bank 3A (bank 3B and 4A are the DDR banks for the FPGA DDR memory), then it claims it can't fit a Fractional PLL because of pin constraints. Why does using the DDR memory stop me using any of the other clock inputs to run a PLL? Makes it fairly pointless having a device with 15 PLLs.

And why does it try and place a fractional PLL when I don't need the fractional bit?

Any help appreciated.

Simon
↧
Viewing all 19390 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>