I am using the LVDS HSMC RX pins on the Arria V GX Starter Board, I have RX pins HSMA_RX_D[16:0] all to be clocked using HSMA_CLK_INP1 (all pins are LVDS). The incoming clock is 250MHz and the data is DDR but I need to have a deserialization factor of 4 (i.e. 125MHz output clock). I have tried to use the ALTLVDS_RX IP and regardless if I use an external PLL or have the PLL internal to the ALTLVDS_RX block I get an error during the fitting process after Analysis & Synthesis has succeeded:
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 PLL LVDS output(s)). Fix the errors described in the submessages, and then rerun the Fitter.
Error (175020): The Fitter cannot place logic PLL LVDS output that is part of Altera PLL pll_adc in region (169, 21) to (169, 24), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The PLL LVDS output name(s): <PLL OUTPUT CLOCK AT DATA RATE>
Error (16234): No legal location could be found out of 4 considered location(s). Reasons why each location could not be used are summarized below:
Error (180002): Can't place PLL LVDS output because the SERDES DPA is already driven by 2 clock and clock enable pairs (4 locations affected)
Info (175029): PLLLVDSOUTPUT_X169_Y21_N2
Info (175029): PLLLVDSOUTPUT_X169_Y22_N2
Info (175029): PLLLVDSOUTPUT_X169_Y23_N2
Info (175029): PLLLVDSOUTPUT_X169_Y24_N2
Info (175013): The PLL LVDS output is constrained to the region (169, 21) to (169, 24) due to related logic
Info (175015): The I/O pad HSMC_CLKIN_p[1] is constrained to the location PIN_AN3 due to: User Location Constraints (PIN_AN3)
Info (14709): The constrained I/O pad is contained within a pin, which drives a fractional PLL, which drives this PLL LVDS output
Some things I tried:
1) I looked at
http://www.alteraforum.com/forum/arc...p/t-42882.html ... So I tried ALTLVDS_RX module to use the "Regional Clock" setting and the "Auto" clock output setting (before specifying the PLL was external when using an external PLL).
2)
http://www.alteraforum.com/forum/showthread.php?t=46028 solved a similar issue using two different ALTLVDS_TX modules, I did the same except used one module for each input data pin
3)
https://www.altera.com/support/suppo...82.tablet.html mentioned using a buffer so I did that:
arriav_pll_lvds_output #(
.pll_loaden_enable_disable("true"),
.pll_lvdsclk_enable_disable("true"))
arriav_pll_lvds_output_inst (
.ccout({clkadc_rxen, clkadc_data}),
.loaden(lvds_clken),
.lvdsclk(lvds_clkdata)
);
lvds_adc rx_adc_lvds (
.rx_inclock(lvds_clkdata),
.rx_enable(lvds_clken),
.rx_in(HSMC_RX_p[14:2]),
.rx_out(adc_lvds_out[51:0])
);
I got the following error:
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 PLL LVDS output(s)). Error (175020): The Fitter cannot place logic PLL LVDS output in region (169, 21) to (169, 24), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The PLL LVDS output name(s): arriav_pll_lvds_output_inst
Error (16234): No legal location could be found out of 4 considered location(s). Reasons why each location could not be used are summarized below:
Error (180002): Can't place PLL LVDS output because the SERDES DPA is already driven by 2 clock and clock enable pairs (4 locations affected)
Am I doing something wrong? Is there something I am missing? Please note, if only one pin data pin is being clocked using the ALTLVDS_RX module it will work, my issue is it will not fit if I have multiple data pins (either using multiple ALTLVDS_RX blocks or using one multilple channel ALTLVDS_RX block)