The performance of FPGA is not the same when I download the sof file into the FPGA for some times. In my project, I have done a module which create a reset signal for 1 second, I think the time is enough. I have constraint the all clock and the fault path. The timequest is passed.
↧
The performance of FPGA is not the same when I download the sof file into the FPGA
↧
Why change phase of PLL doesn't improve clock skew?
Dear all,
I have an dedicated clock input to feed an main PLL and has too clock output with the same frequency, one clock output from the main PLL is to launch the finished data, the other clock is to feed the logic unit (which has its own PLL) to process data. There is -4.6 ns clock skew between the derived clock inside the logic unit and the first clock output from main PLL. I changed the phase of the first clock output which is responsible to launch finished data, want to improve clock skew. However, the clock skew doesn't seem to change.
Anyone can help me? Thank you very much!
I have an dedicated clock input to feed an main PLL and has too clock output with the same frequency, one clock output from the main PLL is to launch the finished data, the other clock is to feed the logic unit (which has its own PLL) to process data. There is -4.6 ns clock skew between the derived clock inside the logic unit and the first clock output from main PLL. I changed the phase of the first clock output which is responsible to launch finished data, want to improve clock skew. However, the clock skew doesn't seem to change.
Anyone can help me? Thank you very much!
↧
↧
Add subtract seven segments display
I am going to pre-apologize for posting something so elementary on this site. I have taken a class where we have basically been told that Verilog is a programming language now go code a 7 segment display in ISE design suite. We have been taught absolutely nothing about Verilog so this is quite the frustrating endeavor for me.
The goal is to take two inputs A,B and an Overflow S and either subtract B from A if Overflow=0 or add the two if Overflow = 1. We are to then have the correct answer displayed on a 7 segment display. I have pasted what I have come up with so far below. Any help would be greatly appreciated. I am extremely lost.
module AddOrsubtractThenSelectAndDecodeInto7SegmentDispla y(
input [3:0] A,
input [3:0] B,
input [1:0] S,
output [3:0] Output,
output reg [1:0] Overflow,
output reg [6:0] Display
);
reg [3:0] Output_reg;
wire [3:0] A;
wire [3:0] B;
wire [1:0] S;
always @(S or A or B)
begin:Ouput_reg
if (S == 1'b1) begin
Output_reg = A + B;
end else begin
Output_reg = A - B;
end
end
endmodule
module Seven_dig(
Overflow,
Output_reg,
Display
);
input Overflow,Output_reg;
output Display;
reg Display;
always @({Overflow,Output_reg}) begin
case ({Overflow,Output_reg} )
5'b00000: Display = 7'b1111110;
5'b00001: Display = 7'b0110000;
5'b00010: Display = 7'b1101101;
5'b00011: Display = 7'b1111001;
5'b00100: Display = 7'b0110011;
5'b00101: Display = 7'b1011011;
5'b00110: Display = 7'b1011111;
5'b00111: Display = 7'b1110000;
5'b01000: Display = 7'b1111111;
5'b01001: Display = 7'b1111011;
5'b01010: Display = 7'b1110111;
5'b01011: Display = 7'b0011111;
5'b01100: Display = 7'b1001110;
5'b01101: Display = 7'b0111101;
5'b01110: Display = 7'b1001111;
5'b01111: Display = 7'b1000111;
5'b00000: Display = 7'b1111110;
5'b10000: Display = 7'b1111110;
5'b10001: Display = 7'b0110000;
5'b10010: Display = 7'b1101101;
5'b10011: Display = 7'b1111001;
5'b10100: Display = 7'b0110011;
5'b10101: Display = 7'b1011011;
5'b10110: Display = 7'b1011111;
5'b10111: Display = 7'b1110000;
5'b11000: Display = 7'b1111111;
5'b11001: Display = 7'b1111011;
5'b11010: Display = 7'b1110111;
5'b11011: Display = 7'b0011111;
5'b11100: Display = 7'b1001110;
5'b11101: Display = 7'b0111101;
5'b11110: Display = 7'b1001111;
5'b11111: Display = 7'b1000111;
default: Display = 7'b0001111;
endcase
end
endmodule
The goal is to take two inputs A,B and an Overflow S and either subtract B from A if Overflow=0 or add the two if Overflow = 1. We are to then have the correct answer displayed on a 7 segment display. I have pasted what I have come up with so far below. Any help would be greatly appreciated. I am extremely lost.
module AddOrsubtractThenSelectAndDecodeInto7SegmentDispla y(
input [3:0] A,
input [3:0] B,
input [1:0] S,
output [3:0] Output,
output reg [1:0] Overflow,
output reg [6:0] Display
);
reg [3:0] Output_reg;
wire [3:0] A;
wire [3:0] B;
wire [1:0] S;
always @(S or A or B)
begin:Ouput_reg
if (S == 1'b1) begin
Output_reg = A + B;
end else begin
Output_reg = A - B;
end
end
endmodule
module Seven_dig(
Overflow,
Output_reg,
Display
);
input Overflow,Output_reg;
output Display;
reg Display;
always @({Overflow,Output_reg}) begin
case ({Overflow,Output_reg} )
5'b00000: Display = 7'b1111110;
5'b00001: Display = 7'b0110000;
5'b00010: Display = 7'b1101101;
5'b00011: Display = 7'b1111001;
5'b00100: Display = 7'b0110011;
5'b00101: Display = 7'b1011011;
5'b00110: Display = 7'b1011111;
5'b00111: Display = 7'b1110000;
5'b01000: Display = 7'b1111111;
5'b01001: Display = 7'b1111011;
5'b01010: Display = 7'b1110111;
5'b01011: Display = 7'b0011111;
5'b01100: Display = 7'b1001110;
5'b01101: Display = 7'b0111101;
5'b01110: Display = 7'b1001111;
5'b01111: Display = 7'b1000111;
5'b00000: Display = 7'b1111110;
5'b10000: Display = 7'b1111110;
5'b10001: Display = 7'b0110000;
5'b10010: Display = 7'b1101101;
5'b10011: Display = 7'b1111001;
5'b10100: Display = 7'b0110011;
5'b10101: Display = 7'b1011011;
5'b10110: Display = 7'b1011111;
5'b10111: Display = 7'b1110000;
5'b11000: Display = 7'b1111111;
5'b11001: Display = 7'b1111011;
5'b11010: Display = 7'b1110111;
5'b11011: Display = 7'b0011111;
5'b11100: Display = 7'b1001110;
5'b11101: Display = 7'b0111101;
5'b11110: Display = 7'b1001111;
5'b11111: Display = 7'b1000111;
default: Display = 7'b0001111;
endcase
end
endmodule
↧
DE2i-115 LCD 16x2
Hi Everyone;
I have a problem with my lcd_controller. I think that the initialization is wrong. here is my code.
I wonder if you can help me please. I have no idea where is the problem.
Thank you.
Best Regards.
I have a problem with my lcd_controller. I think that the initialization is wrong. here is my code.
Code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
Entity LCD_Controller Is
Port (
CLK : in std_logic;
RST : in std_logic;
Sel : in std_logic_vector(1 downto 0);
Power_ON : out std_logic;
LCD_EN : out std_logic;
LCD_Busy : out std_logic;
LED_Test : out std_logic_vector(9 downto 0);
LCD_RS : out std_logic;
LCD_RW : out std_logic;
LCD_DATA : out std_logic_vector(7 downto 0)
);
end LCD_Controller;
ARCHITECTURE Arch OF LCD_Controller Is
TYPE State_Type IS (Power_Up, Initialisation, ReturnHome,
Choose, Word1, Word2, Word3,
WriteData11, WriteData12, WriteData13, WriteData14
--,WriteData21, WriteData22, WriteData23, WriteData24, WriteData25, WriteData26, WriteData27, WriteData28, WriteData29, WriteData2A, WriteData2B, WriteData2C, WriteData2D, WriteData2E, WriteData2F, WriteData2G, WriteData2H, WriteData2I, WriteData2J, WriteData2K, WriteData2L,
--WriteData31, WriteData32, WriteData33, WriteData34, WriteData35
);
Signal pr_Stat, nx_Stat : State_Type;
Signal SlowClk : std_logic := '0';
CONSTANT freq : INTEGER := 50; --system clock frequency in MHz
Begin
Power_ON <= '1';
PROCESS(CLK, RST)
BEGIN
IF(RST = '1')THEN
pr_Stat <= Power_Up;
ELSIF(clk'EVENT and clk = '1') THEN
pr_Stat <= nx_Stat;
END IF;
END PROCESS;
PROCESS(pr_Stat, Sel)
VARIABLE clk_count : INTEGER RANGE 0 TO 4194304; --event counter for timing
BEGIN
CASE pr_Stat IS
When Power_Up =>
LCD_Busy <= '1';
LED_Test(0) <= '1';
IF(clk_count < (3000 * freq)) THEN --wait 50 ms with clock 50Mhz after Vcc rises 4.5V
clk_count := clk_count + 1;
nx_Stat <= Power_Up;
ELSIF(clk_count < (5000 * freq)) THEN --power-up complete
LCD_RS <= '0';
LCD_RW <= '0';
LCD_DATA <= "00110000";
nx_Stat <= Initialisation;
ELSE
clk_count := 0;
END IF;
When Initialisation =>
LCD_Busy <= '1';
clk_count := clk_count + 1;
IF(clk_count < (40 * freq)) THEN --function set, 39us
LCD_DATA <= "00111000"; --8bits, 2-line mode, display on, Font5x8 dots
LCD_EN <= '1';
LED_Test(1) <= '1';
nx_Stat <= initialisation;
ELSIF(clk_count < (60 * freq)) THEN --wait 20 us
LCD_DATA <= "00000000";
LCD_EN <= '0';
LED_Test(2) <= '1';
nx_Stat <= initialisation;
ELSIF(clk_count < (100 * freq)) THEN --display on/off control, 39us
LCD_DATA <= "00001000"; --display on, cursor off, blink off
LCD_EN <= '1';
LED_Test(3) <= '1';
nx_Stat <= initialisation;
ELSIF(clk_count < (120 * freq)) THEN --wait 20 us
LCD_DATA <= "00000000";
LCD_EN <= '0';
LED_Test(4) <= '1';
nx_Stat <= initialisation;
ELSIF(clk_count < (2120 * freq)) THEN --display clear 1.53ms
LCD_DATA <= "00000001";
LCD_EN <= '1';
LED_Test(5) <= '1';
nx_Stat <= initialisation;
ELSIF(clk_count < (2140 * freq)) THEN --wait 20 us
LCD_DATA <= "00000000";
LCD_EN <= '0';
LED_Test(6) <= '1';
nx_Stat <= initialisation;
ELSIF(clk_count < (2180 * freq)) THEN --entry mode set 39us
LCD_DATA <= "00000110"; --increment mode, entire shift off
LCD_EN <= '1';
LED_Test(7) <= '1';
nx_Stat <= initialisation;
ELSIF(clk_count < (2240 * freq)) THEN --wait 60 us
LCD_DATA <= "00000110";
LCD_EN <= '0';
LED_Test(8) <= '1';
nx_Stat <= initialisation;
ELSE --initialization complete
clk_count := 0;
LCD_Busy <= '0';
nx_Stat <= Choose;
END IF;
When Choose =>
CASE sel IS
when "00" => nx_Stat <= Word1;
when "01" => nx_Stat <= Word2;
when "10" => nx_Stat <= Word3;
when OTHERS => nx_Stat <= Choose;
End Case;
When Word1 => nx_Stat <= WriteData11;
--When Word2 => nx_Stat <= WriteData21;
--When Word3 => nx_Stat <= WriteData31;
When WriteData11 =>
LCD_RS <= '1'; LCD_RW <= '0';
LCD_DATA <= "01010110";
LED_Test(9) <= '1';
nx_Stat <= WriteData12;
When WriteData12 =>
LCD_RS <= '1'; LCD_RW <= '0';
LCD_DATA <= "01001000";
nx_Stat <= WriteData13;
When WriteData13 =>
LCD_RS <= '1'; LCD_RW <= '0';
LCD_DATA <= "01000100";
nx_Stat <= WriteData14;
When WriteData14 =>
LCD_RS <= '1'; LCD_RW <= '0';
LCD_DATA <= "01001100";
nx_Stat <= ReturnHome;
When Word2 => nx_Stat <= WriteData11;
When Word3 => nx_Stat <= WriteData11;
When ReturnHome =>
LCD_RS <= '1'; LCD_RW <= '0';
LCD_DATA <= "00000001";
nx_Stat <= Choose;
END CASE;
END PROCESS;
END Arch;I wonder if you can help me please. I have no idea where is the problem.
Thank you.
Best Regards.
↧
how to set weak pull up resistor
hi,
In:
assignments - settings - fitter settings - more fitter setting, there is item weak pull-up resistor
I set it on and off, i found it does work.
But In:
assignments - assignment editor.
I set value(ON) and enabled(YES) for weak pull -up resistor, i found it does not work.
the device is EPM240, i don't know what is the diffenence between the two ways to contol the weak pull up feature. would the two setting be conflicted?
In:
assignments - settings - fitter settings - more fitter setting, there is item weak pull-up resistor
I set it on and off, i found it does work.
But In:
assignments - assignment editor.
I set value(ON) and enabled(YES) for weak pull -up resistor, i found it does not work.
the device is EPM240, i don't know what is the diffenence between the two ways to contol the weak pull up feature. would the two setting be conflicted?
↧
↧
Partial Reconfiguration - JTAG Debug Mode
Hi all,
How should one instantiate a PR megafunction in order to be able to partially reconfigure the FPGA in JTAG Debug mode?
In the PR ip user guide https://www.altera.com/content/dam/a..._partrecon.pdf it is explained how to add PR programming files but not how to connect the IP.
JTAG mode is allowed for both internal and external host so what are the necessary steps to perform partial reconfiguration?
I hope someone who has done it before could help.
Regards,
Stef
How should one instantiate a PR megafunction in order to be able to partially reconfigure the FPGA in JTAG Debug mode?
In the PR ip user guide https://www.altera.com/content/dam/a..._partrecon.pdf it is explained how to add PR programming files but not how to connect the IP.
JTAG mode is allowed for both internal and external host so what are the necessary steps to perform partial reconfiguration?
I hope someone who has done it before could help.
Regards,
Stef
↧
Disable HAL UART drivers NIOS II.
Hi!
I've got custom make file. I want to disable some HAL drivers and use my driver implementation. I've tried this command
Unfortunately it removes altera_avalon_uart_regs.h from bsp project.
I've got custom make file. I want to disable some HAL drivers and use my driver implementation. I've tried this command
Code:
nios2-bsp hal $(BSP_FILE) $(SOPC_FILE) --cmd set_driver none uart↧
setup time and hold time
I want to know the setup time and hold time of the EP2AGX65..., but I can't find the parameter in its handbook, Who can tell me ? thank you!!
↧
quartus_hps with qspi in quad mode
It looks like quartus_hps expects the qspi flash to be in 1-bit command mode. Is there any support for other modes or a way to add support ? Once the flash gets switched into another mode, quartus_hps will no longer update the flash.
↧
↧
.sh file not runningArrow SoCkit
Hi,
I am trying to Running the Application on the Arrow SoCkit Board.
I am following below document, as I have Cyclone V terasic board
https://rocketboards.org/foswiki/pub...2014-11-25.pdf
While I have finished steps like Setting Up The Windows Environment, Compiling the Example Design(Hello world),
Que.1 : While I try to Building host program, I applied make command but Its not generating hello_world file in bin folder under hello_world folder.
Que 2: Running the Application on the Arrow SoCkit Board: when I command source ./init_opencl.sh, I got error:-sh: source: .init_opencl.sh: file not found in Putty, Even Putty is Showing same error for aocl version.
but I f I am writing aocl version command in terminal Window(cmd) its showing me all version information.
Could you please let me know, what kind of proble has it?
Thanks in advance.
I am trying to Running the Application on the Arrow SoCkit Board.
I am following below document, as I have Cyclone V terasic board
https://rocketboards.org/foswiki/pub...2014-11-25.pdf
While I have finished steps like Setting Up The Windows Environment, Compiling the Example Design(Hello world),
Que.1 : While I try to Building host program, I applied make command but Its not generating hello_world file in bin folder under hello_world folder.
Que 2: Running the Application on the Arrow SoCkit Board: when I command source ./init_opencl.sh, I got error:-sh: source: .init_opencl.sh: file not found in Putty, Even Putty is Showing same error for aocl version.
but I f I am writing aocl version command in terminal Window(cmd) its showing me all version information.
Could you please let me know, what kind of proble has it?
Thanks in advance.
↧
FGPA clock problem
Hi,
I designed a Cyclone IV EP4CE6E22N board and i used a 65 mhz crystal for clock input.
But Jtag Cable not found the device. Should I change crystal to 50 mhz one?
I designed a Cyclone IV EP4CE6E22N board and i used a 65 mhz crystal for clock input.
But Jtag Cable not found the device. Should I change crystal to 50 mhz one?
↧
MAX3512AFI256-10 programming issue
Dear Sir
I don't know who can solve this problem. Kindly direct this mail to the concerned person.
I am working in India. I bought 90 components of MAX3512AFI256-10. Igot some 12 components soldered on my 12 different boards.
Each board is having only one CPLD. While doing Programming/Verifying by using Quartus 8.0 or Quartus 5.0, i am getting 98% verified then error comes failed verifying device. Earlier the same boards with some difficulty after some attempts use to get programmed and verified, but now i am unable to program/verify them. I need those boards urgently to be used for integration but they are unusable.
I tried as per some of your websites suggested:
1. Use 10K between TMS nd VCC.
2. Use 1K between TCK and Gnd
3. Sometimes I used in between TDI and VCC also 10K resistor.
4. Sometimes I used 4.7K pull up for TDI, TCK, TMS.
5. sometimes I used 10K in between TCK and VCC
Nothing helped me to program/verify device, same error after 98%.
Only this lot components are giving trouble, earlier in other boards i used other lot components they never gave trouble. Kindly suggest how to program/verify them and make them useful. I am in deep urgency and i cannot send all 12 boards for rework. and what about remaining 78 components.
Regards
I don't know who can solve this problem. Kindly direct this mail to the concerned person.
I am working in India. I bought 90 components of MAX3512AFI256-10. Igot some 12 components soldered on my 12 different boards.
Each board is having only one CPLD. While doing Programming/Verifying by using Quartus 8.0 or Quartus 5.0, i am getting 98% verified then error comes failed verifying device. Earlier the same boards with some difficulty after some attempts use to get programmed and verified, but now i am unable to program/verify them. I need those boards urgently to be used for integration but they are unusable.
I tried as per some of your websites suggested:
1. Use 10K between TMS nd VCC.
2. Use 1K between TCK and Gnd
3. Sometimes I used in between TDI and VCC also 10K resistor.
4. Sometimes I used 4.7K pull up for TDI, TCK, TMS.
5. sometimes I used 10K in between TCK and VCC
Nothing helped me to program/verify device, same error after 98%.
Only this lot components are giving trouble, earlier in other boards i used other lot components they never gave trouble. Kindly suggest how to program/verify them and make them useful. I am in deep urgency and i cannot send all 12 boards for rework. and what about remaining 78 components.
Regards
↧
DE2-115 "Working" Webserver built with Quartus 15.1
After 2 weeks of beating head against the wall, I finally got the board to get DHCP from my router and display the webpages correctly.
Here is what I did to get it working in RGMII mode. The attached archive QAR project is setup for NET0 but if you want to use NET 1,
just change the define in the top level verilog.
ATTACHED FILES
1) Attached is the archive of my project. It does not include the software but I did not make any changes from the original generated RGMII webserver.
2) Open up the archive in Quartus , compile and program the SOF to the DE2-115. Then, in your workspace, create a new project and bsp. Chose the webserver for RGMII
and use the .sopcino file generated form Quartus. From there, everything should work fine with the names being correct.
CONVERSION
1) Quartus 12.1 is the last version that has both SOPC and QSYS together. I used 12.1 to convert the original files to a QSYS file.
2) I then opened up the project with Quartus 15.1
3) The old TSE does not work so I had to delete it and add in the new TSE
4) This is where my errors started, I had the wrong clock connections to the "receive_clock_connection" and "transmit_clock_connection".
Originally I started with the actual tx and rx clocks going to the phy. I always got the code to run but the DHCP timed out everything.
When I put these signals to the same clock as the CPU, everything came alive. The PCS clocks are the ones that need the phy clock. See
the top level verilog for connections.
CODE CHANGES IN QSYS OR THE SOFTWARE
1) When you create your project the names in QSYS needs to match what is in the generated webserver software. I found it easier
to change the names in QSYS . instead of "eth_mac" change it to "tse_mac" in qsys. change "cfi_flash" to "ext_flash". change "ledg" to "led_pio".
By doing this in qsys, it will match the generated software of the webserver.
Why? The generated webserver code does not match what was in the original DE2-115 SOPC/QSYS. They need to match name for name.
2) The base address of the CFI flash MUST be at 0x0 (we renamed it to ext_flash.) If you don't do this, the webserver can't find the HTML files written to flash. Set it to 0x0 and lock it down, then
regenerate the address as needed. This is pointed out as a limitation in the readme file where the top level code was generated from the nios tools. Example /software/rgmii_webserver where i named
my project rgmii_webserver.
Programming FLASH with ro_zipfs.zip
1) The webserver example looks forthis file at 0x100000. You can see this when you open up bsp_editor under "software packages". Use the flash programmer and set it up with the bsp you are using.
when you pull in the ro_zipfs.zip file, you will see some scripts kick up. Modify the Files for flash conversion location to 0x100000 in the gui. It is under "Flash Offset"
near the add and remove buttons.
Best of luck.
JC
Here is what I did to get it working in RGMII mode. The attached archive QAR project is setup for NET0 but if you want to use NET 1,
just change the define in the top level verilog.
ATTACHED FILES
1) Attached is the archive of my project. It does not include the software but I did not make any changes from the original generated RGMII webserver.
2) Open up the archive in Quartus , compile and program the SOF to the DE2-115. Then, in your workspace, create a new project and bsp. Chose the webserver for RGMII
and use the .sopcino file generated form Quartus. From there, everything should work fine with the names being correct.
CONVERSION
1) Quartus 12.1 is the last version that has both SOPC and QSYS together. I used 12.1 to convert the original files to a QSYS file.
2) I then opened up the project with Quartus 15.1
3) The old TSE does not work so I had to delete it and add in the new TSE
4) This is where my errors started, I had the wrong clock connections to the "receive_clock_connection" and "transmit_clock_connection".
Originally I started with the actual tx and rx clocks going to the phy. I always got the code to run but the DHCP timed out everything.
When I put these signals to the same clock as the CPU, everything came alive. The PCS clocks are the ones that need the phy clock. See
the top level verilog for connections.
CODE CHANGES IN QSYS OR THE SOFTWARE
1) When you create your project the names in QSYS needs to match what is in the generated webserver software. I found it easier
to change the names in QSYS . instead of "eth_mac" change it to "tse_mac" in qsys. change "cfi_flash" to "ext_flash". change "ledg" to "led_pio".
By doing this in qsys, it will match the generated software of the webserver.
Why? The generated webserver code does not match what was in the original DE2-115 SOPC/QSYS. They need to match name for name.
2) The base address of the CFI flash MUST be at 0x0 (we renamed it to ext_flash.) If you don't do this, the webserver can't find the HTML files written to flash. Set it to 0x0 and lock it down, then
regenerate the address as needed. This is pointed out as a limitation in the readme file where the top level code was generated from the nios tools. Example /software/rgmii_webserver where i named
my project rgmii_webserver.
Programming FLASH with ro_zipfs.zip
1) The webserver example looks forthis file at 0x100000. You can see this when you open up bsp_editor under "software packages". Use the flash programmer and set it up with the bsp you are using.
when you pull in the ro_zipfs.zip file, you will see some scripts kick up. Modify the Files for flash conversion location to 0x100000 in the gui. It is under "Flash Offset"
near the add and remove buttons.
Best of luck.
JC
↧
↧
ExclusiveAccess Exception while running OpenCL program on Altera FPGA
Hello Everyone,
I am trying to run a OpenCL Wordcount program on an Altera FPGA using Quartus Prime Pro 15.1.2 Edition, and while programming the FPGA using JTAG I am getting the following Exceptions:
ExclusiveAccess -> Trying to Acquire lock ==> lockname = kernel.process.sync.file.Altera => TID = 124
ExclusiveAccess -> Success Acquiring lock ==> lockname = kernel.process.sync.file.Altera => TID = 124
ExclusiveAccess -> Released lock ==> lockname = kernel.process.sync.file.Altera => TID = 124
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! This is getting generated continuously !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
ExclusiveAccess -> Exception: ==> sun.nio.ch.SharedFileLockTable.checkList(FileLockT able.java:255) => lockName = kernel.process.sync.file.Altera => TID = 123
ExclusiveAccess -> Exception: ==> sun.nio.ch.SharedFileLockTable.checkList(FileLockT able.java:255) => lockName = kernel.process.sync.file.Altera => TID = 123
ExclusiveAccess -> Exception: ==> sun.nio.ch.SharedFileLockTable.checkList(FileLockT able.java:255) => lockName = kernel.process.sync.file.Altera => TID = 123
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! This is getting generated continuously !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! After this the compiler hangs and program is not responding !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Does anyone have any idea why I might be getting this error?
Note: The OpenCL code has been generated from Java Code using a Compiler
Thanks in Advance,
Saurabh
I am trying to run a OpenCL Wordcount program on an Altera FPGA using Quartus Prime Pro 15.1.2 Edition, and while programming the FPGA using JTAG I am getting the following Exceptions:
ExclusiveAccess -> Trying to Acquire lock ==> lockname = kernel.process.sync.file.Altera => TID = 124
ExclusiveAccess -> Success Acquiring lock ==> lockname = kernel.process.sync.file.Altera => TID = 124
ExclusiveAccess -> Released lock ==> lockname = kernel.process.sync.file.Altera => TID = 124
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! This is getting generated continuously !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
ExclusiveAccess -> Exception: ==> sun.nio.ch.SharedFileLockTable.checkList(FileLockT able.java:255) => lockName = kernel.process.sync.file.Altera => TID = 123
ExclusiveAccess -> Exception: ==> sun.nio.ch.SharedFileLockTable.checkList(FileLockT able.java:255) => lockName = kernel.process.sync.file.Altera => TID = 123
ExclusiveAccess -> Exception: ==> sun.nio.ch.SharedFileLockTable.checkList(FileLockT able.java:255) => lockName = kernel.process.sync.file.Altera => TID = 123
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! This is getting generated continuously !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! After this the compiler hangs and program is not responding !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Does anyone have any idea why I might be getting this error?
Note: The OpenCL code has been generated from Java Code using a Compiler
Thanks in Advance,
Saurabh
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custom i2c
Just after a quick/general comment as I am a bit new to HDL.
I was struggling to get much over 30kHz on my i2c connection because my code on my Nios II processor was not handling the interrupts quick enough (1 interrupt per byte). I was holding the clock line down while it waiting for the ISR to be serviced, but the slave did not like this.
So, knowing the read and write always consists of 1 byte address and 2 bytes read or write, I modified the i2c HDL to do it all and just have an interrupt on the final stop. It seems to work fine at 900kHz now but the signals look like shark fins. I do sample rather than edge detect to read the data.
Is this how I should address the issue? Does anyone do this in practice?
regards,
Graham
I was struggling to get much over 30kHz on my i2c connection because my code on my Nios II processor was not handling the interrupts quick enough (1 interrupt per byte). I was holding the clock line down while it waiting for the ISR to be serviced, but the slave did not like this.
So, knowing the read and write always consists of 1 byte address and 2 bytes read or write, I modified the i2c HDL to do it all and just have an interrupt on the final stop. It seems to work fine at 900kHz now but the signals look like shark fins. I do sample rather than edge detect to read the data.
Is this how I should address the issue? Does anyone do this in practice?
regards,
Graham
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Bitwise logical NOT does NOT work!!
Anyhow, I have this Assembly assignment in which I have to count the number of binary 0's in a given hex value. It shows us how to count the 1's. I figured I'd try the NOT operator. It mentions the NOT operator in the InstructionSetReference.PDF, but it doesn't show us how to use it anywhere. I've tried everything I can think of, but all it does is return errors upon compilation with the Altera Monitor Program. When I try it like NOT r2 It gives this error: Error: unrecognised instruction not Compilation stopped. So, what's the deal with this? I go online, and everywhere they talk about the NOT instruction, that's how you use it. Perhaps some of you are familiar with this assignment. Here's the primary code: You see, in part 3, we have to count the 0's instead of the 1's. .text .global _start _start: ldw r2, NUM(r0) /* Loading hex value from the .word directive. I will use that hex number''s binary equivalent. */ mov r5, r0 /* Register is the counter, and increments by one, leaving the last incremented value to be the max number of consequtive 1''s. */ LOOP: beq r2, r0, END /* This loops until r2 no longer contains 1''s in its binary value. */ srli r3, r2, 0x1 /* Shifts binary value of r2 to the right and stores that shifted value into r3 */ and r2, r2, r3 /* ANDing the binary of r2 with the shifted binary of r3 so that all 1''s now ANDed with 0''s turn to 0, and then overwriting r2 with the new binary result */ addi r5, r5, 1 /* Incrementing counter by 1. */ br LOOP /* Relooping this until there are no more 1''s in the binary value of r2. */ END: br END NUM: .word 0x3fabedef /* This is the value who''s binary value will be assessed for max number of consecutive 1''s. */ NOTE: Sorry about how the message all compacted together. I can't seem to figure out how to make it space out properly in this message. It's like this doesn't honor any new lines
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Change size of Memory
Hi
I have a DDR3 Memory with the HMC. I have som important Data (Nios Instruction and Data) and some nonimportant Data (from external). Both process have to write into the RAM. I now realized, that this would be possible with the HMC sind I have there two Avalon Busses. But the problem is, both are pointing on the same Memory with different adresses.
I'm ok with different adresses. But the Problem is the following:
I want to use Avalon_0 for my NIOS and Avalon_1 for external Data. How do I set a maximum size of Avalon_0/1 so that they don't get overridden by the heap etc?
I have a DDR3 Memory with the HMC. I have som important Data (Nios Instruction and Data) and some nonimportant Data (from external). Both process have to write into the RAM. I now realized, that this would be possible with the HMC sind I have there two Avalon Busses. But the problem is, both are pointing on the same Memory with different adresses.
I'm ok with different adresses. But the Problem is the following:
I want to use Avalon_0 for my NIOS and Avalon_1 for external Data. How do I set a maximum size of Avalon_0/1 so that they don't get overridden by the heap etc?
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MIF and DSP Builder problem.
Hello, I am pretty new using dsp builder , I have the following problem : I would like to create a model with inputs data located in a MIF (memory initialization file) and I have no idea on how to proceed.
I am stuck, really. Thank you in advance for any help.
I am stuck, really. Thank you in advance for any help.
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Timing paths problem
hellow every body;
I made a timing analysis using altera time-quest timing analyzer, and i found that there are many paths that is not belongs to my design and report a timing problems. Is this can be happens in altera timing report. if this can be occurs. is it correct to set these paths as false nodes.
Thanks
I made a timing analysis using altera time-quest timing analyzer, and i found that there are many paths that is not belongs to my design and report a timing problems. Is this can be happens in altera timing report. if this can be occurs. is it correct to set these paths as false nodes.
Thanks
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New library using DSP Builder standard blockset
I have created new blocks inside a new library using DSP Builder standard blockset.
I have created and simulated a new model using these library and its blocks, but when I compiled the model the DSP Builder has created only simple VHDL project. I have opened the project at Quartus II and It is very small. The blocks wasn't compiled. I can't compile each block or full library because the compiler show one error.
What could be wrong?
I have created and simulated a new model using these library and its blocks, but when I compiled the model the DSP Builder has created only simple VHDL project. I have opened the project at Quartus II and It is very small. The blocks wasn't compiled. I can't compile each block or full library because the compiler show one error.
What could be wrong?
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