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Quartus Prime LIte - USB Blaster/USB Blaster II and compatibility with Windows 10

April 14, 2016, 8:41 am
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Hi
Is Quartus Prime LIte - USB Blaster/USB Blaster II and the associated drivers compatible with Windows 10? When I try to make any kind of JTAG connection to a MAX V using a USB Blaster I get a blue screen IRQL_NOT_LESS_OR_EQUAL error. What is the less costly path to programming and being able to use the Logic Analyzer functions in Quartus Prime Lite with MAX V CPLD with computer with a Windows 10 operating system?
If there are any questions or suggestions please let me know.
Roger50310
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Ethernet interface not working on Max10 eval board with Linux

April 14, 2016, 1:13 pm
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Hello,

I have an Altera MAX10 10M50 Rev C Development Kit that want to setup under Linux. I have found the instructions below to set it up: https://rocketboards.org/foswiki/Doc...tKitLinuxSetup

It is working mostly: the board boots, and I can access the shell via the UART. The problem I have is I can't get the ethernet port to work. The PHY seems to be up (one LED lighted and the connection status is "up" as seen from the PC.
I have tried forcing a static address with "ifconfig up" to no avail. I have attached the boot log for reference.

Any help will be greatly appreciated.

Best regards
Loic
Attached Files
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Arria V A5 FPGA fPLL and it's c-counters power supply

April 14, 2016, 6:27 pm
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Where can I find the document that describes which power supply does the FPLL and c-counters use in this Arria V FPGA board?
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question about the object dump file

April 14, 2016, 8:35 pm
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hi,
the *.objdump contains lots of useful information, such as how many space the code occupy
but i can not unstand it. is there any document can help me read the *.objdump file ?

thanks!

Sections:
Idx Name Size VMA LMA File off Algn
0 .entry 00000000 01040000 01040000 00013000 2**5
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .exceptions 00000220 00800020 00800020 00001020 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .text 0000f738 00800240 00800240 00001240 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
3 .rodata 0000032c 0080f978 0080f978 00010978 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
4 .rwdata 00001bfc 0080fca4 0080fca4 00010ca4 2**2
CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA
5 .bss 00000160 008118a0 008118a0 000128a0 2**2
ALLOC, SMALL_DATA
6 .qd_new_sdram_controller_0 00000000 00811a00 00811a00 00013000 2**0
CONTENTS
7 .onchip_flash_0_data 00000000 01040020 01040020 00013000 2**0
CONTENTS
8 .comment 00000023 00000000 00000000 00013000 2**0
CONTENTS, READONLY
9 .debug_aranges 00000c08 00000000 00000000 00013028 2**3
CONTENTS, READONLY, DEBUGGING
10 .debug_info 00022c5d 00000000 00000000 00013c30 2**0
CONTENTS, READONLY, DEBUGGING
11 .debug_abbrev 0000898a 00000000 00000000 0003688d 2**0
CONTENTS, READONLY, DEBUGGING
12 .debug_line 0000a8d3 00000000 00000000 0003f217 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_frame 00001ff0 00000000 00000000 00049aec 2**2
CONTENTS, READONLY, DEBUGGING
14 .debug_str 000036e9 00000000 00000000 0004badc 2**0
CONTENTS, READONLY, DEBUGGING
15 .debug_loc 00016ad4 00000000 00000000 0004f1c5 2**0
CONTENTS, READONLY, DEBUGGING
16 .debug_alt_sim_info 00000020 00000000 00000000 00065c9c 2**2
CONTENTS, READONLY, DEBUGGING
17 .debug_ranges 00001360 00000000 00000000 00065cc0 2**3
CONTENTS, READONLY, DEBUGGING
18 .thread_model 00000003 00000000 00000000 0006a084 2**0
CONTENTS, READONLY
19 .cpu 0000000f 00000000 00000000 0006a087 2**0
CONTENTS, READONLY
20 .qsys 00000001 00000000 00000000 0006a096 2**0
CONTENTS, READONLY
21 .simulation_enabled 00000001 00000000 00000000 0006a097 2**0
CONTENTS, READONLY
22 .sysid_hash 00000004 00000000 00000000 0006a098 2**0
CONTENTS, READONLY
23 .sysid_base 00000004 00000000 00000000 0006a09c 2**0
CONTENTS, READONLY
24 .sysid_time 00000004 00000000 00000000 0006a0a0 2**0
CONTENTS, READONLY
25 .stderr_dev 0000000e 00000000 00000000 0006a0a4 2**0
CONTENTS, READONLY
26 .stdin_dev 0000000e 00000000 00000000 0006a0b2 2**0
CONTENTS, READONLY
27 .stdout_dev 0000000e 00000000 00000000 0006a0c0 2**0
CONTENTS, READONLY
28 .sopc_system_name 00000002 00000000 00000000 0006a0ce 2**0
CONTENTS, READONLY
29 .quartus_project_dir 00000030 00000000 00000000 0006a0d0 2**0
CONTENTS, READONLY
30 .jdi 00003f0c 00000000 00000000 0006a100 2**0
CONTENTS, READONLY
31 .sopcinfo 000422d1 00000000 00000000 0006e00c 2**0
CONTENTS, READONLY
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Altera support request 11218245 - Reinstate the auk_ddr_hp_controller.vhd core li

April 15, 2016, 12:26 am
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Hi



I am getting the following error:



Warning: Can't generate programming files for project because design file "C:/Users/RKanjee/Documents/Pleora/iPort NTX/ntx_mini_pt01_pb0mx1_32tg_20205/ntx_mini_ip_offering_pkg/fpga/application/src/auk_ddr_hp_controller.vhd" is encrypted. It does not have license file support that allows generation of programming files.



I spoke to Pleora and they said I must ask you to reinstate the auk_ddr_hp_controller.vhd core license. Once I have that license I will be able to generate the SOF file in Quartus 8.1.



Thank you so much






Kind Regards



Ritesh Kanjee
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Custom component with GPIO Lite component generates 12006 error: undefined entity

April 15, 2016, 2:00 am
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Hello!
I've created a custom component in Qsys that includes a Altera GPIO lite component. The component is instansiated like this:

Code:
    inst_lvds_input : LVDS_INPUT
    PORT MAP
    (
        dout            => reg_lvds_in,
        pad_in(0)          => lvds_in_pos,
        pad_in_b(0)    => lvds_in_neg
  );
The component is then copied to the IP folder of another Quartus project and included into a Nios system. Qsys creates the system but when running the synthesis in Quartus the error message is:

Error (12006): Node instance "lvds_input_inst" instantiates undefined entity "altera_gpio_lite". Make sure that the required user library paths are specified correctly. If the project contains EDIF Input Files (.edf), make sure that you specified the EDA synthesis tool settings correctly. Otherwise, define the specified entity or change the calling entity. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/suppo...se/search.html and search for this specific error message number.

I've included the .qip file into my custom component in Qsys but didn't seem to make a difference as it shows up in the synthesis folder of the new Nios system.
Any ideas?
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Adjust I2C setup/hold timing in driver?

April 15, 2016, 4:20 am
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Anyone knows if it is possible to control the timing on I2C via the Linux i2c kernel driver (for the Cyclone V HPS)? Can SDA setup and hold timing be adjusted from userspace?

I have a problem using an external I2C device (which is connected through the FPGA fabric). Investigation of the signals shows that the SDA and SCL edges are toggling very close to each others. By physically placing your finger on the SDA line actually makes it work though, which leads me to suspect SDA hold violation.
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SDI transmitter serial output problem

April 15, 2016, 4:35 am
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I try to simulate SDI IP. I connect transmitter output to the receiver input. All work correctly, but sometimes serial output from SDI transmitter set to '0' or '1' for random time, and some time ago start work correctly again.
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PCIe Avalon ST Multifunction Simulation

April 15, 2016, 6:54 am
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Does any one used Altera Avalon ST Multifunction design, if so need help, in simulating the design.
The design example as well testbench support from altera is default for only single function.

Need to know, what all modifications to be done to the BFM part to support for the Multifunction.
Like Bar table Pointer control for different functions, Bar space allocation...

Thanks
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Verilog Question with Quartus.

April 15, 2016, 7:28 am
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I use verilog in my Quartus designs and like using the "parameter" statements. When I design a new module and use the statements everything works fine. My problem is when I change the value of the "parameter" it always keeps the last value I assigned.

If there a "Clean" compile or something like that I could do to get the new value to be recognized?

Thanks in advance for the help!
Brandon
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Max 10 Bank 8 set 1.2V ?

April 15, 2016, 8:54 am
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Hello,

I am working on a project with the Max 10, specifically using the Arrow Deca kit, which has a 10M50DAF484C6GES.

I am working on a video project, but I am having a simple pin assignment issue that I do not understand.
The Deca kit has a bank of 8 leds. According to the schematic and example projects, the leds are assigned to certain pins on bank 8 at 1.2V.
The example project succesfully compile the Start IO command (and the Start compile comand).

However, when I try to run Start IO with my project, I get errors (see attached) regarding the voltage level of bank 8.

As far as I can see, I've assigned the pins in Pin Planner exactly the same way they are in the example project (I've copied from mipi_hdmi project), and there is nothing else on Bank 8 except those LEDs.

I'm not sure why my project is having an issue with the voltage, and the mipi_hdmi is not.


Thank you for any advice,
or for any documentation or tutorials I should pursue to understand.

Attached Files
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Timing Optimized VHDL Code

April 15, 2016, 8:58 am
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I'm looking for coding guidelines, rules, online resources, examples, etc. on how to write VHDL code that helps me achieve a higher fmax for my FPGA design.

Does anybody have any good recommendations?
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Quartus Prime lite 15.1-Max10 Modelsim-Altera gate level simulation - infinite loop

April 15, 2016, 10:10 am
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Hi

I am trying to run Modelsim-Altera gate level simulation from
Tools -> Run simulation Tool -> Gate Level simualtion

Every time I try to run, it responds "Rerun the EDA Netlist Writer".
When I do re-run the netlist writer and try to re-run the simulation it responds with the same message.
I am able to run an RTL simulation runs just fine form the Tools menu.

That said, if I try to run RTL or Gate level simulations from the "Task" window, the simulations just hang !!!!

Anyone experienced similar issues (that they resolved)

Fionbarra
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Altera MAX10 10M50 Rev C hardware config with linux image

April 15, 2016, 2:45 pm
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Hello,

I have an Altera MAX10 10M50 Rev C Development Kit that want to setup under Linux based on the instructions below :
https://rocketboards.org/foswiki/view/Documentation/AlteraMAX1010M50RevCDevelopmentKitLinuxSetup

Anybody knows more about the hardware configuration there? How fast is the CPU clocked? Is it using cache?
That information will be handy for benchmarking versus other targets.

Thanks and best regards,
Loic
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Recommendations for a USB Blaster cable that has worked with Quartus on W 10

April 15, 2016, 4:59 pm
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Hi
Quartus Prime Lite is officially not ready for Windows 10 but I was fine using it that way until trying JTAG communications with a USB Blaster clone from Waveshare. Does anyone have a recommendation on a USB Blaster cable that has worked in a Windows 10 - Quartus Prime LIte environment for them? I have seem some posts on development boards with built in blasters working with Quartus - Windows 10. Would it be less problems and easier to get things to work right just to run things under Linux for the time being?
If there are any suggestions or questions please let me know.
Roger50310
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Cite Altera in my paper

April 15, 2016, 9:05 pm
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hello every body;
how to cite altera books and chapters in my paper. I need a formal altera citation for its editions.
Thanks.
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What dose local_size make for ddr2 hpcii?

April 16, 2016, 12:08 am
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As the topic, what dose local_size affect to ddr2 hpcii? For example, I configure local_wdata as 64bits, what is differences between local_size = 2 and local_size = 4?

According to the specification, local_size specifies the brust number of local_wdata and is allowed to set up to 1024.
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C2H Request !

April 16, 2016, 1:57 am
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Hello mates
I managed to develop my C code using nios II (Quartus 13.0 web edition), as far as I know I should accelerate the functions using HDL.
I thought there is a tool C2H compiler for Altera environment but I read that it has been abandoned and no longer used !!
If it is true How I can do the acceleration task ?!
If not how can I Start it !? Is there any version still support the C2H ?:confused:
Thnx for advance
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QSys - Exporting an AXI4-Lite interface

April 16, 2016, 5:23 pm
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It's reasonably trivial to export an AXI3 or AXI4 interface from QSys to external HDL by instantiating an AXI Bridge. However AXI4-Lite is not available as a protocol option on this component.
It is available (and exportable) on an AXI Slave Agent (or AXI Master Agent) component but I see no way to use these components without building your own Qsys memory mapped interconnect since they expose the Qsys packet interface as Avalon-ST.

Is there an obvious way I'm missing to expose an AXI4 Lite interface such that I can connect an AXi4-Lite slave in external HDL?

(Quartus 15.1/Arria10)
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Floating point addition in vhdl

April 17, 2016, 12:01 am
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Hii
I want to add 4 floating point no.what will be the result range.I am using
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
this package.For example if I want to add two floating point no then the result range is
C= A+ B -- range of C is (max(A'right ,B'right)+1 downto min (A'left ,B'left))
and it is working fine .But when I am doing
C = A+B+D+E;
What will be the new C range.
If I am following the same as above I am getting an error

"D:/214ee1411/vhdl codes/floatarith/mul_1test/fmul_1.vhd" Line 50: Expression has 11 elements ; expected 9
Please help me with this.
Thank you
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