Trying to interface HPS and FPGA for UART connection. Have done the interfacing using Qsys. The FPGA is Cyclone V DE1 SoC board. Compiling the code gives the following error. Error (35030): Partition "fpgahps_hps_0_hps_io_border:border" contains I/O cells that do not connect to top-level pins or have illegal connectivity Error (35032): Output port "fpgahps:u0|fpgahps_hps_0:hps_0|fpgahps_hps_0_hps_ io:hps_io|fpgahps_hps_0_hps_io_border:border|mem_d m[0]" on partition "fpgahps_hps_0_hps_io_border:border" must drive a top-level pin but is driving "" Error (35032): Output port "fpgahps:u0|fpgahps_hps_0:hps_0|fpgahps_hps_0_hps_ io:hps_io|fpgahps_hps_0_hps_io_border:border|mem_d qs[0]" on partition "fpgahps_hps_0_hps_io_border:border" must drive a top-level pin but is driving "fpgahps:u0|fpgahps_hps_0:hps_0|fpgahps_hps_0_hps_ io:hps_io|fpgahps_hps_0_hps_io_border:border|hps_s dram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_a cv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pa ds:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_ cyclonev:altdq_dqs2_inst|strobe_in"fpgahps is the name of the Qsys file.Can anybody help?
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Interface between HPS and FPGA for UART connection
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Question regarding VCCIO of arria V SX series
Hi ,
I am planning to use 5ASXMB3G4F40I5N in my current project.
I am using Bank 3A and 3C for 3.3V LVCMOS signals.
so my question is can i use bank 3D for LVDS signals.
if i can use it then what will be the VCCPD for group ( 3A,3B,3C,3D )?
thanks and regards
mahima satsangi
I am planning to use 5ASXMB3G4F40I5N in my current project.
I am using Bank 3A and 3C for 3.3V LVCMOS signals.
so my question is can i use bank 3D for LVDS signals.
if i can use it then what will be the VCCPD for group ( 3A,3B,3C,3D )?
thanks and regards
mahima satsangi
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↧
Custom IP Simulation in ModelSim
Hi all,
I have a Custom IP developed in VHDL and i am able to communicate with the NiosII Soft processor.But when i simulate the Nios II processor,the communication between the Nios II and the IP is not as expected.
If i watch the slave_write and chip_select ,then in between the consecutive slave_write pulses,there comes a slave_read pulse also.
How to avoid the slave_read pulses in between?
I have a Custom IP developed in VHDL and i am able to communicate with the NiosII Soft processor.But when i simulate the Nios II processor,the communication between the Nios II and the IP is not as expected.
If i watch the slave_write and chip_select ,then in between the consecutive slave_write pulses,there comes a slave_read pulse also.
How to avoid the slave_read pulses in between?
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SDRAM on NIOS2
Hello Everyone, I am trying to implement edge detection on nios2. so I have designed qsys system with nios2cpu-onchipmeory-jtag uart.
when i run my C code for edge detection i got errors like(1) undefined reference to fseek, fopen, fwrite and (2) .rwdata, .bss in not in the region of onchip.
To reduce first errors i did like. bsp editor-setting-common-HAL and unchecked small c library.
Now How can I reduce second errors.
To remove second errors i can use sdram but can anyone tell me how to use sdram for nios2 system ?
Thanks
when i run my C code for edge detection i got errors like(1) undefined reference to fseek, fopen, fwrite and (2) .rwdata, .bss in not in the region of onchip.
To reduce first errors i did like. bsp editor-setting-common-HAL and unchecked small c library.
Now How can I reduce second errors.
To remove second errors i can use sdram but can anyone tell me how to use sdram for nios2 system ?
Thanks
↧
Mapping inout to inout
Is is possible to map inout ports to other inout ports without resolving direction? The use case is for mapping local ports in a hierarchical design for abstraction naming only.
I have an eval kit with top-level "inout GPIO[35:0]". The kit has a daughter board with a pin-header which is mapped to specific GPIO pins by HW. I'd like to create a pinmap module mapping GPIO ports up against a "inout DSP[18:0]" port for abstraction, but without deciding direction on any of the signals yet. On top of this, the application will use the inout DSP port and the application determine the true direction of the pins. Is this possible with verilog?
I have an eval kit with top-level "inout GPIO[35:0]". The kit has a daughter board with a pin-header which is mapped to specific GPIO pins by HW. I'd like to create a pinmap module mapping GPIO ports up against a "inout DSP[18:0]" port for abstraction, but without deciding direction on any of the signals yet. On top of this, the application will use the inout DSP port and the application determine the true direction of the pins. Is this possible with verilog?
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↧
Altera ROM IP
Hello every body;
Can I use an "unregstered input" single port ROM using the Altera megawizard tool.
Thanks
Can I use an "unregstered input" single port ROM using the Altera megawizard tool.
Thanks
↧
SOC evaluation board for learning
I want to know which SOC evaluation board (Cyclone 5) that is good and inexpensive to get.
I hope that this board has very good and working tutorials to start and operate the SOC with DDR and Ethernet and SD_CARD, VGA and other things
I want to be able to run it with the free webedition of quartus.
Please recommend one.
I hope that this board has very good and working tutorials to start and operate the SOC with DDR and Ethernet and SD_CARD, VGA and other things
I want to be able to run it with the free webedition of quartus.
Please recommend one.
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Interrupt - not working with the ADC module IP
Hello, recently I've been doing some designs with the MAX10 FPGA and I've faced some issues in regards to the Sample Storage mode of operation that the ADC module IP from Altera gives.
The process that I'm developing is this one:
1 - disable the interrupt;
2 - register the ISR;
3 - enabling the interrupt - I don't know if the ADC starts the conversion at this point, cause I'm only enabling the interrupt, but I'm not invoking the "adc_start" API, which starts the ADC for the sequencer mode. :confused::confused::confused:
4 - in an infinite loop waiting for the interruption - however it never occurs.
I`ve read a couple of articles and codes that implement an interrupt that is triggered by a button from the board, but I couldn't find anything that is related with the modular ADC, and the documentation that Altera provides does not explain any coding process to get the sample storage mode working.
This is the code I'm running:
Thanks!
The process that I'm developing is this one:
1 - disable the interrupt;
2 - register the ISR;
3 - enabling the interrupt - I don't know if the ADC starts the conversion at this point, cause I'm only enabling the interrupt, but I'm not invoking the "adc_start" API, which starts the ADC for the sequencer mode. :confused::confused::confused:
4 - in an infinite loop waiting for the interruption - however it never occurs.
I`ve read a couple of articles and codes that implement an interrupt that is triggered by a button from the board, but I couldn't find anything that is related with the modular ADC, and the documentation that Altera provides does not explain any coding process to get the sample storage mode working.
This is the code I'm running:
Code:
#include<stdio.h>
#include "alt_types.h"
#include "system.h"
#include "altera_avalon_pio_regs.h"
#include "altera_modular_adc_sample_store_regs.h"
#include "altera_modular_adc_sequencer_regs.h"
#include "altera_modular_adc.h"
#include "sys/alt_irq.h"
#include "priv/alt_iic_isr_register.h"
#include "sys/alt_alarm.h"
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
static void adcInterrupt(void* context)
#else
static void adcInterrupt(void* context, alt_u32 id)
#endif
{
printf("Interrrrrrrrrruption!!!!!!!!!!!!");
adc_clear_interrupt_status(MODULAR_ADC_SAMPLE_STORE_CSR_BASE);
volatile int* edge_capture_ptr = (volatile int*) context;
//Interruption handler
}
int main(void){
printf("*** The ADC has started ***\n");
alt_u32 *adc_data_ptr;
alt_u32 line_in_data;
printf("*** Configure and start the sample_store config ***\n");
//Disable the interrupt
ALTERA_MODULAR_ADC_SAMPLE_STORAGE_IRQ_DISABLE(MODULAR_ADC_SAMPLE_STORE_CSR_BASE);
//Configuring the interrupt
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
alt_ic_isr_register (MODULAR_ADC_SAMPLE_STORE_CSR_IRQ_INTERRUPT_CONTROLLER_ID,
MODULAR_ADC_SAMPLE_STORE_CSR_IRQ,
adcInterrupt,
(void *)MODULAR_ADC_SAMPLE_STORE_CSR_BASE,
(void *)0);
#else
alt_irq_register (MODULAR_ADC_SAMPLE_STORE_CSR_IRQ, MODULAR_ADC_SAMPLE_STORE_CSR_BASE, adcInterrupt);
#endif
//enabling the interrupt
alt_ic_irq_enable(MODULAR_ADC_SAMPLE_STORE_CSR_IRQ_INTERRUPT_CONTROLLER_ID,
MODULAR_ADC_SAMPLE_STORE_CSR_IRQ);
adc_interrupt_enable(MODULAR_ADC_SAMPLE_STORE_CSR_BASE);
//adc_start(MODULAR_ADC_SEQUENCER_CSR_BASE);
printf("*** All enabled ***\n");
while(1){
adcSampleStorageIRQStatus=READ_ALTERA_MODULAR_ADC_SAMPLE_STORAGE_IRQ_STATUS(MODULAR_ADC_SAMPLE_STORE_CSR_BASE);
printf("IRQ Status: %d",adcSampleStorageIRQStatus);
adcInterruptAsserted=adc_interrupt_asserted(MODULAR_ADC_SAMPLE_STORE_CSR_BASE);
printf("Interrupt Asserted?: %d\n",adcInterruptAsserted);
}
return 0;
}↧
fpga choice
hello,
my FPGA is stratix II EP2S60F672C3N , but when i'd like to simulate on it with quartus II software, i just find on the device family EP2S60F672C3 and EP2S60F672C3ES.
please what choise i have to make ??
thank you an advance
my FPGA is stratix II EP2S60F672C3N , but when i'd like to simulate on it with quartus II software, i just find on the device family EP2S60F672C3 and EP2S60F672C3ES.
please what choise i have to make ??
thank you an advance
↧
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DDR3 memory with Uniphy is SLOW
I don't understand this controller. I have 4 things trying to access the DDR3 memory. I've tried it several different ways, and I seem to have trouble getting it go fast enough.
So to describe my system:
I have a Cyclone V with 1GB DDR3 memory @ 32 bits wide. I've been running it at 400MHz without data corruption, but have recently slowed it down to 350MHz because the FPGA couldn't quite keep up. At 350MHz, I calculate a total (albeit unachieveable) bandwidth of 22.4 Gbps.
Connected to it I have a VIP de-interlacer in HQ mode, a VIP frame buffer the ARM processor and some code of mine. I was struggling because occasionally the de-interlacer or frame buffer would stall, and then when I added my module on I found I couldn't read the data fast enough. I put the internal scope (Signal-Tap II) on my signals and noticed that data was coming in VERY slowly, even through a burst request. About one data word every 6 DDR clocks. Doesn't sound like a burst of data to me! So I wondered if my cycle was somehow being formed incorrectly, so added the Frame Buffer read signals to my internal scope. And that gets data at the same rate. The internal scope picture is attached, where the bottom 6 signals are from the Video Frame Buffer, and the upper 7 are from my code. The clock used to capture the data is actually the video clock, not the DDR half clock, but my "read_count" signal decrements by one for each "out_fifo_writereq" (which is a one cycle delayed readdatavalid signal).
So that I can get the avalon bus on the DDR memory connected to both Qsys and to my module outside Qsys, I use a Avalon-MM Pipeline Bridge to export the interface for me. The VFB also connects through a Pipeline Bridge (I copied this from a reference design example). The bridges are set to 32 or 512 words max burst size, and "Line wrap bursts" is off.
I have tried the DDR memory as a soft-controller, or as a MPFE Hard Memory controller, with very similar results.
I know that DDR memory has an overhead, but it's also designed to do burst transfers. So why is my burst data coming in so slowly? I must be getting something like 3.5 Gbps bandwidth.
Very frustrated.
Simon
So to describe my system:
I have a Cyclone V with 1GB DDR3 memory @ 32 bits wide. I've been running it at 400MHz without data corruption, but have recently slowed it down to 350MHz because the FPGA couldn't quite keep up. At 350MHz, I calculate a total (albeit unachieveable) bandwidth of 22.4 Gbps.
Connected to it I have a VIP de-interlacer in HQ mode, a VIP frame buffer the ARM processor and some code of mine. I was struggling because occasionally the de-interlacer or frame buffer would stall, and then when I added my module on I found I couldn't read the data fast enough. I put the internal scope (Signal-Tap II) on my signals and noticed that data was coming in VERY slowly, even through a burst request. About one data word every 6 DDR clocks. Doesn't sound like a burst of data to me! So I wondered if my cycle was somehow being formed incorrectly, so added the Frame Buffer read signals to my internal scope. And that gets data at the same rate. The internal scope picture is attached, where the bottom 6 signals are from the Video Frame Buffer, and the upper 7 are from my code. The clock used to capture the data is actually the video clock, not the DDR half clock, but my "read_count" signal decrements by one for each "out_fifo_writereq" (which is a one cycle delayed readdatavalid signal).
So that I can get the avalon bus on the DDR memory connected to both Qsys and to my module outside Qsys, I use a Avalon-MM Pipeline Bridge to export the interface for me. The VFB also connects through a Pipeline Bridge (I copied this from a reference design example). The bridges are set to 32 or 512 words max burst size, and "Line wrap bursts" is off.
I have tried the DDR memory as a soft-controller, or as a MPFE Hard Memory controller, with very similar results.
I know that DDR memory has an overhead, but it's also designed to do burst transfers. So why is my burst data coming in so slowly? I must be getting something like 3.5 Gbps bandwidth.
Very frustrated.
Simon
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connecting 4 GPIO pins to DAC using SPI interface
Hi.
I am new to altera and am interested in connecting a DAC via the GPIO pins on my development board. the DAC takes a data connection using the spi interface so I am wondering what is the best design to use. i currently have a 3-wire SPI slave with miso mosi, clock, and ssn wires exported (See attached photo). The DAC also requires a certain delay to be introduced. Do you know how to set this up in QSYS? Also, does anyone have sample code for this in NIOS II (eclipse)?
Best.
Leeor.
![]()
I am new to altera and am interested in connecting a DAC via the GPIO pins on my development board. the DAC takes a data connection using the spi interface so I am wondering what is the best design to use. i currently have a 3-wire SPI slave with miso mosi, clock, and ssn wires exported (See attached photo). The DAC also requires a certain delay to be introduced. Do you know how to set this up in QSYS? Also, does anyone have sample code for this in NIOS II (eclipse)?
Best.
Leeor.
↧
How to use SDRAM on DE2 board?
Hi,
I am working on a school project, and I am using FPGA to control a DAC(digital to analog converter) and a ADC (analog to digital converter) with SPI protocol.
Basically, I looked at the timing diagram of these two chips, and then I wrote Verilog and upload them into the FPGA. So, I got this part done. My FPGA can send binary codes to DAC, however, I have a huge lookup table which contains 2^16 of 16-Bit of binary codes need to send to DAC. So I think I will need to use SDRAM to store this lookup table. I did some search, and I found I can use DE2 control panel to upload my lookup table into the SDRAM, I tried it and it worked.
My question is, as I use DE2 control panel to upload my lookup table into SDRAM, and FPGA is ready to send binary codes to DAC, how can I let my verilog program
access these binary codes inside of SDRAM, and send them out? There are some people suggested to build a memory controller with Qsys, but I am not quite sure
how does it work. So any help would be appreciated!
Thanks,
Tao
I am working on a school project, and I am using FPGA to control a DAC(digital to analog converter) and a ADC (analog to digital converter) with SPI protocol.
Basically, I looked at the timing diagram of these two chips, and then I wrote Verilog and upload them into the FPGA. So, I got this part done. My FPGA can send binary codes to DAC, however, I have a huge lookup table which contains 2^16 of 16-Bit of binary codes need to send to DAC. So I think I will need to use SDRAM to store this lookup table. I did some search, and I found I can use DE2 control panel to upload my lookup table into the SDRAM, I tried it and it worked.
My question is, as I use DE2 control panel to upload my lookup table into SDRAM, and FPGA is ready to send binary codes to DAC, how can I let my verilog program
access these binary codes inside of SDRAM, and send them out? There are some people suggested to build a memory controller with Qsys, but I am not quite sure
how does it work. So any help would be appreciated!
Thanks,
Tao
↧
Shift left register using VHDL shift operator : sll trouble
Code:
library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;entity shift_reg isport( d :instd_logic; clk :instd_logic; rst_bar :instd_logic; q :outstd_logic_vector(7downto0));end shift_reg;architecture post_vhdl_08 of shift_reg isbeginprocess(clk, rst_bar)variable q_int :std_logic_vector(7downto0);beginif rst_bar ='0'then q_int :=(others=>'0');elsif rising_edge(clk)then q_int := q_int(6downto0)& d;endif; q <= q_int;endprocess;end post_vhdl_08;
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↧
Fitter error for LVDS o/p ports
Hi,
I am currently executing one vhdl code in quartus. I am getting the following error during fitter.
" Error (169175): Pin %signal% with LVDS I/O standard needs a differential output buffer which is not available on location AE13. "
Can you suggest some workaround for this .
Thanks and regards
Mahima Satsangi
I am currently executing one vhdl code in quartus. I am getting the following error during fitter.
" Error (169175): Pin %signal% with LVDS I/O standard needs a differential output buffer which is not available on location AE13. "
Can you suggest some workaround for this .
Thanks and regards
Mahima Satsangi
↧
custom Avalon MM master questions.
Hello All.
I am try make master for write my data to on_chip memory.
I am create component, make qsys design.
And now have to many i am think simple questions about next step.
Guys, please help me understand what assign signals in top level.
And exactly i am make all right or no.
In generated top-level i am pins for MM master for write data, possible not used pins for write to master or no?
And in all cases on-chip memory in my design not initialise if i am run - on-chip memory editor.
I am read all what possible and dont understand this.
new_component - its top level generated in qsys
mem.vhd - similar generated in qsys.
Thank you for help and you are time.
I am try make master for write my data to on_chip memory.
I am create component, make qsys design.
And now have to many i am think simple questions about next step.
Guys, please help me understand what assign signals in top level.
And exactly i am make all right or no.
In generated top-level i am pins for MM master for write data, possible not used pins for write to master or no?
And in all cases on-chip memory in my design not initialise if i am run - on-chip memory editor.
I am read all what possible and dont understand this.
new_component - its top level generated in qsys
mem.vhd - similar generated in qsys.
Thank you for help and you are time.
↧
DE2 Board, design loads but doesn't run
Hey
Currently trying to get my traffic lights system to run on the Altera DE2 board.
Its simulated and all working in the software however when i program it to the board it shows the initial state in the LED's but doesn't run. It doesn't respond to any change in inputs either.
Has anyone else came across this?
Im still new to all this so any advice would be very helpful!
Thanks
Currently trying to get my traffic lights system to run on the Altera DE2 board.
Its simulated and all working in the software however when i program it to the board it shows the initial state in the LED's but doesn't run. It doesn't respond to any change in inputs either.
Has anyone else came across this?
Im still new to all this so any advice would be very helpful!
Thanks
↧
Error (209053): Unexpected error in JTAG server -- error code 89
hello,
i installed Quartus II v 13.0sp, for 64 bit ubuntu 15.04.
and when i tried to run the toturial on the video below i don't obtain the final hardaware implementation on my fpga.
i tried to run this toturial on my FPGA wich is STRATIX II EP2S60F672C3N and all the steps of the simulations are succeful but when I'm trying to download my hardware configuration in my board and when I run the programmer there's a message from Quartus that said :
Error (209053): Unexpected error in JTAG server -- error code 89
Error (209012): Operation failed
What is this ? anyone knows what's going on?
thank you an advance!!
i installed Quartus II v 13.0sp, for 64 bit ubuntu 15.04.
and when i tried to run the toturial on the video below i don't obtain the final hardaware implementation on my fpga.
i tried to run this toturial on my FPGA wich is STRATIX II EP2S60F672C3N and all the steps of the simulations are succeful but when I'm trying to download my hardware configuration in my board and when I run the programmer there's a message from Quartus that said :
Error (209053): Unexpected error in JTAG server -- error code 89
Error (209012): Operation failed
What is this ? anyone knows what's going on?
thank you an advance!!
↧
↧
Error (209053): Unexpected error in JTAG server -- error code 89
hello,
i installed Quartus II v 13.0sp, for 64 bit ubuntu 15.04.
and when i tried to run the toturial on the video below i don't obtain the final hardaware implementation on my fpga.
i tried to run this toturial on my FPGA wich is STRATIX II EP2S60F672C3N and all the steps of the simulations are succeful but when I'm trying to download my hardware configuration in my board and when I run the programmer there's a message from Quartus that said :
Error (209053): Unexpected error in JTAG server -- error code 89
Error (209012): Operation failed
What is this ? anyone knows what's going on?
thank you an advance!!
i installed Quartus II v 13.0sp, for 64 bit ubuntu 15.04.
and when i tried to run the toturial on the video below i don't obtain the final hardaware implementation on my fpga.
i tried to run this toturial on my FPGA wich is STRATIX II EP2S60F672C3N and all the steps of the simulations are succeful but when I'm trying to download my hardware configuration in my board and when I run the programmer there's a message from Quartus that said :
Error (209053): Unexpected error in JTAG server -- error code 89
Error (209012): Operation failed
What is this ? anyone knows what's going on?
thank you an advance!!
↧
Interacting with LCD screen using Linux on board, Cyclone V FPGA,
Hello,
So, I'm still pretty much a beginner. I already viewed and ran an example design project for the I2C controller, this example interacts with the LCD screen, EEPROM and a few other things (https://www.altera.com/content/dam/a...-CV-GNU.tar.gz). I was able to run it on the board and it all works and was done through the USB Blaster port and configured from Eclipse. I want to try to only interact with the LCD only and building such a project from scratch and running an executable from the on board SD card through Linux. Is it possible to interact with the LCD from the SD card or does it only have to be done using the USB Blaster port. Also, the design example described makes use of Altera's HWLIB which is meant to interface to HPS hardware on board and the hiearchy and paths in the project are a mess, so i'm thus not sure about the way to go forward
So, I'm still pretty much a beginner. I already viewed and ran an example design project for the I2C controller, this example interacts with the LCD screen, EEPROM and a few other things (https://www.altera.com/content/dam/a...-CV-GNU.tar.gz). I was able to run it on the board and it all works and was done through the USB Blaster port and configured from Eclipse. I want to try to only interact with the LCD only and building such a project from scratch and running an executable from the on board SD card through Linux. Is it possible to interact with the LCD from the SD card or does it only have to be done using the USB Blaster port. Also, the design example described makes use of Altera's HWLIB which is meant to interface to HPS hardware on board and the hiearchy and paths in the project are a mess, so i'm thus not sure about the way to go forward
↧
HPS power consumption for Arria V SOC using PowerPlay Tool
Hello,
I am new to SOC design. We are using an Arria V SOC chip. I used the Quartus PowerPlay tool to estimate the various
supply currents required. I turned the USE HPS option on in the HPS calculator screen and set the CPU freq to 800MHz.
After running PowerPlay I see a VCC_HPS (1.1V core) current of only 30mA. This seems extremely low to me. I was expecting to see something > 1A at least.
Am I doing something wrong or making some bad assumption?
Thanks,
- Matt Knapp
I am new to SOC design. We are using an Arria V SOC chip. I used the Quartus PowerPlay tool to estimate the various
supply currents required. I turned the USE HPS option on in the HPS calculator screen and set the CPU freq to 800MHz.
After running PowerPlay I see a VCC_HPS (1.1V core) current of only 30mA. This seems extremely low to me. I was expecting to see something > 1A at least.
Am I doing something wrong or making some bad assumption?
Thanks,
- Matt Knapp
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