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using the uart core

April 26, 2016, 2:01 am
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Hi all,
I'm working on a project with max10 using nios2_gen, I try to send /receive informations from the max 10 to an esp 13 shield ( esp 8266) wifi, my skills in this domaine are limited, I start by making a system with Qsys this system contain a nios2_gen2 processor, RAM, I/O, a system ID and uart (RS232 serial port), I think that all what I'm gonna need for sending just a "Hello",now my problem is : I dont know what I have to do in Eclipse. please guys I need Help :oops::oops:.
Tkhs all.
Ayoub
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PLL Input for Cyclone V

April 26, 2016, 2:37 am
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Hi,
I had a problem with my design, so the only way to have a clock into my Cyclone V is to use a standard I/O, but i can't use this one in order to program my ALT PLL:
Error (11667): Input reference clock of fractional PLL pll2_GammaCam:inst5|pll2_GammaCam_0002:pll2_gammac am_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL must originate from a clock pin
Warning (179010): Source I/O is not placed onto a dedicated REFCLK input pin
Info (179012): Refclk input I/O pad XTIN_USB is placed onto PIN_H16


If any of you have an idea to work with it, it would be great.

Thank you
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How to get C program or openCL program to call or interact with a preconfigured FPGA

April 26, 2016, 4:38 am
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Hi,
I am new to FPGA's but I am wondering is it possible to to have a preconfigured FPGA already pre-built to do a particular task and have a C or C++ or openCL function call the FPGA and send and receive data to and from it. How would a scenario like this be done??
Appreciate any response. Thanks for your time.
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Logic utilization different between Partition Statistic and Resource Usage Summary

April 26, 2016, 7:47 am
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Hi,

Anyone knows why the SUM of logic utilization in Partition Statistic is NOT EQUAL to logic utilization in Resource Usage Summary in Fitter report? Bug?
52,714+64+81=52,859 not equal to 52,258.

Seen this in..
Quartus : 15.1
Device : Arria 10

HTML Code:
+---------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                              ;
+-------------------------------------------------------------+-----------------------+-------+
; Resource                                                    ; Usage                ; %    ;
+-------------------------------------------------------------+-----------------------+-------+
; Logic utilization (ALMs needed / total ALMs on device)      ; 52,258 / 427,200      ; 12 %  ;
; ALMs needed [=A-B+C]                                        ; 52,258                ;      ;

+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Partition Statistics                                                                                                                                ;
+-------------------------------------------------------------+-------------------------+--------------------+-----------------------+------------------------+
;Statistic                                                  ; Top                    ; dump_qxp:u_qxp    ; pzdyqx:nabboc        ; sld_hub:auto_hub      ;
+-------------------------------------------------------------+-------------------------+--------------------+-----------------------+------------------------+
; Logic utilization (ALMs needed / total ALMs on device)      ; 52714 / 427200 ( 12 % ) ; 0 / 427200 ( 0 % ) ; 64 / 427200 ( < 1 % ) ; 81 / 427200 ( < 1 % )  ;
; ALMs needed [=A-B+C]                                        ; 52714                  ; 0                  ; 64                    ; 81                    ;


Thanks,
OT
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Buiding Host program

April 26, 2016, 9:10 am
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Hi Guys,

I have make file for Hello world program.

I have Compiled the Example (Hello world), Now I am trying to use make comand and Its showing some library error. I open the make file to understand function of it.

and I have some question from it; Make file is assigning directories as below:


# Directories.
HOST_DIR := host
TARGET_DIR := bin
INC_DIRS := host/inc ../common/inc
LIB_DIRS := ../common/lib

Now my question is I havenot get Lib folder under Common folder. What could be reason for it?

Next question is like I am trying to compile the Vector_add example but I could not find make file for it. Do we really need make file or we can work without make file and generate host code file!!

Many thanks.
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Modelsim ERROR: No extended dataflow license exists

April 26, 2016, 9:52 am
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Hi guys i am running a project for some school work on quartus 15.1.

The compilation is ok, test bench is ok, but when i run modelsim appears this error:

Code:
# ERROR: No extended dataflow license exists
# do Microprocessador_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
#    vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim ALTERA vmap 10.4b Lib Mapping Utility 2015.05 May 27 2015
# vmap -modelsim_quiet work rtl_work
# Modifying /home/altera_lite/15.1/modelsim_ase/linuxaloem/../modelsim.ini
Vhdl files seems ok and i didnt find information about this error. :(

Help would be appreciated.

i didnt found anything about this error.
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Functional Sim of PLL broken, Quartus 15.1, Modelsim Starter 10.4b

April 26, 2016, 11:11 am
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Trying to functionally simulate PLL. Created the PLL with wizard, instantiated in verilog module.
I have compiled altera_mf.v, cycloneive_atoms.v into work. When vsim is invoked, all models
are found and loaded without error. Simulator is invoked with "-t ps".

I apply a clock to "inclk0_sig" and run for 100ns, then assert areset for 100ns, then deassert.
All outputs of PLL go "X". I also usually get an "iteration limit exceeded" error.

Just need a simple functional sim of the pll at this point. Help anyone?

Regards,
Roger
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Strange max 10 startup & non-volatile operation

April 26, 2016, 1:44 pm
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I have a PCB I made using the Max 10 10M16DAF256C8G dual supply series FPGA. I've observed some unexpected behaviors in terms of startup and non-volatile operation.

When programming the board with .sof file, everything worked okay the first time.

When programming the board with .pof file, I had to play around with tools -> options in the programming window and check the "initiate configuration after programming" box for the program to work. I'm also not 100% clear on whether it should be CFM, UFM, both, neither. According to this https://www.altera.com/content/dam/a...m10_config.pdf, it reads like either one will work to program into internal flash.

The problem is, the non-volatile behavior in both scenarios appears finicky. After the board is programmed, shut down, and restarted, I have to wait some random amount of time before it runs the program. Sometimes it takes maybe 5 seconds, other times it might take over an hour. The program is a simple program that turns on an LED and some other stuff. I don't know what might be causing this - if there is a certain power-up sequence this thing needs to see or what, maybe a setting somewhere in the programmer?
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Having a clock issue

April 26, 2016, 9:12 pm
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Im rather new to quartus and having trouble with one of my assignments.

I am designing a moore counter using 8 states and 3 jkff2 flip flops. Im almost certain that everything is wired up correctly but my simulation only shows the first state and almost seems that the circuit is not running the positive edge clock input.

Im not sure if i have to do anything to set up the clock or if simply creating an input with a controlled waveform is right but for some reason the clock won't shift into the second state.

Any suggestions or help would be greatly appreciated.

Thank you.
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Transmitting frames with Triple-Speed Ethernet MegaCore over Ethernet/RGMII

April 27, 2016, 12:30 am
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Hello,

I'm working with Quartus II, and had implemented the Triple-Speed Ethernet Megacore.
I simulate my design with ModelSim Altera Starter Edition.
My hardware is the BeMicro CV A9 with a Cyclone V FPGA and a Micrel Phy (KSZ9021RN).

I set the signals ff_tx_data, ff_tx_sop, ff_tx_eop and ff_tx_wren (from my PaketGenerator). And in my simulation, I got some signals on rgmii_out and tx_control (tx_control seems to be strange, isn't it?) Of course there is a 100-MHz-signal for ff_tx_clk and a 25-MHz-signal for tx_clk (I want to transmit at 100 MBit/s).

Is the simulation right?

And why my FPGA board doesn't work in reality and doesn't transmit any frames? (in the statistic counters of the TSE I got sometimes in register 0x1A one paket (but on my host I don't receive any paket), mostly I got in register 0x23 one paket - I send 10000 pakets in reallity and 10 pakets in simulation)

Look also at the photos I added to this request.

Kind regards, Matthias
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Update EPCS with IPcore ALTASMI_PARALLEL, then power restart, but FPGA can not work

April 27, 2016, 12:55 am
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Hi all,
Recently, I designed a project of cycloneIII with Quartus. I use Ethernet to receive configure data(.rpd format), and use ALTASMI_PARALLEL IPcore to update EPCS.
EPCS connected with FPGA via AS mode.

Typical procedures are:
1. Bluk erase EPCS;
2. Write configure data(.rpd format) to EPCS;
3. If write done then, read data from EPCS, define these data as data0;
4. Restart FPGA power.
Result: FPGA can not work with the new configure data.

Addition: I use USB Blaster to download .pof file via AS connector, and read the raw data from EPCS, defined as data1. Restart FPGA power, can work.
The data of .rpd defined as data2. data0, data1 and data2 are same.

So I was confused, the EPCS data are same, but FPGA don't work(update with ALTASMI_PARALLEL IPcore).
So I suppose something is changed in FPGA compared with USB Blaster way, but I cannot find any valuable thing in FPGA booting documents.

Could anyone tell me, what's wrong with my design? Thanks very much.
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Reconfigure entire FPGA without using external pin

April 27, 2016, 1:05 am
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Hello all,
i'm new in altera-forum and have problems with starting a reconfiguration process from inside a Cyclone 4-FPGA. The functionality i need is exactly the same as pulling the nconfig-pin low. But on my custom fpga-board there is no way to do this from fpga-logic. I've tried to use the reconfig-signal of remote-update-core but it seem there are some side-effects which lead to non-derterministic behavior after reconfiguration. The reconfiguration seems to work, but later there are sporadic additional reconfigurations without activating the reconfig-signal. I guess this is due to watchdog-timer. Is there another way of starting a reconfiguration process from inside an FPGA?

Thank you very much.
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Interpreting Optimization Report

April 27, 2016, 4:46 am
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Hello Everyone,

I need help interpreting the following optimization report. The basic structure of my kernel looks as follows:

Code:

while(true)
  read_channel(channel_0)
  Modify data
  write_channel(channel_1)
I get the following Optimization Report:

Code:
========================================================================================================================
|                                          *** Optimization Report ***                                                |
========================================================================================================================
| Kernel: data_reader                                                                                      | File:Ln  |
========================================================================================================================
| Loop while.body                                                                                          | [1]:167  |
|  Pipelined execution inferred.                                                                          |          |
|  Successive iterations launched every 10 cycles due to:                                                |          |
|                                                                                                          |          |
|      Data dependency on variable pkt_size_bytes                                                        | [1]:137  |
|      Largest Critical Path Contributors:                                                                |          |
|          54%: 'acl_stall_free_exit.c1.while.body.data_reader' Function Call Operation                  |          |
|          12%: 'acl_stall_free_entry.c1.while.body.data_reader' Function Call Operation                  |          |
|          10%: Icmp Operation                                                                            | [1]:137  |
|          10%: Lshr Operation                                                                            | [1]:215  |
========================================================================================================================
Line 167 has the while loop with condition.
Line 137 has a variable declaration.
Line 215 has a variable = array[index++] type assignment.


What does "54%: 'acl_stall_free_exit.c1.while.body.data_reader' Function Call Operation" mean? I cannot find any info online, nor in the Altera manuals about this.

My target is to lower the Initialization Interval.

Thanks for the help!
Monstrumus
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SignalTap transitional mode with Time base

April 27, 2016, 5:09 am
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Hi
Why doesn't Altera provide a transitional mode with time base .
meaning - when using transitional mode , altera should add internal time counter( or clock counter), so each sample taken by the signaltap will be accompanied by a time\clock counter.
when showing the output on the signaltap the time\clock counter will provide a time base for X axis (instead of samples).
:cool: (I'm waiting for this feature since altera introduced transitional mode at quatrus 6 ..)
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ALTPLL Megafunction simulation error

April 27, 2016, 5:14 am
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Hello All,

I am trying to simulate Altera_soft_LVDS megafunction using external PLL using ALTPLL megafunction. If I start simulation in Modelsim tool I am getting this type of errors in transcript

# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(110): Unresolved defparam reference to 'altpll_component' in altpll_component.bandwidth_type.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(111): Unresolved defparam reference to 'altpll_component' in altpll_component.clk0_divide_by.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(112): Unresolved defparam reference to 'altpll_component' in altpll_component.clk0_duty_cycle.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(113): Unresolved defparam reference to 'altpll_component' in altpll_component.clk0_multiply_by.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(114): Unresolved defparam reference to 'altpll_component' in altpll_component.clk0_phase_shift.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(115): Unresolved defparam reference to 'altpll_component' in altpll_component.clk1_divide_by.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(116): Unresolved defparam reference to 'altpll_component' in altpll_component.clk1_duty_cycle.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(117): Unresolved defparam reference to 'altpll_component' in altpll_component.clk1_multiply_by.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(118): Unresolved defparam reference to 'altpll_component' in altpll_component.clk1_phase_shift.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(119): Unresolved defparam reference to 'altpll_component' in altpll_component.compensate_clock.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(120): Unresolved defparam reference to 'altpll_component' in altpll_component.inclk0_input_frequency.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(121): Unresolved defparam reference to 'altpll_component' in altpll_component.intended_device_family.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(122): Unresolved defparam reference to 'altpll_component' in altpll_component.lpm_hint.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(123): Unresolved defparam reference to 'altpll_component' in altpll_component.lpm_type.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(124): Unresolved defparam reference to 'altpll_component' in altpll_component.operation_mode.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(125): Unresolved defparam reference to 'altpll_component' in altpll_component.pll_type.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(126): Unresolved defparam reference to 'altpll_component' in altpll_component.port_activeclock.
#
# Region: /lvds_transmitter/DUT_2
# ** Error: (vsim-10000) D:/VISH_WORKSPACE/Projects/Waveform_Generator/LVDS/pll_alt.v(127): Unresolved defparam reference to 'altpll_component' in altpll_component.port_areset.
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install OpenCL RTE in custom Linux in DE1-SoC

April 27, 2016, 6:03 am
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Hello everybody,

I am using DE1-SoC to implement an application, I have used buildroot and linux-socfpga, to build my custumized linux.
It runs well, without problem.

Now I want to add OpenCL RTE to my linux, to accelerate my application.

what are the steps to do that?

Thanks
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Quartus Prime Arria 10 synthesis and PC memory utilization

April 27, 2016, 7:30 am
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I'm just starting to play with Quartus Prime (15.1.2)

I have a legacy Stratix V design that I've ported to Arria 10.

After kicking off synthesis, Quartus eventually spawns 7 instances of quartus_syn.exe which mostly allocate around 17 GB RAM (as listed in the "Commit" column in Windows resource monitor, which I believe represents total virtual memory allocated), but one of the seven allocates 42 GB, so the total is around 140 GB. My PC is Win7, 12 core @ 3.3 GHz, 32 GB RAM, with an additional 120 GB (!) pagefile reserved on the drive containing the Quartus program.

Altera recommends up to 48 GB RAM for Arria 10. I'm using all the default synthesis options.

Is it normal for Quartus Prime to use up this much memory and spawn this many processes during synthesis? I didn't have any trouble routing this design on Stratix V with Quartus 13.1. The design does contain a very large qsys component, which I've also regenerated.

Are there synthesis options that can reduce memory utilization in Quartus Prime?

Ultimately we plan to buy a beefier machine to do FPGA routes and I want to get a sense of real memory requirements...so that's my focus for now.

Thanks,
Tom
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Help with my LCD Controller

April 27, 2016, 12:36 pm
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Hello everyone,

my code of lcd controller compile well and the simulation in modelsim work well. but when I send it to my board. I see nothing. I dont know where is the mistake.
Here is the code ( I dont like to show the entire code :( )

Code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY LCD_Controller IS
  PORT(
    CLK          : IN    STD_LOGIC;
    RST          : IN    STD_LOGIC;
    Sel          : IN    STD_LOGIC_VECTOR (1 downto 0) := "00" ;
    LCD_busy    : OUT  STD_LOGIC := '1';
    POWER_ON    : OUT  STD_LOGIC;
    LCD_RW      : OUT  STD_LOGIC; 
    LCD_RS      : OUT  STD_LOGIC;
    LCD_EN      : OUT  STD_LOGIC;
    LED_Test    : OUT  STD_LOGIC_VECTOR (9 downto 0);
    LCD_DATA    : OUT  STD_LOGIC_VECTOR (7 DOWNTO 0));
END LCD_Controller;

ARCHITECTURE Arch OF LCD_Controller IS

  TYPE CONTROL IS(Power_Up, Initialisation, ReturnHome,
                        Choose, Word1, Word2, Word3,
                        WriteData11, WriteData12, WriteData13, WriteData14 );
  SIGNAL    state      : CONTROL;
  CONSTANT  freq      : INTEGER := 50; --system clock frequency in MHz 50
BEGIN

  Power_ON <= '1';

  PROCESS(CLK,RST)
 
    VARIABLE CLK_count : INTEGER := 0;
   
  BEGIN
  --reset
  IF(RST = '0') THEN
    state <= power_up;
     
  ELSIF(CLK'EVENT and CLK = '1') THEN
   
      CASE state IS
       
        --wait 50 ms to ensure Vdd has risen and required LCD wait is met
        WHEN power_up =>
                IF(clk_count < (30000 * freq)) THEN 
                clk_count := clk_count + 1;
                state <= Power_Up;
               
                ELSIF (clk_count < (30010 * freq)) THEN
                    LCD_RS <= '0';
                    LCD_RW <= '0';
                    LCD_DATA <= "00110000";
                    clk_count := clk_count + 1;
                    state <= Power_Up;
               
                ELSIF (clk_count < (35010 * freq)) THEN
                    LCD_RS <= '0';
                    LCD_RW <= '0';
                    LCD_DATA <= "00000000";
                    clk_count := clk_count + 1;
                    state <= Power_Up;
               
                ELSIF (clk_count < (35020 * freq)) THEN
                    LCD_RS <= '0';
                    LCD_RW <= '0';
                    LCD_DATA <= "00110000";
                    clk_count := clk_count + 1;
                    state <= Power_Up;
               
                ELSIF (clk_count < (35220 * freq)) THEN
                    LCD_RS <= '0';
                    LCD_RW <= '0';
                    LCD_DATA <= "00000000";
                    clk_count := clk_count + 1;
                    state <= Power_Up;
               
                ELSIF (clk_count < (35230 * freq)) THEN
                    LCD_RS <= '0';
                    LCD_RW <= '0';
                    LCD_DATA <= "00110000";
                    clk_count := clk_count + 1;
                    state <= Power_Up;

                ELSIF(clk_count < (55000 * freq)) THEN    --power-up complete
                    LCD_RS <= '0';
                    LCD_RW <= '0';
                    LCD_DATA <= "00000000";
                      clk_count := clk_count + 1;
                    state <= Power_Up;
                ELSE
                    clk_count := 0;
                    state <= Initialisation;
                END IF;
         
        --cycle through initialization sequence 
        WHEN Initialisation =>
          LCD_Busy <= '1';
          clk_count := clk_count + 1;
          IF(clk_count < (40 * freq)) THEN      --function set, 39us
            LCD_RS <= '0';
                LCD_RW <= '0';
                LCD_EN <= '1';
                LCD_DATA <= "00111000";      --8bits, 2-line mode, Font5x8 dots
                LED_Test(1) <= '1';
            state <= initialisation;
           
          ELSIF(clk_count < (60 * freq)) THEN    --wait 20 us
                LCD_RS <= '0';
                LCD_RW <= '0';
                LCD_EN <= '0';
                LCD_DATA <= "00000000";
                LED_Test(2) <= '1';
                state <= initialisation;
           
          ELSIF(clk_count < (100 * freq)) THEN    --display on/off control, 39us
            LCD_RS <= '0';
                LCD_RW <= '0';
                LCD_EN <= '1';
                LCD_DATA <= "00001000";      --display off, cursor off, blink off         
                LED_Test(3) <= '1';
            state <= initialisation;
           
            ELSIF(clk_count < (120 * freq)) THEN  --wait 20 us
            LCD_RS <= '0';
                LCD_RW <= '0';
                LCD_EN <= '0';
                LCD_DATA <= "00000000";
                LED_Test(4) <= '1';
            state <= initialisation;
           
          ELSIF(clk_count < (2120 * freq)) THEN  --display clear 1.53ms
            LCD_RS <= '0';
                LCD_RW <= '0';
                LCD_EN <= '1';
                LCD_DATA <= "00000001";
                LED_Test(5) <= '1';
            state <= initialisation;
            ELSIF(clk_count < (2140 * freq)) THEN  --wait 20 us
            LCD_RS <= '0';
                LCD_RW <= '0';
                LCD_EN <= '0';
                LCD_DATA <= "00000000";
                LED_Test(6) <= '1';
            state <= initialisation;
           
          ELSIF(clk_count < (2180 * freq)) THEN  --entry mode set 39us
            LCD_RS <= '0';
                LCD_RW <= '0';
                LCD_EN <= '1';
                LCD_DATA <= "00000110";      --increment mode, entire shift off
                LED_Test(7) <= '1';
            state <= initialisation;
           
          ELSIF(clk_count < (2240 * freq)) THEN  --wait 60 us
            LCD_RS <= '0';
                LCD_RW <= '0';
            LCD_EN <= '0';
                LCD_DATA <= "00000000";
                LED_Test(8) <= '1';
            state <= initialisation;
           
          ELSE                                  --initialization complete
            clk_count := 0;
            LCD_Busy <= '0';
            state <= Choose;
          END IF;   
 
       
       
          WHEN Choose =>
            CASE sel IS
                WHEN "00" => state <= Word1;
                  WHEN "01" => state <= Word2;
                  WHEN "10" => state <= Word3;
                  WHEN OTHERS => state <= Choose;
            End Case;

          WHEN Word1 => state <= WriteData11;
   
          --WHEN Word2 => state <= WriteData21;
   
          --WHEN Word3 => state <= WriteData31;
         
           
          WHEN WriteData11 =>
                IF(clk_count < 10 )THEN
                    LCD_RS <= '1'; LCD_RW <= '0';
                    LCD_DATA <= "01010110";
                    clk_count := clk_count +1;
                    state <= WriteData11;
                ELSIF(clk_count < 30)THEN
                      LCD_RS <= '0'; LCD_RW <= '0';
                      LCD_DATA <= "00000000";
                      clk_count := clk_count +1;
                      state <= WriteData11;
                ELSE
                    state <= WriteData12;
                END IF;
               
          WHEN WriteData12 =>
                IF(clk_count < 40)THEN
                    LCD_RS <= '1'; LCD_RW <= '0';
                    LCD_DATA <= "01001000";
                    clk_count := clk_count +1;
                    state <= WriteData12;
                ELSIF(clk_count < 60)THEN
                      LCD_RS <= '0'; LCD_RW <= '0';
                      LCD_DATA <= "00000000";
                      clk_count := clk_count +1;
                      state <= WriteData12;
                ELSE
                      state <= WriteData13;
                END IF;
               
          WHEN WriteData13 =>
                IF(clk_count <= 70)THEN
                    LCD_RS <= '1'; LCD_RW <= '0';
                    LCD_DATA <= "01000100";
                    clk_count := clk_count +1;
                    state <= WriteData13;
                elsIF(clk_count < 90)THEN
                        LCD_RS <= '0'; LCD_RW <= '0';
                        LCD_DATA <= "00000000";
                        clk_count := clk_count +1;
                        state <= WriteData13;
                ELSE
                    state <= WriteData14;
                END IF;
               
          WHEN WriteData14 =>
                IF(clk_count < 100)THEN
                      LCD_RS <= '1'; LCD_RW <= '0';
                    LCD_DATA <= "01001100";
                    clk_count := clk_count +1;
                    state <= WriteData14;
                ELSIF(clk_count < 120)THEN
                      LCD_RS <= '0'; LCD_RW <= '0';
                      LCD_DATA <= "00000000";
                      clk_count := clk_count +1;
                      state <= WriteData14;
                  ELSE
                    state <= ReturnHome;
                END IF;
               
                LED_Test(9) <= '1';
               
          WHEN Word2 => state <= WriteData11;
          WHEN Word3 => state <= WriteData11;
               
          WHEN ReturnHome =>
                IF(clk_count < 1600)THEN
                      LCD_RS <= '0'; LCD_RW <= '0';
                    LCD_DATA <= "00000010";
                    clk_count := clk_count +1;
                    state <= ReturnHome;
                ELSIF(clk_count < 1800)THEN
                          LCD_RS <= '0'; LCD_RW <= '0';
                        LCD_DATA <= "00000000";
                        clk_count := clk_count +1;
                ELSE
                clk_count := 0;
                state <= Choose;
                END IF;

      END CASE;   
   
  END IF;
  END PROCESS;
END Arch;
Thank you very much.
↧

Resource utilization is 0 when added qxp file as source file

April 27, 2016, 7:28 pm
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Hi Altera Gurus,

I included a .qxp file in my quartus design as source file (not set in Partition Planner) and instantiated it in Top-Level-design. After compilation, I noticed the its (dump_qxp:u_qxp) resource utilization is 0% in Fitter Partition Statistic report. Is this an expected case? Anyone?


HTML Code:

+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Partition Statistics                                                                                                                                ;
+-------------------------------------------------------------+-------------------------+--------------------+-----------------------+------------------------+
; Statistic                                                  ; Top                    ; dump_qxp:u_qxp    ; pzdyqx:nabboc        ; sld_hub:auto_hub      ;
+-------------------------------------------------------------+-------------------------+--------------------+-----------------------+------------------------+
; Logic utilization (ALMs needed / total ALMs on device)      ; 52714 / 427200 ( 12 % ) ; 0 / 427200 ( 0 % ) ; 64 / 427200 ( < 1 % ) ; 81 / 427200 ( < 1 % )  ;
; ALMs needed [=A-B+C]                                        ; 52714                  ; 0                  ; 64                    ; 81                    ;
;    [A] ALMs used in final placement [=a+b+c+d]            ; 52440 / 427200 ( 12 % ) ; 0 / 427200 ( 0 % ) ; 66 / 427200 ( < 1 % ) ; 96 / 427200 ( < 1 % )  ;
;        [a] ALMs used for LUT logic and registers          ; 47092                  ; 0                  ; 28                    ; 39                    ;
;        [b] ALMs used for LUT logic                        ; 3386                    ; 0                  ; 29                    ; 32                    ;
;        [c] ALMs used for registers                        ; 1772                    ; 0                  ; 9                    ; 25                    ;
;        [d] ALMs used for memory (up to half of total ALMs) ; 190                    ; 0                  ; 0                    ; 0                      ;
;    [B] Estimate of ALMs recoverable by dense packing      ; 737 / 427200 ( < 1 % )  ; 0 / 427200 ( 0 % ) ; 2 / 427200 ( < 1 % )  ; 15 / 427200 ( < 1 % )  ;
;    [C] Estimate of ALMs unavailable [=a+b+c+d]            ; 1011 / 427200 ( < 1 % ) ; 0 / 427200 ( 0 % ) ; 0 / 427200 ( 0 % )    ; 0 / 427200 ( 0 % )    ;
;        [a] Due to location constrained logic              ; 0                      ; 0                  ; 0                    ; 0                      ;
;        [b] Due to LAB-wide signal conflicts                ; 22                      ; 0                  ; 0                    ; 0                      ;
;        [c] Due to LAB input limits                        ; 41                      ; 0                  ; 0                    ; 0                      ;
;        [d] Due to virtual I/Os                            ; 948                    ; 0                  ; 0                    ; 0                      ;
;                                                            ;                        ;                    ;                      ;                        ;
; Difficulty packing design                                  ; Low                    ; Low                ; Low                  ; Low                    ;
;                                                            ;                        ;                    ;                      ;                        ;
; Total LABs:  partially or completely used                  ; 7693 / 42720 ( 18 % )  ; 0 / 42720 ( 0 % )  ; 12 / 42720 ( < 1 % )  ; 17 / 42720 ( < 1 % )  ;
;    -- Logic LABs                                          ; 7674                    ; 0                  ; 12                    ; 17                    ;
;    -- Memory LABs (up to half of total LABs)              ; 19                      ; 0                  ; 0                    ; 0                      ;
;                                                            ;                        ;                    ;                      ;                        ;
; Combinational ALUT usage for logic                          ; 98578                  ; 0                  ; 91                    ; 114                    ;
Thanks,
OT
↧

QSPI booting problem

April 27, 2016, 10:15 pm
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Hi,

I am working on arro cyclone v soc kit.I built preloader image with boot from qspi option enabled.I programmed qspi flash by using following command.

quartus_hps -c 1 -o PV -a 0 preloader-mkpimage.bin

on altera command shell it is displaying program and verification from flash is successful
.I changed BOOTSEL settings to boot from flash(BOOTSE[2:0]110]on board.
I am expecting some prints on uart console.console is not displaying any messages.pls help me how to boot preloader from the QSPI flash.
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