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MAX 10 Pin Questions

April 27, 2016, 10:37 pm
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Hello,

I am working on design using a Altera 10M50SC device and have a few questions regarding pin types.

First, this file https://www.altera.com/content/dam/a...10/10m50sc.pdf specifies no IO performance for pins 50,58,62 and 135. What is the IO performance of these pins?

Second, I have run into trouble with Cyclone V single-ended clock input pins where only the _p input could be used single ended. With this MAX10 device, can either the _p and _n of a clock input be used single-ended? May they *both* be used as different single-ended clocks at the same time? If one is used as a single-ended clock, may the other be used without restriction as general purpose IO?

Finally, similar to the question about clock inputs, are there any restrictions when using PLL_L_CLKOUTp and n as one or two single-ended clock outputs or single-ended clock output and the other IO?

Thanks,

Steve
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Epm240t100

April 28, 2016, 12:11 am
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Dear Sir

I want to do a boundary scan testing of Board which having a configuration as attach.
I am doing boundary scan testing since 2011. But I had never seen this type of design ever.
If anyone can give me a some idea how to do this it will be great help.

Please help me.

Best Regards
Nikhil
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Power on detection

April 28, 2016, 2:06 am
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Hello, please help me solving the issue.

I have FPGA (cyclone-3 based) module connected to another system. That system generates reset signal on power on, and FPGA translates this signal to its devices. But it did not work some times, and I found out why: when power is applied, system activates reset signal, at the same time FPGA starts configuration from EPCS device. However, it seems configuration takes longer than system has reset signal active, and when FPGA is "ready" reset time has already finished, and devices attached to FPGA were not reset properly ("reset" output pin of FPGA was tri-stated during config).

Of course there's option to solve it in hardware - put pull-down resistor onto FPGA "reset" output pin, and during configuration all devices will be in reset state.

Is there any way to solve this issue in FPGA configuration - e.g. detect the end of configuration so that FPGA can perform reset to its attached devices?

Please advise. Thank you!
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DDR3 SDRAM controller core

April 28, 2016, 2:33 am
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I am working on Cyclone V project (5CEFA5F23C8) and I have DDR3 SDRAM controller core instantiated.
I am getting hold violations for the DDR_DQ path. I have seen in the qsys that constraint scripts would be applied but not able to see those constraint scripts in sdc file. Does anybody know where these scripts are generated so that I can copy paste to my top sdc file.
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multiplication of unsigned and sfixed numbers

April 28, 2016, 7:43 am
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I am trying to multiply an unsigned number with sfixed number (0.703125). following are the code and errors:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
USE ieee.numeric_std.all;


entity tryproduct is
end tryproduct;


architecture Behavioral of tryproduct is (Line 11)
signal a : sfixed(0 downto -6);
signal k : sfixed(8 downto -6);
SIGNAL temp1: UNSIGNED (8 downto 0) := "101001001" ;


begin


a <= to_sfixed (0.703125,a);
k <= to_sfixed(temp1) * a; (Line 19)
end Behavioral;






Errors:
ERROR:HDLCompiler:432 - "G:/vhdlcodes/producttry/tryproduct.vhd" Line 19: Formal <arg> has no actual or default value.
ERROR:HDLCompiler:841 - "G:/vhdlcodes/producttry/tryproduct.vhd" Line 19: Expecting type integer for <temp1>.
ERROR:HDLCompiler:9 - "G:/vhdlcodes/producttry/tryproduct.vhd" Line 19: Found 0 definitions for operator "*".
ERROR:HDLCompiler:854 - "G:/vhdlcodes/producttry/tryproduct.vhd" Line 11: Unit <behavioral> ignored due to previous errors.




thanks in advance
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Programming Issue Connected to Tool / System Change

April 28, 2016, 9:36 am
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I have recently migrated from Quartus 13 on 32bit Windows Vista to Quartus 15 on 64bit Windows 7. I am working with DE2-115 development boards, extracting data from them over USB using FTDI UMFT1601A to connect to the PC. As of this tool/system change, when the FTDI daughter board is connected to the PC, Programmer no longer recognizes that a USB-Blaster device is connected to the computer.

The order of connection does not matter. The FTDI chip always overrides.
jtagconfig.exe report is consistent with the GUI.
Device Manager properly reports which devices are connected to the machine.
Altera took care of driver filename conflicts many years ago.

Any suggestions on how to resolve this problem are appreciated.
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Quartus Command Line Trial

April 28, 2016, 12:37 pm
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Hello,

I'm using Quartus 13 on a Linux server with no GUI support using command line scripts. I would like to try Quartus 15 before purchasing the license but I'm not able to start a 30-day trial without using the GUI. Is there a way to initiate a trial using the command line?

Thanks
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Why there is no device model for EPM1270GM256 in quartus?

April 28, 2016, 8:33 pm
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I am going to use the CPLD EPM1270GM256, but I cannot find EPM1270GM256 device in quartus.There is EPM1270M256,but not EPM1270GM256.How to solve this problem?
Wishing for your help!!Thank you
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altera v gt board

April 28, 2016, 11:58 pm
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can we use pin HSMA_TX_D_P0 to HSMA_TX_D_P16 of HSMC_A port of board Arria V GT as input pin. or it is fix fir transmitting pin

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Component TCL file in Qsys

April 29, 2016, 12:00 am
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Hi,

I have designed the component's TCL file. It has one avalon slave port and avalon master port. I want to read the Base Address of my Avalon Slave Port in TCL file.

When Qsys is generated, master port of another component will get connected to my Avalon Slave Port. How can I get the Base Address of this Slave Port?

Thanks in advance..

Regards,
Harsh.
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MAX 10 FPGA_ Device Selection Help

April 29, 2016, 1:48 am
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Hello All,
Does Max 10 FPGA series support Ethernet core?. I am thinking of using a max 10 FPGA part number - 10M50SFE144I7G....But, I couldn't find if I would be able to use an Ethernet core with it. Please advice.

Thanks,
Manoj
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problem using Jtagconfig and enableremote

April 29, 2016, 3:08 am
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Hi everyone,

I have been trying to use the jtagconfig tool to program and debug remotely a stratix IV FPGA plugged to a debian machine.
However, when launching the jtagconfig tool with the --enableremote <pass> flag, the tool gives me this error:

Error when setting password - Feature not implemented or unavailable under current execution privilege level

I have tried running the same tool in root but it didn't change anything.
I have search for similar cases on internet but couldn't find one, has anyone dealt with this problem before ?

Thank you in advance,

Best regards

Laurent.
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pins - component

April 29, 2016, 3:12 am
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Hello.
Can I physically (pin FPGA) use ports operator, which is used as an ingredient?
When I use the pin planner, I see ports only main entity. How to do it?

Thanks.
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PCIe IO BAR's limited to "Legacy Endpoints"

April 29, 2016, 12:39 pm
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I am looking to define an EP with a BAR defined as IO instead of memory inorder to test the IO / CNFG PCI ordering rules .

I thought it would be as easy as going into an existing design and re-defining the BAR type ... It appears the IO BAR type is only supported by "Legacy Endpoints" .

Does anyone know why this is or how to get around it ?

Thanks, Bob.
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Incremental Motor Encoder -- How Best to Count Transitions

April 29, 2016, 6:00 pm
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I need to count the transitions (high and low) of a incremental motor encoder.

I wrote a simple async counter, using only the encoder output signal as the my stimulus (i.e. always @ (posedge relEnc)) but it doesn't seem to work very well, especially at high speeds of the motor. Is there a way to know how fast I could operate this portion of the design? Like an fmax for the relative encoder speed?

Otherwise, to get better more accurate counts, should it be done synchronously - use the main system clock 100mhz, to monitor and count the transitions of the encoder clock?

Also, I must be blind, but I don't see an Altera LPM block for a simple counter! I wanted to experiment and see if my 'fmax' would be improved using an altera counter.
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Connect Bus Line to another Bus Line

April 30, 2016, 6:22 am
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I am doing universal shift register in quartus. The situation now is I want to connect Q[0] to data1[1], Q[1] to data1[2],... and so on. Is it possible to do that?
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Quartus web edition 10.0 timing

April 30, 2016, 11:29 am
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Is there any way to use the classic timing analyzer instead of TimeQuest in Quartus Web Edition 10.0? There is a message stating that classic timing will be disabled in future versions but I don't have a full license. Any way around this for a short period of time?
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Quartus Prime Lite SignalTap II Logic Analyzer usable with MAX V?

April 30, 2016, 12:59 pm
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Hi
In the spec sheet on the MAX V CPLD is says "You can debug your MAX V designs using In-System Sources and Probes Editor in the Quartus II software. This feature allows you to easily control any internal signaland provides you with a completely dynamic debugging environment." But when I try to use the SignalTap II Logic Analyzer in Quartus Prime on a MAX V through a USB Blaster clone I get the message "SignalTap II is not supported for the current device"
I am using Quartus Prime Lite running on Ubuntu Linux.
What am I missing?
If you have any questions or suggestions please let me know.
Thanks
Roger50310
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Errors when trying to create 24 hr clock in Quartus II using VHDL

April 30, 2016, 2:05 pm
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I am news to VHDL and trying to create a 24 hr clock with hours, minutes and seconds that outputs on the seven segment display but I am getting errors and have been unable to resolve them. Here is the code.

Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clocker is
    port (CLOCK_50: in std_logic;
            printer: in std_logic_vector(15 downto 0);
            enter: in std_logic_vector(3 downto 0);
            out1, out2,
            out3, out4,
            out5, out6,
            out7, out8 : out std_logic_vector(0 to 6));
end clocker;


architecture Behavior of clocker is
    component ring
    port (dividor, divisor : in std_logic_vector(3 downto 0);
            clock2, reset, inner, outer : in std_logic_vector(3 downto 0);
            p: out std_logic_vector(3 downto 0));
    end component;
   
    component printOut2
        port( digit : in std_logic_vector(3 downto 0);
                print : out std_logic_vector(0 to 6));
    end component;
   
    signal count: std_logic_vector(24 downto 0);
    signal h0, h1, m0, m1, s0, s1: std_logic_vector(3 downto 0);
    signal divh0: std_logic_vector(3 downto 0);
    signal sec0, sec1, min0, min1, hr0, hr1: std_logic;


begin
    process(CLOCK_50)
    begin   
        if (CLOCK_50'event and CLOCK_50 ='1') then
            count <= count + '1';
        end if;
    end process;
   
    sec0 <= '1' when (count = 0) else '0';
    secs0: ring port map ("0000", "1001", CLOCK_50, enter(3), '0', sec0, s0);
    sec1 <= '1' when (s0 = 9) and (sec0 = '1') else '0';
    secs1: ring port map ("0000", "0101", CLOCK_50, enter(3), '0', sec1, s1);
   
    min0 <= '1' when (s1 = 5) and (sec1 = '1') else '0';
    mins0: ring port map (printer(3 downto 0), "1001", CLOCK_50, enter(3), not enter(0), min0, m0);
    min1 <= '1' when (m0 = 9) and (min0 = '1') else '0';
    mins1 : ring port map(printer(7 downto 4), "0101", CLOCK_50, enter(3), not enter(0), min1, m1);
   
    hr0 <= '1' when (m1 = 5) and (min1 = '1') else '0';
    divh0 <= "0011" when (h1 = 2) else "1001";
    hrs0: ring port map(printer(11 downto 8), divh0, CLOCK_50, enter(3), not enter(0), hr1, h0);
    hr1 <= '1' when (((h1 = 2) and (h0 = 3)) or (h0 = 9)) and (hr0 = '1') else '0';
    hrs1 :ring port map (printer(15 downto 12), "0010", CLOCK_50, enter(3), not enter(0), hr1, h1);
    hrs1: ring port map (printer(15 downto 12), "0010", CLOCK_50, enter(3), not enter(0), hr1, h1);
   
    d7: printOut port map (h1, out8);
    d6: printOut port map (h0, out7);
    d5: printOut port map (m1, out6);
    d4: printOut port map (m0, out5);
    d3: printOut port map (s1, out4);
    d2: printOut port map (s0, out3);
    d1: printOut port map ("1111", out2);
    d0: printOut port map ("1111", out1);
   
end Behavior;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity ring is
    port (dividor, divisor : in std std_logic_vector(3 downto 0);
            clock2, reset, inner, outer : in std_logic_vector(3 downto 0);
            p: out std_logic_vector(3 downto 0));
end ring;


architecture Behavior of ring is
    signal count2: std_logic_vector(3 downto 0);
begin
    process(clock2)
    begin
        if (clock2 = '1' and clock2'event) then
            if (reset = '0') then
                count2 <= "0000";
            elsif (inner = '1') then
                count2 <= dividor;
            elsif (outer = '1') then
                if (count2 = divisor) then
                    count2 <= "0000";
                else
                    count2 <= count + '1';
                end if;
            end if;
        end if;
    end process;
    p <= count2;
end Behavior;


library ieee;
use ieee.std_logic_1164.all;


entity printOut2 is
        port( digit : in std_logic_vector(3 downto 0);
                print : out std_logic_vector(0 to 6));
end printOut2;


architecture Behavior of printOut2 is
begin
    process(digit)
    begin
        case(digit) is
            when "0000" => print <= "0000001";
            when "0001" => print <= "1001111";
            when "0010" => print <= "0010010";
            when "0011" => print <= "0000110";
            when "0100" => print <= "1001100";
            when "0101" => print <= "0100100";
            when "0110" => print <= "1100000";
            when "0111" => print <= "0001111";
            when "1000" => print <= "0000000";
            when "1001" => print <= "0001100";
            when others => print <= "1111111";
        end case;
    end process;
end Behavior;
The errors I get are:
Error (10476): VHDL error at clocker.vhd(42): type of identifier "CLOCK_50" does not agree with its usage as "std_logic_vector" type
Error (10381): VHDL Type Mismatch error at clocker.vhd(42): indexed name returns a value whose type does not match "std_logic_vector", the type of the target expression
Error (10316): VHDL error at clocker.vhd(42): character ''0'' used but not declared for type "std_logic_vector"
Error (10476): VHDL error at clocker.vhd(42): type of identifier "sec0" does not agree with its usage as "std_logic_vector" type





Please tell me where I am going wrong. Thanks!
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FPGA/CPU acceleration: Are companies using it?

May 1, 2016, 1:17 am
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Hi all,

There has been a lot of buzz about FPGAs to be used as accelerators for data centers (among others on Intel's acquisition of Altera). Which made me wonder: Are there any companies out there that have seriously adopted that methodology, except Microsoft's Catapult project? I'm not talking about companies offering solutions, and not academic research projects.

Really for the sake of curiosity, can anyone point at a big company that has FPGAs crunching data for them in a room full with hybrid processor/FPGA computers? Or even a not-so-big?

Thanks,
Andrew.
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