i have an array consisting of values in sfixed format (9 downto -6) with 100 values . i want to transfer it to a text file. can anyone please help ??
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writing an array to text file
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Cyclone V SoC, DE1-SoC Board. Ethernet and USB don't work with custom kernel
Hi,
I'm trying to build a custom Linux system on a DE1-SoC board by Terasic. The stock Linux works fine. Even with my own preloader and U-boot.
Currently I'm trying to build a custom Kernel. I need Kernel Version 4.5.2. I compiled the Kernel using socfpga_defconfig.
In addition to that I searched for a device tree for the DE1 SoC Board.
the Kernel is running and the SD card is working. However, USB and Ethernet aren't working.
I attached my Device-Tree-File. It includes the "standard" include files that come with the linux kernel.
the first Problem I have is the one with the Ethernet.
I added a custom mdio section to the gmac1 device because without it Linux couldn't detect the PHY.
My Ethernet config looks like that:
Now the problem:
Inside of Linux everything seems fine. I have a eth0 Network device that automatically detects link etc. when I plug in the LAN cable dmesg shows
I can assign a IP address to the interface as well. Even the MAC address configured in u-boot is set up correctly.
Despite all that, the interface isn't working at all.
I connected the DE1 SoC directly to an other PC. As soon as I start ping on the DE1 SoC the LEDs of the PC indicate that Ehternet traffic is present. But I can't view any data via Wireshark. I don't get it. It's like the Ethernet is sending with the wrong frequency. I just don't get it.
My second problem is the USB interface. As you can see in my dts-File, I'm just activating the module and leave everything as it is defined in the standard includes supplied with the kernel. I get following output when the board boots:
For me this seems correct. However, no USB device is detected when I connect it to the board. dmesg doesn't show anything.
If I boot with a connected USB-Device (USB Memory Stick) and unplug it. I get following dmesg message:
I'm also not able to identify the problem here.
I hope you can help me to get this thing working.
Thanks!
I'm trying to build a custom Linux system on a DE1-SoC board by Terasic. The stock Linux works fine. Even with my own preloader and U-boot.
Currently I'm trying to build a custom Kernel. I need Kernel Version 4.5.2. I compiled the Kernel using socfpga_defconfig.
In addition to that I searched for a device tree for the DE1 SoC Board.
the Kernel is running and the SD card is working. However, USB and Ethernet aren't working.
I attached my Device-Tree-File. It includes the "standard" include files that come with the linux kernel.
the first Problem I have is the one with the Ethernet.
I added a custom mdio section to the gmac1 device because without it Linux couldn't detect the PHY.
My Ethernet config looks like that:
Code:
&gmac1 {
status = "okay";
phy-mode = "rgmii";
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
txc-skew-ps = <2600>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <2000>;
/* CUSTOM Adaptations */
interrupt-parent = < &intc >;
address-bits = < 48 >;
micrel-ksz9021rlrn-clk-skew = < 0xA0E0 >;
micrel-ksz9021rlrn-rx-skew = < 0x0 >;
max-frame-size = <3800>;
/* Custom MDIO Block. Seems to work. stmmac now checks address of PHY */
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy1: ethernet-phy@0 {
/* No options here */
};
};
};Inside of Linux everything seems fine. I have a eth0 Network device that automatically detects link etc. when I plug in the LAN cable dmesg shows
Code:
[ 2387.294093] socfpga-dwmac ff702000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/txDespite all that, the interface isn't working at all.
I connected the DE1 SoC directly to an other PC. As soon as I start ping on the DE1 SoC the LEDs of the PC indicate that Ehternet traffic is present. But I can't view any data via Wireshark. I don't get it. It's like the Ethernet is sending with the wrong frequency. I just don't get it.
My second problem is the USB interface. As you can see in my dts-File, I'm just activating the module and leave everything as it is defined in the standard includes supplied with the kernel. I get following output when the board boots:
Code:
[ 1.663535] usb 1-1: new high-speed USB device number 2 using dwc2
[ 1.770992] random: init urandom read with 9 bits of entropy available
[ 1.875030] hub 1-1:1.0: USB hub found
[ 1.879051] hub 1-1:1.0: 2 ports detectedIf I boot with a connected USB-Device (USB Memory Stick) and unplug it. I get following dmesg message:
Code:
[ 26.152423] usb 1-1.2: USB disconnect, device number 3I hope you can help me to get this thing working.
Thanks!
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OpenCL SDK with time-limited Megafunction
Hello everyone.
Does OpenCL SDK allow to use time-limited evaluation version of Megafunctions? Because I have an odd problem.
I am using time-limited evaluation version of Triple-Speed-Ethernet Megafunction with OpenCL SDK 15.1 on Linux and a Cyclone V SoC.
When I compile my kernel, I have the error : "Error : Compiler Error, not able to generate hardware". The file "quartus_sh_compile.log" tells me that the compiler is unable to find the binary file "top.sof". However, it has generated a file named "top_time_limited.sof".
So I tried to trick the compiler by renaming "top_time_limited.sof" in "top.sof" and restarting the compilation. Now, the compiler finds this file.
But I still have the problem "Error : Compiler Error, not able to generate hardware". At the end of the log file, a different message is written :
Does OpenCL SDK allow to use time-limited evaluation version of Megafunctions? Because I have an odd problem.
I am using time-limited evaluation version of Triple-Speed-Ethernet Megafunction with OpenCL SDK 15.1 on Linux and a Cyclone V SoC.
When I compile my kernel, I have the error : "Error : Compiler Error, not able to generate hardware". The file "quartus_sh_compile.log" tells me that the compiler is unable to find the binary file "top.sof". However, it has generated a file named "top_time_limited.sof".
So I tried to trick the compiler by renaming "top_time_limited.sof" in "top.sof" and restarting the compilation. Now, the compiler finds this file.
But I still have the problem "Error : Compiler Error, not able to generate hardware". At the end of the log file, a different message is written :
Info: Running Quartus Prime Convert_programming_file
Info: Version 15.1.0 Build 185 10/21/2015 SJ Standard Edition
Info: Processing started: Mon May 2 09:39:12 2016
Info: Command: quartus_cpf -c -o bitstream_compression=on top.sof top.rbf
Info: Using INI file /home/hwt/altera/programs/eth_test/eth_test/device/bin/eth_test/quartus.ini
Info (210039): File top.sof contains one or more time-limited megafunctions that support the OpenCore Plus feature that will not work after the hardware evaluation time expires. Refer to the Messages window for evaluation time details.
Info (210040): SRAM Object File top.sof contains time-limited megafunction that supports OpenCore Plus feature -- Vendor: 0x6AF7, Product: 0x00BD
Error: Quartus Prime Convert_programming_file was unsuccessful. 0 errors, 0 warnings
Error: Peak virtual memory: 395 megabytes
Error: Processing ended: Mon May 2 09:39:13 2016
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Info: Error generating RBF file! ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.
Error: Flow compile (for project /home/hwt/altera/programs/eth_test/eth_test/device/bin/eth_test/top) was not successful
Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.
Info: Version 15.1.0 Build 185 10/21/2015 SJ Standard Edition
Info: Processing started: Mon May 2 09:39:12 2016
Info: Command: quartus_cpf -c -o bitstream_compression=on top.sof top.rbf
Info: Using INI file /home/hwt/altera/programs/eth_test/eth_test/device/bin/eth_test/quartus.ini
Info (210039): File top.sof contains one or more time-limited megafunctions that support the OpenCore Plus feature that will not work after the hardware evaluation time expires. Refer to the Messages window for evaluation time details.
Info (210040): SRAM Object File top.sof contains time-limited megafunction that supports OpenCore Plus feature -- Vendor: 0x6AF7, Product: 0x00BD
Error: Quartus Prime Convert_programming_file was unsuccessful. 0 errors, 0 warnings
Error: Peak virtual memory: 395 megabytes
Error: Processing ended: Mon May 2 09:39:13 2016
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Info: Error generating RBF file! ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.
Error: Flow compile (for project /home/hwt/altera/programs/eth_test/eth_test/device/bin/eth_test/top) was not successful
Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.
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Megafunction plugin missing
HI, i need help. i'm using Quartus II V9.0 and when i want to select megafunction the plug-in are missing. What should i do to solve this issue. attached is the picture.
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Error (12002): Port "iCursor_RGB_EN" does not exist in macrofunction "u1"
Hi guys! Please help me. I encountered this error while compiling. What should I do to solve this? I am trying to create a Sobel Edge Detection in DE1 Board.
Here is the part of the code which has the error.
Here is the part of the code which has the error.
Code:
VGA_Controller u1 ( // Host Side
.iCursor_RGB_EN(4'b0111),
.oAddress(mVGA_ADDR),
.oCoord_X(Coord_X),
.oCoord_Y(Coord_Y),
.iRed(mVGA_R),
.iGreen(mVGA_G),
.iBlue(mVGA_B),
// VGA Side
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC),
.oVGA_BLANK(VGA_BLANK),
// Control Signal
.iCLK(VGA_CTRL_CLK),
.iRST_N(DLY_RST_0) );
Reset_Delay u2 ( .iCLK(CLOCK_50),
.iRST(KEY[0]),
.oRST_0(DLY_RST_0),
.oRST_1(DLY_RST_1),
.oRST_2(DLY_RST_2) );
//camera module
CCD_Capture u3 ( .oDATA(mCCD_DATA),
.oDVAL(mCCD_DVAL),
.oX_Cont(X_Cont),
.oY_Cont(Y_Cont),
.oFrame_Cont(Frame_Cont),
.iDATA(rCCD_DATA),
.iFVAL(rCCD_FVAL),
.iLVAL(rCCD_LVAL),
.iSTART(startCAM),
.iEND(stopCAM),
.iCLK(CCD_PIXCLK),
.iRST(DLY_RST_1));
//convert raw data to RGB
RAW2RGB u4 ( .oRed(mCCD_R),
.oGreen(mCCD_G),
.oBlue(mCCD_B),
.oDVAL(mCCD_DVAL_d),
.iX_Cont(X_Cont),
.iY_Cont(Y_Cont),
.iDATA(mCCD_DATA),
.iDVAL(mCCD_DVAL),
.iCLK(CCD_PIXCLK),
.iRST(DLY_RST_1));
SEG7_LUT_8 u5 ( .oSEG0(HEX0),.oSEG1(HEX1),
.oSEG2(HEX2),.oSEG3(HEX3),
.oSEG4(HEX4),.oSEG5(HEX5),
.oSEG6(HEX6),.oSEG7(HEX7),
.iDIG({16'h0000,SADTemp}) ); //.iDIG({Frame_Cont}) ); //
//this is completely differnet now
// the ram is partitioned between two images
//specifically, image 1 is in the first 640*512 block
// image 2 is offset by h100000 (~the offset required
// for the blanking pixel clock cycles)
reg [31:0] pixcnt;
reg FRMA;
always @(posedge CCD_PIXCLK)
begin
if (~DLY_RST_1)
begin
pixcnt<=0;
FRMA<=0;
end
else if (sCCD_DVAL)
begin
if (pixcnt < ((640*512)-1))
pixcnt<=pixcnt+1;
else
begin
pixcnt<=0;
FRMA<=~FRMA;
end
end
end
Sdram_Control_4Port u6 ( // HOST Side
.REF_CLK(CLOCK_50),
.RESET_N(1'b1), //never reset
// FIFO Write Side 1 (image 1)
.WR1_DATA({6'b000000,sCCD_BW[9:0]}),
.WR1(sCCD_DVAL & FRMA),
//.WR1(sCCD_DVAL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(640*512),
.WR1_LENGTH(9'h100), //256
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(CCD_PIXCLK),
// FIFO Write Side 2 (image 2)
.WR2_DATA({6'h0,sCCD_BW[9:0]}),
.WR2(sCCD_DVAL & ~FRMA),
.WR2_ADDR(22'h100000),
.WR2_MAX_ADDR(22'h100000+640*512),
.WR2_LENGTH(9'h100),
.WR2_LOAD(!DLY_RST_0),
.WR2_CLK(CCD_PIXCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(SDRAM_READ_LOGIC), //.RD1(Read), //.RD1()
.RD1_ADDR(640*16), //16 bit offset is for the differing resolutions
.RD1_MAX_ADDR(640*496),
.RD1_LENGTH(9'h100),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(SDRAM_READ_CLOCK), //.RD1_CLK(VGA_CTRL_CLK) //.RD1_CLK()
// FIFO Read Side 2
.RD2_DATA(Read_DATA2),
.RD2(SDRAM_READ_LOGIC),
.RD2_ADDR(22'h100000+640*16),
.RD2_MAX_ADDR(22'h100000+640*496),
.RD2_LENGTH(9'h100),
.RD2_LOAD(!DLY_RST_0),
.RD2_CLK(SDRAM_READ_CLOCK),
// SDRAM Side
.SA(DRAM_ADDR),
.BA({DRAM_BA_1,DRAM_BA_0}),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM}),
.SDR_CLK(DRAM_CLK) );
//configures the I2C registers on the camera (gain, etc.)
//modified explosure to higher value
I2C_CCD_Config u7 ( // Host Side
.iCLK(CLOCK_50),
.iRST_N(KEY[1]),
.iExposure(SW[9:0]),
// I2C Side
.I2C_SCLK(CCD_SCLK),
.I2C_SDAT(CCD_SDAT) );
//modified to convert to black and white
Mirror_Col u8 ( // Input Side
.iCCD_R(mCCD_R),
.iCCD_G(mCCD_G),
.iCCD_B(mCCD_B),
.iCCD_DVAL(mCCD_DVAL_d),
.iCCD_PIXCLK(CCD_PIXCLK),
.iRST_N(DLY_RST_1),
// Output Side
.oCCD_BW(sCCD_BW),
.oCCD_DVAL(sCCD_DVAL),
//.oLED(LEDR)
);
wire [17:0] VGASRAM_ADDR;
wire [15:0] VGASRAM_DATA;
//performs block correlation and generates edges
sobel u9 ( .iReset(reset),
.iClock(CLOCK_50),
.oLED(LEDR),
//the images from the SDRAM
.oSDRAM_READ_CLOCK(SDRAM_READ_CLOCK), //data clock on the sdram (each cycle gets a new word)
.oSDRAM_READ_LOGIC(SDRAM_READ_LOGIC), //set high when data is wanted
.iSDRAM_IMAGE1(Read_DATA1), //data from image 1
.iSDRAM_IMAGE2(Read_DATA2), //data from image 2
//the output to the VGA
.oVGASRAM_ADDR(VGASRAM_ADDR), //address of VGA output SRAM (320x240)
.oVGASRAM_DATA(VGASRAM_DATA), //data for " "
.iVGA_OK_TO_WRITE(VGA_OK_TO_WRITE), //signal indicating it is OK to write to the SRAM
.iVGA_CTRL_CLK(VGA_CTRL_CLK),
.oStartEdgeDetect(startEdgeDetect), //ready signal for VGA
.isw(SW[9:0]) //threshold values
);
wire VGA_OK_TO_WRITE;
assign VGA_OK_TO_WRITE = (~VGA_VS | ~VGA_HS) & (~reset); //this will go high during blanking
reg lock;
always @ (posedge VGA_CTRL_CLK)
begin
if (reset) //synch reset assumes KEY0 is held down 1/60 second
begin
//clear the screen
addr_reg <= {Coord_X[9:1],Coord_Y[9:1]} ; // [19:0]
we <= 1'b0; //write some memory
data_reg <= 16'h0000; //write all zeros (black)
led <= 8'b11111111;
end
//modify display during sync and edge calculation is active
//data from sobel edge detection
else if (VGA_OK_TO_WRITE & startEdgeDetect)
begin
addr_reg <= VGASRAM_ADDR;
lock <= 1'b1;
data_reg <= VGASRAM_DATA;
we <= 1'b0;
led <= 8'b00001111;
end
//show display when not blanking,
//which implies we=1 (not enabled); and use VGA module address
else if (~VGA_OK_TO_WRITE)
begin
we <= 1'b1;
addr_reg <= {Coord_X[9:1],Coord_Y[9:1]} ;
lock <= 1'b0;
end
end
endmodule↧
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line follower using nios ii assembly
hii everyone, i need a quick help please :( please please i'am designing a line follower robot using fpga de2 board and nios ii assembly, can you help me giving me any help about the algorithm and how the program to be, knowing that iam using infrared sensor and the output of the sensors is interfaced with an ADC. HOW CAN I USE THE NIOS II ASSEMBLY TO READ FROM ADC AND HOW TO DO THE DECISION.THANK YOU IN ADVANCE AND PLEASE PLEASA HELP EVEN IF JUST WITH AN IDEA IAM REALLY DESPERATE.:(:(:(
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Library auk_dspip_lib not found
I use a FIR II IP Core to simulate a lowpass filter with two input channels in Modelsim SE 10.1a. The decimation factor of the filter is 2. I generate a project about filter in Quartus II 12.0 and then use Modelsim SE 10.1a to simulate the RTL founction of the filter. But it conn't compile successfully. The errors are as follows:
# ** Error: F:/hsf_files/sar/sar_new_20150727/IP/filt2_clken_ast.vhd(32): Library auk_dspip_lib not found.# ** Error: F:/hsf_files/sar/sar_new_20150727/IP/filt2_clken_ast.vhd(33): (vcom-1136) Unknown identifier "auk_dspip_lib".
#
# ** Error: F:/hsf_files/sar/sar_new_20150727/IP/filt2_clken_ast.vhd(36): VHDL Compiler exiting
Firstly, I open the file filt2_clken.v(the name of FIR II IP Core is filt2_clken). It instantiated a module,namely filt2_clken_ast_inst,by filt2_clken_ast. Then I open the file filt2_clken_ast.vhd. I found that it use a library,namely <auk_dspip_lib>. But I don't find this library.
Is there anybody who can help me?
# ** Error: F:/hsf_files/sar/sar_new_20150727/IP/filt2_clken_ast.vhd(32): Library auk_dspip_lib not found.# ** Error: F:/hsf_files/sar/sar_new_20150727/IP/filt2_clken_ast.vhd(33): (vcom-1136) Unknown identifier "auk_dspip_lib".
#
# ** Error: F:/hsf_files/sar/sar_new_20150727/IP/filt2_clken_ast.vhd(36): VHDL Compiler exiting
Firstly, I open the file filt2_clken.v(the name of FIR II IP Core is filt2_clken). It instantiated a module,namely filt2_clken_ast_inst,by filt2_clken_ast. Then I open the file filt2_clken_ast.vhd. I found that it use a library,namely <auk_dspip_lib>. But I don't find this library.
Is there anybody who can help me?
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simple pin to pin delay managing in Cyclone
Hi everybody,
I want to know just a simple thing. I'm going to use my FPGA as a bypass element for a bus.
Imagine, I have a couple of inputs "INPUT_1" and "INPUT_2", and I'm going to redirect to "OUTPUT_1" and "OUTPUT_2". There is no logic, there is no clocks, just a couple of input to output with the only FPGA pin buffers in the middle.
For me, it's not important the total delay introduced by the FPGA pins but it's critical the different delays between one couple to the other. Thus if one has, e.g., 5.000 ns delay the other must to have 5.000 ns and not 7, 8 o 10 ns delay. I think is clear.
The question is:
How can I manage this case in timequest? and /or how can I constraint it with timequest / quartus?
Thanks a lot!
Jordi
I want to know just a simple thing. I'm going to use my FPGA as a bypass element for a bus.
Imagine, I have a couple of inputs "INPUT_1" and "INPUT_2", and I'm going to redirect to "OUTPUT_1" and "OUTPUT_2". There is no logic, there is no clocks, just a couple of input to output with the only FPGA pin buffers in the middle.
For me, it's not important the total delay introduced by the FPGA pins but it's critical the different delays between one couple to the other. Thus if one has, e.g., 5.000 ns delay the other must to have 5.000 ns and not 7, 8 o 10 ns delay. I think is clear.
The question is:
How can I manage this case in timequest? and /or how can I constraint it with timequest / quartus?
Thanks a lot!
Jordi
↧
Performance counter report
Hey
I am running performance counter on my C code
My problem is that the report only show the result for section 1 !! (even if I change sections order it only show the first)
It should show 4 sections !
What could be the problem ?!
thnx
%%%%%%%%%%%%%%%%
perf_print_formatted_report((void *)PERFORMANCE_COUNTER_BASE,
ALT_CPU_FREQ,4,
"section_1",
"section_2",
"section_3",
"section_4");
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
--Performance Counter Report--
Total Time: 3.35524 seconds (335524437 clock-cycles)
+---------------+-----+-----------+---------------+-----------+
| Section | % | Time (sec)| Time (clocks)|Occurrences|
+---------------+-----+-----------+---------------+-----------+
|section_1 | 0.27| 0.00905| 905319| 1|
+---------------+-----+-----------+---------------+-----------+
|section_2 | 0| 0.00000| 0| 0|
+---------------+-----+-----------+---------------+-----------+
|section_3 | 0| 0.00000| 0| 0|
+---------------+-----+-----------+---------------+-----------+
|section_4 | 0| 0.00000| 0| 10175|
+---------------+-----+-----------+---------------+-----------+
I am running performance counter on my C code
My problem is that the report only show the result for section 1 !! (even if I change sections order it only show the first)
It should show 4 sections !
What could be the problem ?!
thnx
%%%%%%%%%%%%%%%%
perf_print_formatted_report((void *)PERFORMANCE_COUNTER_BASE,
ALT_CPU_FREQ,4,
"section_1",
"section_2",
"section_3",
"section_4");
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
--Performance Counter Report--
Total Time: 3.35524 seconds (335524437 clock-cycles)
+---------------+-----+-----------+---------------+-----------+
| Section | % | Time (sec)| Time (clocks)|Occurrences|
+---------------+-----+-----------+---------------+-----------+
|section_1 | 0.27| 0.00905| 905319| 1|
+---------------+-----+-----------+---------------+-----------+
|section_2 | 0| 0.00000| 0| 0|
+---------------+-----+-----------+---------------+-----------+
|section_3 | 0| 0.00000| 0| 0|
+---------------+-----+-----------+---------------+-----------+
|section_4 | 0| 0.00000| 0| 10175|
+---------------+-----+-----------+---------------+-----------+
↧
↧
Nios2 console output
Hello Everyone,
I am implementing edge detection using nios2. As an input , I have store my images as 128*128 array.
I have implemented sobel filter and as an output, I am expecting pixel values which i can read in matlab. My C program is working fine in any c compiler (like code blocks). When I am trying to run this c program on nios2, I am not getting any pixeles. If I try to run the same program using 15*15 or any small arrays, it is working and giving me output pixels.
Can anyone suggest me what should i do ?
Thanks
I am implementing edge detection using nios2. As an input , I have store my images as 128*128 array.
I have implemented sobel filter and as an output, I am expecting pixel values which i can read in matlab. My C program is working fine in any c compiler (like code blocks). When I am trying to run this c program on nios2, I am not getting any pixeles. If I try to run the same program using 15*15 or any small arrays, it is working and giving me output pixels.
Can anyone suggest me what should i do ?
Thanks
↧
NIOS II on DE2-115, can't download ELF
I'm new to the FPGA world and new to the NIOS II soft-processor. I've inherited a functioning project at work that implements the NIOS II and some C code on a DE2-115 board. I've got the directory structure and project files that were originally used to program the DE2-115, but need to be able to make changes to the C code built for the NIOS II. With the project compiled and the .sof programmed to the board, I'm unable to program the .elf file to the NIOS II using the USB blaster from the Eclipse SBT. Per several tutorials, I'm using the Run As -> NIOS II hardware option and getting "Launching test NIOS II Hardware configuration has encountered a problem. Downloading ELF Process failed." Can anyone shed some light on this? Thanks.
↧
Stratix iv GT General Purpose I/O's
I'm working on two projects, one with the DE0-Nano and Stratix iv GT boards. My project is to make a duobinary signal with the two boards. I was able to do so with the DE-Nano fairly easily, but I'm having trouble doing it with the Stratix iv board. I was told not to use the transceivers on the board, but instead use the general purpose user I/O header field because they act similar to the GPIO pins in the Nano. However, I see them all labeled only as J25 and not individually so I'm not able to make the correct pin assignments in the pin assignment editor. I need to activate two of those pins so I can connect them to a circuit I made and test the signal. Help is appreciated
↧
Issues with Help content not displaying on left window pane
New to this, so here is the issue I am experiencing:
-clicked on "search" option in the "Help" drop down menu on the Quartus II program
-on the Left window pane with the "Search" , "Contents", "Index", "Forums" and "Feedback" options, I am not getting anything in the list for "Contents" or "Index" which is a bummer Because I was just looking for the info on the "Project Navigator" for the Quartus II program, YES I am the Newbie here.... ALSO using the search feature brings up nothing... THANK you :)
-clicked on "search" option in the "Help" drop down menu on the Quartus II program
-on the Left window pane with the "Search" , "Contents", "Index", "Forums" and "Feedback" options, I am not getting anything in the list for "Contents" or "Index" which is a bummer Because I was just looking for the info on the "Project Navigator" for the Quartus II program, YES I am the Newbie here.... ALSO using the search feature brings up nothing... THANK you :)
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Net "VGA_B[0]", which fans out to "VGA_B[0]", cannot be assigned more than one value
Hi guys. What do you mean by the error? Error (12014): Net "VGA_B[0]", which fans out to "VGA_B[0]", cannot be assigned more than one value Error (12015): Net is fed by "GND"
Error (12015): Net is fed by "VGA_Controller:u1|oVGA_B[0]"
Please help. Thanks.
Error (12015): Net is fed by "VGA_Controller:u1|oVGA_B[0]"
Please help. Thanks.
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How to rum QCMD from cmd window for different quartus version
hii all,
i have three version of quartus installed with me , quartus 9 quartus 11.1 and quartus 12.1. this is because some old projects are done on these version and time to time bug fixatures require to use corresponding quartus version.
now when i am trying to open quartus from cmd by using command qcmd it only opens for quartus 11.1 but i want to open version 9 . searched many places for method to open qcmd for corresponding version when u have two or three diff version but never found a method.
plz reply if any of u have any reply.
i have three version of quartus installed with me , quartus 9 quartus 11.1 and quartus 12.1. this is because some old projects are done on these version and time to time bug fixatures require to use corresponding quartus version.
now when i am trying to open quartus from cmd by using command qcmd it only opens for quartus 11.1 but i want to open version 9 . searched many places for method to open qcmd for corresponding version when u have two or three diff version but never found a method.
plz reply if any of u have any reply.
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Problem with JTAG MAX 10
Is there anyone who is facing the same problem i am facing in MAX 10 JTAG? (see attachment). If anyone has any idea to solve this please let me know. I tried all sorts of way which has been shared in the forum regarding this. But nothing worked out. Please
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NMOS switch code
Hi, I'm being a total noob here and a dunce but I'll ask anyway. :) How come the vhdl code attached does not simulate properly. The syntax is correct and it compiles but the signal does not output on simulation. Please help and keep the roasting to a minimum. Thanks.
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SDC problem
hi,
My requriement is that:
There are two input signal, In_a, In_b, these two signals will be connected to clock and data (llike I2C). two output signal, Out_clock, Out_data.
Because the In_a could connect to clock or data, so i need write a module to identify which one(clock or data) will connet to In_a, then re-arrange the order and output the correct signal , i.e. Out_clock or Out_data.
the code is like this:
module Switch(input wire In_a, input wire In_b, input wire S, output wire Out_clock, output wire Out_data)
begin
assign Out_clock = S ? In_a : In_b;
assign Out_data = S ? In_b : In_a;
end
if S is connected to external pin, the maxmum frequency is 200Mhz.
if i write a module to generate control signal S by In_a and In_b, for example like this
module Identify( input wire In_a, input wire In_b, out reg S)
begin
//some statistic code to indetinfy .......
end
the maximu frequency is 30Mhz.
The problem is:
I want the signals from In_a and In_b to Out_clock and Out_data can run at 100Mhz. the module Identify will influence the frequency(tsu). I want to write a SDC file to optimize the maximu speed.
the Identify moule just generate signal S to pick up which one is clock. if the S is ready, it is latched and needn't changed again . the data can be discarded before the S is generated.
So, how can i do this ?
will set_max_delay -from -to affect?
best ...
My requriement is that:
There are two input signal, In_a, In_b, these two signals will be connected to clock and data (llike I2C). two output signal, Out_clock, Out_data.
Because the In_a could connect to clock or data, so i need write a module to identify which one(clock or data) will connet to In_a, then re-arrange the order and output the correct signal , i.e. Out_clock or Out_data.
the code is like this:
module Switch(input wire In_a, input wire In_b, input wire S, output wire Out_clock, output wire Out_data)
begin
assign Out_clock = S ? In_a : In_b;
assign Out_data = S ? In_b : In_a;
end
if S is connected to external pin, the maxmum frequency is 200Mhz.
if i write a module to generate control signal S by In_a and In_b, for example like this
module Identify( input wire In_a, input wire In_b, out reg S)
begin
//some statistic code to indetinfy .......
end
the maximu frequency is 30Mhz.
The problem is:
I want the signals from In_a and In_b to Out_clock and Out_data can run at 100Mhz. the module Identify will influence the frequency(tsu). I want to write a SDC file to optimize the maximu speed.
the Identify moule just generate signal S to pick up which one is clock. if the S is ready, it is latched and needn't changed again . the data can be discarded before the S is generated.
So, how can i do this ?
will set_max_delay -from -to affect?
best ...
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Question on input delay
Hello;
Why should I insert the input_delay constrains in my design?
Thanks.
Why should I insert the input_delay constrains in my design?
Thanks.
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Read/Write image file in Nios II
Hi Everyone,
I want to load an image file (.bmp) using the Nios II but I can not! I used the fopen command and managed to load the image, but when I try to write in another file something happens that the image comes out deformed.
Does anyone know how I can load images in the Nios II?
Thank you!
I want to load an image file (.bmp) using the Nios II but I can not! I used the fopen command and managed to load the image, but when I try to write in another file something happens that the image comes out deformed.
Does anyone know how I can load images in the Nios II?
Thank you!
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