run synthesis/routing on a cloud server?

May 3, 2016, 1:34 pm

≪ Previous: Read/Write image file in Nios II

I am developing an educational FPGA board that runs on arduino. It is for classroom and hobbyist use. It would not be practical for each student to download and run the dev tools on their laptops. We have our own tool to output VHDL from simple schematics the student will input.

We would like to develop a cloud solution that takes this VHDL as input and returns binary programming files for their FPGA. There would be no human interaction. They will not necessarily know the design tool exists. It would just return the binary file and/or error messages. There can't be any syntax errors since the VHDL is machine generated.

This would in no way replace the normal design tool setup. No design interaction. Just VHDL in and binary out. I see from the license agreement states that each license is for only one seat. But this would be using the free version with no license.

Am I allowed to do this? If not who may I talk to about allowing this on a special education basis? Surely it would be good for altera to have students exposed to altera first.

Edit: This is cross-posted on Xilinx forum

↧

emulator for Windows

May 3, 2016, 2:09 pm

≫ Next: QSYS 1st timer -- JTAG to Avalon Master Bridge fails in System Console

≪ Previous: run synthesis/routing on a cloud server?

I have installed "Altera pro Quartus" and visual Studio. How do I install Emulator?

I am looking at the setclenv.bat from Training material and it is setting to a board at \hd\board\c5soc and I don't have the board folder on my system.

Thanks

↧

QSYS 1st timer -- JTAG to Avalon Master Bridge fails in System Console

May 3, 2016, 4:21 pm

≫ Next: Remote Configuration of FPGA Flash via FPGA

≪ Previous: emulator for Windows

Newer user of QSYS and System console here.

I have a JTAG-Avalon master connected as in qsys interconnect picture below. When I try to open service to the only master that is recognized (named phy_0) it fails.

1. Why is the master called phy_0? (I thought it should be master_0 - is this another IP block?
2. Why does to open service fail?

(See second picture of the system-console for commands and hierarchy of what system console is able to "register")

IDEAS? THanks!
Forest

Attached Images

clip1.jpg (19.2 KB)
clip2.jpg (19.5 KB)

↧

Remote Configuration of FPGA Flash via FPGA

May 3, 2016, 4:46 pm

≫ Next: resizing sfixed number

≪ Previous: QSYS 1st timer -- JTAG to Avalon Master Bridge fails in System Console

Is it acceptable to use a cyclone v user I/O pins to program the flash memory containing configuration for the cyclone v. This would be muxed in after power-up/configuration with the DCLK and other reserved I/Os and provide for a way to program through the flash (EPCS device) through the FPGA. Are there downsides to doing it this way, such as power-up problems? I was going to put a heavy pulldown/pullup on the mux select line so that this could only occur in user mode. Alternatively, has anyone used the altera remote update ip core w/o a NIOS? Could I just design my own state machine/processor to communicate with the remote update ip?

↧

resizing sfixed number

May 4, 2016, 12:00 am

≫ Next: Using DE2-115 for Labs designed for DE2

≪ Previous: Remote Configuration of FPGA Flash via FPGA

i want to resize a sfixed number of size(9 downto -6) to sfixed/signed of size (9 downto 0):
here's the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
USE ieee.numeric_std.all;

ENTITY dwt IS

END dwt;

ARCHITECTURE dwt_behaviour OF dwt IS

signal k : sfixed(9 downto -6) ;

signal kk : signed(9 downto 0);

BEGIN
k <= "1100110011000010";
kk <= signed(resize(signed(k), kk'length)); -- error line

END dwt_behaviour;

error is:
Index value -6 (of type std.STANDARD.NATURAL) is out of range 0 to 2147483647.

↧

Using DE2-115 for Labs designed for DE2

May 4, 2016, 9:30 am

≫ Next: Cyclone V PCIe hard IP? Megafunction required??

≪ Previous: resizing sfixed number

Hi,
We have some DE2 boards that will be replaced with DE2-115 boards. We have labs that were designed for the DE2 board and i am wondering how difficult it will be to convert those labs from DC2 to DC2-115.
Any ideas?
thanks

↧

Cyclone V PCIe hard IP? Megafunction required??

May 4, 2016, 12:33 pm

≫ Next: How do I will solidify the nios ii program in fpga

≪ Previous: Using DE2-115 for Labs designed for DE2

Hello, quick question for everyone. I've been looking over the documentation on the Cyclone V PCIe hard IP and not sure if you need to buy a Megafunction to implement a PCIe link on the Cyclone V? The documentation states, "The PCIe hard IP consists of the MAC, data link, and transaction layers". What exactly is "hard IP"? I found the following in the documentation, "The Cyclone® V PCIe hard IP operates independently from the core logic" what is this and how is it different than lets say implement a PCIe link on a Stratix IV fpga?

↧

How do I will solidify the nios ii program in fpga

May 4, 2016, 9:24 pm

≫ Next: Simulation of IP core in quartus 2 version15

≪ Previous: Cyclone V PCIe hard IP? Megafunction required??

How do I will solidify the nios ii program in fpga. Can you give me a tutorial.

↧

Simulation of IP core in quartus 2 version15

May 4, 2016, 9:41 pm

≫ Next: ethernet ip

≪ Previous: How do I will solidify the nios ii program in fpga

I am not able to simulate the IPcores generated using the IP cores listed on the quartus2 version 15. only the .qip file is generated..sip is not found.
when i used qsys, .sip file is generated and i am able to simulate also. .sip is required for simulation of megacore ip?????? please help me
resmi

↧

ethernet ip

May 4, 2016, 9:46 pm

≫ Next: Altera opencl, Diff usage of Processors when using parallel compilation of Quartus.

≪ Previous: Simulation of IP core in quartus 2 version15

can i implement Triple Speed ethernet TSE core in max10 (10 M 16) device????
Resmi

↧

Altera opencl, Diff usage of Processors when using parallel compilation of Quartus.

May 4, 2016, 11:31 pm

≫ Next: Use Avalon IP cores in Quartus II (not Qsys)

≪ Previous: ethernet ip

I am using "Hello world" of example designs offered by Altera Opencl. (https://www.altera.com/products/desi...esign-examples)

I use the "aoc" command and get the .aocx file.

but I have a confusion:

in the file "top.sta.rpt", it have something like this:

+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.08 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-3 ; 2.9% ;
; Processor 4 ; 2.2% ;
+----------------------------+-------------+

Problem:
1. Why Processor 1 is using 100%, and other Processor only use nearly 3% ?
2. How can I increase the usage of Processor 2-4 ?

Thank you, wait for your apply~

↧

Use Avalon IP cores in Quartus II (not Qsys)

May 5, 2016, 2:32 am

≫ Next: HPS Timing Warnings

≪ Previous: Altera opencl, Diff usage of Processors when using parallel compilation of Quartus.

Dear all,

I'd like to add an Avalon ST IP core to my Quartus II project but the IP core is not available in the IP catalog. It is available in the Qsys IP catalog, though.

Specifically, I'd like to create an Avalon ST single clock FIFO in Quartus II 15.0 for writing a simulation testbench. I don't want to create a system in Qsys as my testbench involves some complex register write operations which would be hard to implement in Qsys. Unfortunately, the Avalon IP cores are not available in the Quartus IP catalog. I tried to add the location of the IP core to both the global and local project IP search paths. I refreshed the IP catalog and restarted Quartus but the Avalon IP cores are still not available in the Quartus IP catalog.

Is it even possible to use the Avalon IP cores in Quartus II? If yes, how?

Thanks in advance for your advice,
David

↧

HPS Timing Warnings

May 5, 2016, 4:42 am

≫ Next: triple speed ethernet example for MAC10 with quartus 15.1

≪ Previous: Use Avalon IP cores in Quartus II (not Qsys)

Hello SOC Specialists,

currently I work on a Cyclone V with HPS. Qsys generates a few sdc-files.

My problem is, ... a lot of constraints are ignored. If I correct the signal names within hps_io_board_...sdc, those warnings disappear. But there are still more warnings.

I suppose the signal names in the wrapper file are incorrect. Maybe they should be the same as the signal names generated by QSYS. I will try it the next time I work in the office.

Does anybody know why I get the timing warnings? Is the mistake somewhere else?

With kind regards ...

↧

triple speed ethernet example for MAC10 with quartus 15.1

May 5, 2016, 5:31 am

≫ Next: How does the kernel determine the resource flags of a device node in a device tree?

≪ Previous: HPS Timing Warnings

I have downloaded and complied the TSE based solution on quartus ver 15.1.
I downloaded the solution from :
https://cloud.altera.com/devstore/pl...ethernet-uart/
The compilation is fine but I see warnings when launched IP upgrade in QSYS:

Warning: q_sys.mem_if_ddr3_emif_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
Warning: q_sys.mem_if_ddr3_emif_0.pll_bridge: pll_bridge.pll_sharing cannot be both connected and exported
Warning: q_sys.altpll_shift: altpll_shift.areset_conduit must be exported, or connected to a matching conduit.
Warning: q_sys.altpll_shift: altpll_shift.c2_conduit must be exported, or connected to a matching conduit.
Warning: q_sys.altpll_shift: altpll_shift.c1_conduit must be exported, or connected to a matching conduit.
Warning: q_sys.altpll_shift: altpll_shift.phasedone_conduit must be exported, or connected to a matching conduit.
Warning: q_sys.enet_pll: enet_pll.areset_conduit must be exported, or connected to a matching conduit.
Warning: q_sys.enet_pll: enet_pll.phasedone_conduit must be exported, or connected to a matching conduit.
Warning: q_sys.eth_tse: eth_tse.mac_misc_connection must be exported, or connected to a matching conduit.
Warning: q_sys.mem_if_ddr3_emif_0: mem_if_ddr3_emif_0.pll_sharing must be exported, or connected to a matching conduit.
Warning: q_sys.altpll_shift: altpll_shift.pll_slave must be connected to an Avalon-MM master
Warning: q_sys.enet_pll: enet_pll.pll_slave must be connected to an Avalon-MM master

Do we need to correct these warnings. I do not want to explicitly change anything unless required in the solution provided.

Thanks in Advance.

↧

How does the kernel determine the resource flags of a device node in a device tree?

May 5, 2016, 6:19 am

≫ Next: Stratix II GX PCI Express Development Kit License Issue

≪ Previous: triple speed ethernet example for MAC10 with quartus 15.1

I'm developing a devicedriver in a socfpga-linux provided by SoC EDS 15.1.1.60 for a customFPGA based PCIe Root Complex design on Altera Arria 10 board. I'mtaking pcie-altera.c for reference. When my driver parses the devicetree for the "ranges" property, it fails. Let me give outthe sequence:

drivers/pci/host/pcie-altera.c:

altera_pcie_probe() ->altera_pcie_parse_request_of_pci_ranges().

In altera_pcie_parse_request_of_pci_ranges(), the foll. piece of codedecides checks the device node flags, and decides whether the devicenode (in device tree) is prefetchable or not:

resource_list_for_each_entry(win, &pcie->resources) {
structresource *parent, *res = win->res;

switch(resource_type(res)) {
caseIORESOURCE_MEM:
parent = &iomem_resource;
res_valid |= !(res->flags & IORESOURCE_PREFETCH);
break;
default:
continue;
}

err =devm_request_resource(dev, parent, res);
if (err)
gotoout_release_res;
}

if (!res_valid) {
dev_err(dev,"non-prefetchable memory resource required\n");
err =-EINVAL;
gotoout_release_res;
}

In my case, the device nodeflag happens to be IORESOURCE_BUS, so it falls into the "default"case of switch. Since the res_valid variable is initialized to zeroin the beginning, my code falls into "if(!res-valid)"block and exits with error.

My DTS file is similar toaltera's/rocketboard's pcie DTS file. I've given below a part of myDTS file for reference:

sopc0: sopc@0 {
device_type= "soc";
ranges;
#address-cells = <1>;
#size-cells= <1>;
compatible ="ALTR,avalon", "simple-bus";
bus-frequency = <0>;

test_subsys_pcie: pcie@0x000000000 {
compatible = "altera, my-pcie";
reg= <0xc0000000 0x00001000>,
<0xc0001000 0x00010000>,
<0xff200000 0x00010000>;
reg-names = "axi_slave_1", "axi_slave_2","axi_slave_3";
interrupt-parent = <&HPS_arm_gic_0>;
interrupts = <0 19 4>;
clocks = <&test_subsys_clk_125M>;
device_type = "pci";
bus-range = <0x00000000 0x000000ff>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0xc0000000 0x00001000>;
}; //endunknown@0x000000000 (test_subsys_pcie)

Partof Rocketboard's DTS file is given below for reference:

sopc0:sopc@0 {
device_type= "soc";
ranges;
#address-cells= <1>;
#size-cells= <1>;
compatible= "ALTR,avalon", "simple-bus";
bus-frequency= <0>;

pcie_0_pcie_a10_hip_avmm:pcie@0x010000000 {
compatible= "altr,pcie-root-port-15.1", "altr,pcie-root-port-1.0";
reg= <0xd0000000 0x10000000>,
<0xff2100000x00004000>;
reg-names= "Txs", "Cra";
interrupt-parent= <&arria10_hps_0_arm_gic_0>;
interrupts= <0 24 4>;
interrupt-controller;
#interrupt-cells= <1>;
device_type= "pci"; /* embeddedsw.dts.params.device_type type STRING*/
msi-parent= <&pcie_0_msi_to_gic_gen_0>;
bus-range= <0x00000000 0x000000ff>;
#address-cells= <3>;
#size-cells= <2>;
ranges= <0x82000000 0x00000000 0x00000000 0xd0000000 0x000000000x10000000>;
interrupt-map-mask= <0 0 0 7>;
interrupt-map= <0 0 0 1 &pcie_0_pcie_a10_hip_avmm 1>,
<00 0 2 &pcie_0_pcie_a10_hip_avmm 2>,
<00 0 3 &pcie_0_pcie_a10_hip_avmm 3>,
<00 0 4 &pcie_0_pcie_a10_hip_avmm 4>;
};//end pcie@0x010000000 (pcie_0_pcie_a10_hip_avmm)

Both in my DTS file androcketboard's DTS file, the flags of the device node have NOT beenmentioned. Since the rocketboard's pcie-altera.c file has ONLY the"case IORESOURCE_MEM" in switch..., it is obvious thattheir device node seems to be of IORESOURCE_MEM.

I've 4 questions here.

1) How does therocketboard's device node is taken to be of IORESOURCE_MEM type inspite of their DTS file not mentioning the device node flag anywhere?

2) How does my device nodeis taken to be of IORESOURCE_BUS type, inspite of me following thesame format as rocketboard in DTS as well as code?

3) Is there actually any wayto specify the device node flags in DTS file?

4) When the kernel parsesthe DTS file, how does it determine the flags of a particular devicenode?

Please help me out.

↧

Stratix II GX PCI Express Development Kit License Issue

May 5, 2016, 6:24 am

≫ Next: Creating a terminal to control Nios-II to send commands to SPI slave

≪ Previous: How does the kernel determine the resource flags of a device node in a device tree?

Hi All,

I have recently inherited a "PCI Express Development Board, Stratix II GX Edition" which uses a "Stratix II GX EP2SGX90F1508C3" FPGA.
I looked up the Quartus II compatibility table and downloaded the v11.0sp1 Web Edition toolset which supports the Stratix II GX family.
My part shows up in the device list, so no problems there.

When I try to compile the design I get:
Error: Current license file does not support the EP2SGX90FF1508C3 device

I obviously wrongly assumed the free web edition would work with all devices in the families the website said it supported, please could someone clarify the situation and help me locate a list of devices that the web edition will support?

Thanks,
Andy

↧

Creating a terminal to control Nios-II to send commands to SPI slave

May 5, 2016, 6:51 am

≫ Next: transmit raw file to a flash device connected to altera device

≪ Previous: Stratix II GX PCI Express Development Kit License Issue

To ease testing of slave devices e.g memory devices, ADCs e.t.c is it possible to create an application where one has a terminal window open on PC from which one can write specific words to an SPI slave connected to the Nios processor and read back out to the screen whatever is read in by the Nios processor?

↧

transmit raw file to a flash device connected to altera device

May 5, 2016, 8:42 am

≫ Next: Using UART at arbitrary BAUD Rate

≪ Previous: Creating a terminal to control Nios-II to send commands to SPI slave

provided that I have a raw data file describing exactly how data must fit into a flash device connected to an altera device, is there an altera-approved method to transfer this file into flash device or do I have to develop a custom solution e.g using serial port? I am looking at no less than 1MB flash.

↧

Using UART at arbitrary BAUD Rate

May 5, 2016, 8:54 am

≫ Next: Black Box QSYS Components

≪ Previous: transmit raw file to a flash device connected to altera device

I am using QSYS on the MAX10. I am interfacing to another board over an LVDS Physical Layer using a UART. The data rate is 80 MHZ. I am planning on oversampling at a clock rate 4x the data rate ie 320 MHz.
How can I do this? Can I do this using the altera_up_avalon_rs232 or

altera_avalon_uart

↧

Black Box QSYS Components

May 5, 2016, 11:36 am

≫ Next: Communication between NIOSII core and HDL (Verilog) module- Cyclone IVGX

≪ Previous: Using UART at arbitrary BAUD Rate

I am starting my first QSYS design. I will have to create some of my own components. I would like to create them first as black boxes so that I can do a block diagram of the system, and then go back and put in the VHDL code to make them functional. How would I go about doing this?

↧