Communication between NIOSII core and HDL (Verilog) module- Cyclone IVGX

May 6, 2016, 12:44 am

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Though I have some background with programming, it is very less when it comes to understanding hardware specifications and resulting functionalities. Therefore even after going through NIOSII reference handbooks, I have to post this question.

Problem. I need to create a working model of a NIOSII core communicating (exchanging data bits) with another sequential HDL module in the FPGA. So I create a NIOSII (block symbol file) with 8bit wide PIO(output) and another block symbol file of a Verilog module that accepts 8 bit wide input and stores it in a register.

I then create new project with a Block Diagram file as top level entity and have both the blocks (NIOSII and HDL) connected through a bus .

My question is, is this the desired way of exchanging data for my scenario, or are there any other clever and more efficient means to do so.


PS:Why I haven't tried it on the hardware and checked yet is because I am getting errors while implementing a simple NIOSII on the FPGA which I am dealing with separately. Just want to make sure that my though process for my problem is correct.

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Debugging multiple fpgas

May 6, 2016, 4:00 am

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Hello,

i want to debug my design which is fit into 4 altera fpgs(arria x) i.e., i have 4 different stp files.
Can any one help me in debugging my entire design using only one trigger condition.

In signal tap ii analyzer, I know that multiple instances of same fpga can be managed using trigger in and trigger out option.but how can i manage multiple fpga stp files (i want to debug entire design using only one trigger condition).
Can any one help me out here. Thanks in advance.

MJrao

External Memory without BGA?

May 6, 2016, 4:17 am

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Hi,

i need external memory for a MAX10 FPGA (10M50SCE144I7G).
I am not able to solder BGA packages.

Is it possible, to use a SDRAM with this device?
Only the BGA packages have a memory interface:
https://www.altera.com/content/dam/a...ug_m10_emi.pdf (page 7)

Can I do it without a dedicated memory interface?
It´s no problem if it is slow, I only need the memory for a NIOSII.
I don´t need high performance, but a huge memory.

I´d like to use this DDR SDRAM:
http://docs-europe.electrocomponents...6b813f3609.pdf

Which IP-core memory controller is suitable for this memory?
I can´t find something about DDR ram, the Altera Documents cover only DDR2 and DDR3.

Regards
Olaf

Simplest method to transmit a file to FPGA

May 6, 2016, 5:14 am

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Provided that one has a file that is to be transmitted down to the FPGA and it will store every byte into internal or external memory (maximum size is around 1MegaByte). What is the preferred way of doing this?


Should one create a custom solution in whic the user sends the file down serial port from PC, the FPGA recieves it into a FIFO and then it stores it in internal/external memory on a per-byte or per-byte-block basis.


Or is it possible to utilize the JTAG port for this purpose such that the file can be streamed down the JTAG port and the design inside the FPGA can process the bytes as stated above?


I expected this to be a simple problem since we already transmit configuration data to the FPGA and possibly a connected configuration memory device. However, it seems that it is not. :|

Qsys:Peripherals:Frequency_counter

May 6, 2016, 11:03 am

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There is a "Frequecy_Counter" IP in SOPC and Qsys, but there don't seem to be any instructions on how to use it. When I click on the "Datasheet" link for the IP, it brings me to the "ub_embedded_ip.pdf" which does not include any instructions for this device. System.h lists that it is there when I include it in my NIOS processor, but there are no support functions included in the BSP to give me a clue on how to use it. Altera and Off-site searches would lead me to believe that nobody on the planet has ever used this IP. Can that be true?

Does anybody know where there are instructions on this IP, or have any ideas about register descriptions and which of the 3 clocks are which?

USB Blaster cannot install (Code 37)

May 6, 2016, 8:48 pm

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Dear support
I have a error with USB Blaster: Windows cannot initialize the device driver for this hardware. (Code 37)
I try uninstall and reinstall but unsuccessfully.
Please help me!

Attached Images

• Capture.jpg (17.5 KB)

Quartus 15.1 issue for altsyncram

May 7, 2016, 3:54 am

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Hi,
I am using Quartus 15.1 prime , in that When I instantiate a altsyncram it errors out for Arria 10 Gx ,the error message is as follows:

Info (12128): Elaborating entity "rr4096x8_32r_2p" for hierarchy "sdh:Csdh|stm4in:Cstm4in|wrctrl:Cwrctrl|rr4096x8_3 2r_2p_shell:\g1:0:Crr4096x8_32r_2p|rr4096x8_32r_2p :Crr4096x8_32r_2p"
Info (12128): Elaborating entity "rr4096x8_32r_2p_altsyncram_5n21" for hierarchy "sdh:Csdh|stm4in:Cstm4in|wrctrl:Cwrctrl|rr4096x8_3 2r_2p_shell:\g1:0:Crr4096x8_32r_2p|rr4096x8_32r_2p :Crr4096x8_32r_2p|rr4096x8_32r_2p_altsyncram_5n21: rr4096x8_32r_2p_altsyncram_5n21_component"
Error (12024): WYSIWYG primitive "ram_block1a_0" is not compatible with the current device family
Error (12024): WYSIWYG primitive "ram_block1a_1" is not compatible with the current device family
Error (12024): WYSIWYG primitive "ram_block1a_2" is not compatible with the current device family
Error (12024): WYSIWYG primitive "ram_block1a_3" is not compatible with the current device family
Error (12024): WYSIWYG primitive "ram_block1a_4" is not compatible with the current device family
Error (12024): WYSIWYG primitive "ram_block1a_5" is not compatible with the current device family
Error (12024): WYSIWYG primitive "ram_block1a_6" is not compatible with the current device family
Error (12024): WYSIWYG primitive "ram_block1a_7" is not compatible with the current device family

the design was earlier compiled in cyclone v .

the intended file even won't open using megawizard function, although it is qsys in quartus 15.1 via ip catalogue.

waiting for quick reply.......

Modelsim error

May 7, 2016, 10:10 am

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Hii i am using Modelsim student edition for the simulation of my edge detection code.
I am getting the following error....

** Error: fixed_pkg Unbounded number passed, was a literal used?**

can any one please suggest what is the meaning of this error???
Thanx and regards!!

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Difference in floating point and fixed point arithmetic in vhdl.

May 7, 2016, 10:14 am

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Hiii...
I want to know the difference between floating point and fixed point arithmetic.I searched it on google but I didnt get a clear idea when to use which type of arithematic.
Can any one please help me to understand it in a simple language.
Thank you in advance.

My AXI4 Lite slave hangs CPU after read. Write transactions work correctly

May 7, 2016, 3:09 pm

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Hi,
I have ported my AXI4-Lite to IPbus bridge from Zynq to Altera Cyclone V.
Unfortunately, it behaves in a strange way in Cyclone V.
Tests have been done with "devmem" tool in Buildroot compiled Linux.

There is also Altera sys-id component connected to the same bridge using the same clock and reset signals, which works perfectly, so the clock and reset signals are correct and the lwhps2fpga bridge is enabled (at the U-Boot level).

Below are the Signal Tap recordings for write transactions (32-bit write, and 64-bit write).

devmem 0xff200124 32 0xdad98123

devmem 0xff200000 64 0x12345678fedcba98


Unfortunately, for read accesses the CPU hangs just after the first (in case of 64-bit read)
or the only (in case of 32-bit read) transaction is finished:

devmem 0xff200000 64

devmem 0xff20001c


The transaction is completed correctly at the slave level, however it looks like the information about completion doesn't reach the CPU.
I attach sources of the component. It contains a few IPbus slaves conencted to the bridge. One of registers drives 8 lines conncted to LEDs via "leds" conduit.

The verified Xilinx version is almost the same. It only does not use the WPROT and RPROT ports and uses narrower LEDS conduit (3 LEDS).

What can be the reason of such strange behaviour on the Cyclone V platform?

TIA & Regards,
Wojtek

Attached Images

• axi_write1.png (16.3 KB)
• axi_write3.png (16.0 KB)
• axi_write2.png (16.5 KB)
• axi_read1.png (16.3 KB)
• axi_read2.png (15.6 KB)

Divided integer number

May 7, 2016, 11:36 pm

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Can I divide the integer number (for example, 120) to each of the numbers 1 2 0 in different variables?

Altera MIF file format from MATLAB MIF format for cyclone M4K

May 8, 2016, 2:00 am

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Hi all.
I'm a beginner and i'm trying to save a picture on the M4K blocks (cyclone 2, on DE2) and read it out to the VGA DAC.

The vga part works, but i'm having problems with the MIF file for the M4K which i have generated with MATLAB. It won't display anything, it displays a black screen.

When i'm generating a MIF file with qurtus and randomly puts '1's in the array, it does displays on screen. but if i put the MIF file from matlab, again, just black screen.

if someone knows how to address this issue, i will by grateful.

THANK YOU!!

Seek programming assistance.

May 8, 2016, 2:15 am

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Hello Altera Forums,

I hope I post this in the right subforum - otherwise please feel welcome to move the thread to the right subforum.

As it is I seek programming assistance for what may likely be a simple programming task for the person who already knows about this. I hope one of you will be interested in working on this ... maybe also give me a hint if such a solution already exists.

What I need is to find a solution to two somewhat different tasks yet both are related to streaming data from a No. of ADCs into a PC at relatively high speeds - without any drop-outs in the data stream. The operating system preferably is Windows 7.

The first data stream comes from 2-5 SAR ADCs (20/24 bits) and is in the Two Complement format. This Two Complement data stream eitherneeds to be:

A.: Streamed directly into the PC and stored in a .wav format.
Data transfer rates are 384 kHz, 768 kHz or 1.536 MHz and the output from the SAR ADCs is either 20 or 24 bits, with 2-5 channels of similar data. The file format of the data stream should be a .wav file. The exact data read time from the SAR ADCs should be the same between data readings (and somewhat adjustable).

B.: Or "Translated" from the Two Complement data stream to a continuous I2S signal. Again sample rates are 384 kHz, 768 kHz or 1.536 MHz. The SAR ADC input data formats are 20/24 bits Two Complement, and the I2S output data format is an I2S format at 32 bits. Again, the exact data read time from the SAR ADCs should be the same between data readings (and somewhat adjustable), and it should be possible to transfer 2-5 channels of similar data.

I suppose the "B" solution may be the simplest but would be most interested in hearing from you if you can make a solution for the "A" version.

Since the precise timing of reading data from the SAR ADCs matters I imagine that a CPLD, FPGA or similar device may be a feasible hardware solution, however, am open to other solutions.

The second data stream comes from 2-5 1 bit ADCs all outputting data at 22.579 MHz, i.e. a 22.579 MHz 1 bit signal. I would like these data to be entered directly into the PC and stored in a .dsf format (DSD audio format).

I seek a programmer who already is experienced/proficient in this type of programming and is capable of completing this job within a not too-long period of time.

If you are interested then please contact me by PM, or post here, and we can talk about specifics and your payment for this.

And again, if someone here knows of a solution for this that already exists I would be most interested in hearing about it as I don't see any reason for "re-inventing the wheel".

I hope to hear from you.

Cheers,

Jesper Mønsted

NIOS UART and esp 8266

May 8, 2016, 6:38 am

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Hi all,
I'm trying to make an interface between an FPGA and an esp8266 with the NIOS II UART Core, here you found my transmit and receive functions

Code:

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void uart_send_data(unsigned char char1[])
{
        alt_u32 j,len;
        j=strlen(char1);
        alt_printf("Beginning transfer \n ");
        for (len =0 ; len <j; len++){
            IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE,char1[len]);
            alt_printf("Sending : %c ",IORD_ALTERA_AVALON_UART_TXDATA(UART_BASE));//Character sent
        }
}

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Code:

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void uart_receive_data(void){alt_u16 j=0,len=0,i=0 ;
volatile alt_8 temp;


status = IORD_ALTERA_AVALON_UART_STATUS(UART_BASE);
while ( ( status & 0x0080)){
        temp= IORD_ALTERA_AVALON_UART_RXDATA(UART_BASE);
        Mem[j]=temp;
        j++;
} // waiting for data
len=strlen(Mem);
for (i=0;i<len;len++){


alt_printf("REP%c",Mem[len]);
}
}

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this functions aren't working well I don't know if it is because the ESP8266 or I made smth wrong.
Please guys can you tell me if my program is okay.
TKHS

Tips for solving routing congestion? How to debug?

May 8, 2016, 6:50 am

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How can I debug the source of my routing congestion? Quartus says that routing details can be found in the Chip Planner, but I to looked there and I couldn't understand how to use the information to find the routing issue. For example, the source of my routing congestion could be a reset signal, but how can I can be more confident in that idea before I start another compilation (it takes over 6 hours to compile my design before it gives the error message for routing congestion).

Also are there compilation settings I can adjust to help with routing? I turned on Aggressive Routing Optimization, but is there something else I should try?

Finally, will adding more registers at the I/O pins and spreading the I/O pins out across the device help with routing?

Btw, I am targeting an Arria 10 device and my design takes up approximately 80% of the logic resources.

Thanks in advance!

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Where is PCIeRootPortWithMSI DMA transfer test source code (dmaxfer.c) located?

May 8, 2016, 7:24 am

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Hi,

I would be appreciated, if someone could help me with about the following issue:
I would like to test our FPGA development board as a PCIe endpoint.

I used the https://rocketboards.org/foswiki/vie...ootPortWithMSI description, we have a Cyclone V SoC DB on stock as a rootport, same as the reference design, I have also used the original SD card image.
I have ported the Cyclone V GT design to our devboard, so I would like to test the communication between the two boards the same way as the wiki page describes it.

I have successfully loaded the kernel modules (altera_epde.ko, altera_rpde.ko) but the test (dmaxfer) freezes after the first test item:

root at cyclone5:/mnt# insmod altera_epde.ko
PCI: enabling device 0000:01:00.0 (0140 -> 0142)
altera-epde 0000:01:00.0: using MSI irq #341
root at cyclone5:/mnt# insmod altera_rpde.ko
root at cyclone5:/mnt# lspci
00:00.0 Class 0604: 1172:e000
01:00.0 Class ff00: 1172:e001
root at cyclone5:/mnt# ./dmaxfer

==================================================
PCIe throughput test between RP(OCM) <-> EP(OCM)
RP(OCM) = Root Port On-Chip RAM
EP(OCM) = End Point On-Chip RAM
==================================================

Loop #01: RP-DMA write to EP 262144 Byte 697 MB/s

So, I would like to modify the test code to do some debugging on the system, but I could not find the source file *(dmaxfer.c)* to modify and re-compile it.
I will be very grateful, if anybody help me, where can I find this DMA transfer test source code.
I'm looking forward to hearing from you.

With kind regards,

Zsolt, Voroshazi
Eutecus HU Ltd.

timer in nios ii

May 8, 2016, 7:47 am

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hello everyone, i want to ask how much period cycle do the nios ii timer take???? please help mee :cry:

Use SDRAM from SoC and VHDL component

May 8, 2016, 11:27 am

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Hi
I have SDRAM Controller connected to HPS and i want to use SDRAM (to read/wite) also from my VHDL component. Unfortunately during compilation I get error that says there can by only one signal connected to SDRAM. How to resolve that?

DMA vs MSGDMA

May 8, 2016, 1:21 pm

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What is the difference betwen DMA and MSGDMA? Which is better to use?

Signed addition in Nios II

May 9, 2016, 12:15 am

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Hi all,
I need to add two numbers in Nios II.
For that i simply add two numbers in Nios II C program.
I have assigned the maximum possible 32 bit positive value .i.e. 0x7FFFFFFF in both.
What i expect is the result should saturate to 0x7FFFFFFF as in the case of micro controllers.
But the Nios II does not do like that.What can be the reason for that?