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Unable to target transceiver toolkit to HIP PCIe x2/4/8 instances

May 10, 2016, 4:22 pm
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This is really confounding me. I have retargetted an Altera example design to my own board and am trying to use Transceiver toolkit. The device is Stratix V GX. When I set PCIe core's number of lanes to more 1, I get following warning during assembler stage. After which the TTK is not able to recognize any channels.
Code:
Warning (15104): Quartus Prime software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design.
I saw another post about this error in this forum. That post indicates that paths may be missing or incorrect. But in my case, the funny things is that TTK is I do not get this warning and TTK console recognizes the channels if I only have one lane PCIe core.

BTW, I tried both Quartus Prime 15.1 and 16.0. Same problem.

What may be going on?

Thank you for the help.
Best regards,
Sanjay
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DE0 NANO running LED schematic design not running as expected

May 10, 2016, 6:08 am
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I just bought a DE0-Nano Development and Education Board from:
http://www.terasic.com.tw/cgi-bin/pa...English&No=593

This is my first FPGA.
I use Quartus II 32-bit Version 13.0.1 Web Edition
Start with a simple design I made a running LED
- Use the on-board oscillator. PLL and lpm counter to make the frequency lower
- another lpm counter to feed the lpm decode.
- lpm decode to output the running LED
running OK

Then I tried add a DFF to make the running LED bidirectional (see my pic).
- The DFF is controlled by the lpm decode edge output. The DFF output is controlling the lpm counter.

The running LED is not running as I expected. The led7 only ON at startup and never reach back.
So it run with sequence like this from startup:
led7 - led6 - led5 - led4 - led3 - led2 - led1 - led0 - led1 - led2 - led3 - led4 - led5 - led6 - led5 - led4 - ... (not reaching led7)

Something wrong in my design?
Attached Images
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DE2-115 Linux

May 10, 2016, 6:29 pm
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First, thank you to whomever posted the wonderful DE2-115 Linux demo to the ALTERA WIKI. Very neat. I am getting ready to start some development with the DE2 board and I am looking for head start data. I see the quartus project posted and I've DL'd it. It looks like a ver 9.1 SOPC builder based project. If the person who created this frequents this site, I have 2 questions:

1. Do you have the same design in a Qsys flow?

2. Have you upgraded your Linux kernel into the 3.10 area?

Thanks,
-Stan
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Help with DE1 D5M camera and VGA

May 10, 2016, 10:18 pm
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I wanted to know where is the data being stored after we capture the image using the DE1_D5M camera module in Altera DE1 board? I wanted to make the image be shown in grayscale if I turn on let's say switch SW[9]. I have the code for the conversion of the image to grayscale but I am not sure if I am getting the right image data to be converted to grayscale and I'm not sure where to output the data in VGA. Please help.
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DE0 nano Cycl.V: SDRAM parameters for Qsys

May 11, 2016, 1:59 am
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Hi everyone!
At first: I am new to FPGA/VHDL, but I am in a project at the University, where we are trying to learn the basics of FPGA-programming "by doing".
For our Project we now want to use the SDRAM as a fifo-memory for the VGA-data. I therefore watched a video on youtube (https://www.youtube.com/watch?v=euw0ILLTEhM), which is really really good! The only problem is, that it is for the DE1 nano - not the DE0 nano.

So my problem is now: where can I find the coorect settings for the Qsys-SDRAM-Controller? Like Rows, Columns, Chip Select, Banks, Timings etc? I know that it should be somewhere in the Datasheet but i realy cannot imagine which value is which (especially rows and columns).

Cheers and thank you very much in advance!!!
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powerplay dynamic power consumtion

May 11, 2016, 2:37 am
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hi all
I'm using QuartusII 15.1.0 lite Adition.
I have a small design of 1.5K LE at 50Mhz frequency.
when I ran PowerPlay the Core Dynamic power Dissipation always comes out 0mW.
is there any definitions I'm missing?
Thanks
Zahik
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signed integer to std_logic_vector and vise versa

May 11, 2016, 3:25 am
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Hello Altera people !
I have two questions :

1 // I need to read a signed integer and compare it in vhdl !
Knowing that the output is std_logic (either vector or simple). how to do it ? what are the instructions !?

2// The component will be used as user peripheral in Qsys so I guess the input isn't considered as integer no ? the input is 32 bits how I can do my comparison as if it is signed integer ?!


thnx
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DSP blocks

May 11, 2016, 3:28 am
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Hello
I am synthetizing a FFT on Arria 10. The compiler report gives 136 DSP blocks are used including:
32 floating point multipliers
32 floating point addition of products
72 floating point adders
(32+32+72=136)
For me it does not add up because the same DSP blocks that do the multiplication, do as well the accumulation. So at maximum we should have 104 DSP blocks (32+72).
how can we explain this result ?!
Thanks in advance
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DE1-SoC LXDE Audio

May 11, 2016, 5:35 am
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I have been going through the Getting Started Guides and am currently trying to get Linux running on the DE1-SOC board. After having followed the procedures in the Getting Started Guide I don't get any audio output.

There is somenthing wrong in the procedure done?
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logging error in vhdl

May 11, 2016, 10:56 am
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I got this error several times:

my code gets successfully compiled but the error is

"Logging is not supported for this item"

why this error is displayed, can anyone tell !!!!!!
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using 7 segment display in DE1 soc

May 11, 2016, 9:11 pm
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I am trying to use the 7 segment display of board de1 soc.
I am using linux image in an SD memory card. I could compile successful the hello.c, that has this code:


int main(int argc, char** argv) {
printf("Hello SoC FPGA!\n");
return 0;
}


Running it I could verify that my installation, I am using cross compiling on Windows, is working fine.


After I tried an example to write in 7 segment display.


I tried this code:


#define ADDR_7SEG1 ((volatile long *) 0xFF200020)


int main()
{
*ADDR_7SEG1 = 0x00000006;
}


But when I run it on the board I receive a segmentation fault .... But I don't understand why this is happening.


Somebody has some tips in what is wrong? Is there something that needs to be configured before in Hardware or Software?
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gmon.out not compiling correctly

May 11, 2016, 11:32 pm
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Hi,

I am trying to run the checksum example code from altera for profiling. however after the code is run I am not able top open my gmon.out file. It gives me the error :nios2-elf-gprof: command not found EXIT CODE-127. I followed all the steps the nios profiling pdf. I have a system timer on my hardware and grop-enable ticket on the BSP.

What can be wrong.

Thanks fro the help.

Saru
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CAM(Content Addressable Memory) into QDRII+ / DDR3

May 12, 2016, 1:08 am
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Hi,


We need to implement a CAM using the QDRII+ / DDR3 memory. Basically a typical hash table implementation in FPGA.


Altera provides example design for binary CAM. The implementation is based on M9K embedded memory.


Is it possible to port the same CAM implementation into QDRII+/ DDR3 memory?


Are there any latency statistics available?


Thanks in Advance!
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Count.binary template does not display on the 7 segmant

May 12, 2016, 2:02 am
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Hi, I am using quartus v13.1 and a DE2-115 board. I have a qsys niosII system compiled and programmed onto the board with no warnings or errors and a PIOs for the switches and all the seven segments which appears to have the correct pins assigned. When I try to run the count.binary template on eclipse, the system only displays the output on the nios console on screen. When I look at the c file the sections of the code related to the 7 segment and such are highlighted in grey and after using the debug tool I can confirm that these sections of code are not being executed. Also I have used copies of file examples and systems from tutorials of people who have uploaded their files. When I use their SOPCinfo file and select the count.binary template, the same issue occurs and the C code sections are still highlighted in grey. Also I am confused with the actual 0-ff counter. I would like it to modify it so instead of 0-ff it would simply be a 0-99 decimal counter but I cannot locate where this counting loop takes place. Any help would be greatly appreciated!
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ultrasonic sensor in VHDL

May 12, 2016, 3:53 am
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Corresponding begin/end statements

May 12, 2016, 7:39 am
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I've got a verilog code, and I'm just wondering if there was a tool which quickly found the begin and end statements corresponding with each other. Once the code starts getting big, it's pretty hairy tracking it manually. Thanks.
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DMA read timeout while using PL330?

May 12, 2016, 7:44 am
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Hi

we are using the HPS-DMAC (PL330) on a De0-Nano-SoC board to write and read data from the FPGA through a kernel module using the dmaengine API. Writing works fine (albeit pretty slow), but everytime we try to read data from the FPGA, a timeout occurs. The kernel module ist largely based on the fpga-dma driver provided by altera. I can see that the read transfer is arriving at my module in the FPGA (which is just a loopback FIFO), but for some reason the DMA callback function is never called and so a timeout occurs.

When I remove the timeout from the kernel module, the first transfer still arrives in the FPGA and reads some data. All following read-request dont reach the FPGA until I call a write to the FPGA. When executing the write, the read callback is called and the next read begins. This is very weird to me, I don't understand how the write call can call both the read and write callbacks.

My question is: what determines the end of a read access for the DMAC? Do I have to implement some additional signal in the avalon bus?

I hope someone can give us a hint! If you need any more information or code samples, please let me know!

Thanks in advance!
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Byte Blaster II : Flash Loader IP Not Loaded

May 12, 2016, 7:55 am
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I recently got a new USB-Blaster II. I've been using it for .sof's with no problem.
Today, I try to load a .jic, and get the error:

Info (209060): Started Programmer operation at Thu May 12 10:49:42 2016
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x028030DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Error (209062): Flash Loader IP not loaded on device 1
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Thu May 12 10:49:47 2016

I found my older grey USB-Blaster, and it programmed the .jic with no issues.

Has anyone seen this before? Is my USB-Blaster II broken? Or do I have to do something differently?

Thanks!
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Is there any way to initialize onchip-ram with auto-generated data instead of an .mif

May 12, 2016, 9:55 am
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Hello every one
I have some puzzle in using altsyncram module, and I need your help!
In my design, I want to initialize a altsyncram in a parameterized module. The data filling to ram should be generated with the parameter passed to this parameterized module. But it seems that altsyncram can only be initialized by a .mif file. How can I reach my purpose?

The another way to workaround it is to use verilog to declare a ram register array by specifying 'ramstyle' property with "M-RAM", just like the following code:

Code:
(* ramstyle = "M-RAM" *) reg[7:0] ram[31:0];
But the ram constructed by this way can only be accessed by one port. Dual port accessing code will cause synopsys to allocate double onchip ram blocks, and that should be avoid in my design.

I had tried to generate .mif file in the intial block of module, and it didn't work because quartus II didn't support the system function such as $fopen, $fprintf, etc...

So, could anyone tell me how to initialize altsyncram programmatically in verilog? Or anyway to generate .mif file programmatically through verilog by calling a script? Or How to generate a TRUE Dual-port ram without using IP core such as altsyncram etc?

Thanks very much!
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Powering FPGA During Programming

May 12, 2016, 11:29 am
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Hi everyone-

I am finalizing a PCB layout using a Max10 FPGA. This PCB will (hopefully) go into production in our small electronics business, and it will usually be programmed by technicians on the manufacturing floor. It is essentially a daughter board for a larger circuit board, and as such, it has no "easy" way to attach power during JTAG programming (before it is fully assembled).

So my question (which may be quite common: sorry if it is a repeat)... Is there an easy way to apply power to the FPGA via the JTAG header? We *could* set up some convoluted system with alligator clips and everything to apply power to the correct solder pad, but since this will be programmed by technicians, I would like to keep it as simple as possible.

Has anyone come up with some clever way to accomplish this?

Could I, for example, somehow intercept the Vcc wire on the USB Blaster cable and apply 3.3V (my system voltage) that way?

Thanks!
Robert
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