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i wanna to convert this code in vhdl

May 12, 2016, 12:52 pm
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void main() { SerialPortInit(); /* Serial Communication – 9600-N-8-1 */
Send2Gsm("AT\r\n"); /* Transmit AT to the module – GSM Modem sends OK */ DelayS(2); /* 2 sec delay */
Send2Gsm("ATE0\r\n"); /* Echo Off */ DelayS(2); /* 2 sec delay */
Send2Gsm("AT+CMGF=1\r\n"); /* Switch to text mode */ DelayS(2); /* 2 sec delay */
Send2Gsm("AT+CMGS=\"+919447367176\"\r\n"); /* Send SMS to a cell number */ DelayS(2); /* 2 sec delay */
Send2Gsm("TEST DATA FROM RhydoLABZ-COCHIN"); /* Input SMS Data */ SerialTx(0x1a); /* Ctrl-Z indicates end of SMS */ DelayS(2); /* 2 sec delay */
while(1);
}
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Vulnerability VU#485744 FlexNet lmgrd contains a buffer overflow vulnerability

May 12, 2016, 1:30 pm
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Hello

A buffer overflow vulnerability has been discovered in FlexNet Publisher license servers prior to version 11.13.1.1. This vulnerability affects both the license manager "lmgrd" and the vendor daemons
and may enable a remote attacker to execute arbitrary code in affected server hosts. For more information about this vulnerability see <https://www.kb.cert.org/vuls/id/485744>.

I don't see any update to lmgrd/alterad on Altera's website (the latest edition is 11.11). Are they going to address this issue, and release a patched alterad (11.13.1.2 or later)?

thanks,
roozbeh
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8E1111 PHY tx_clk and rx_clk

May 12, 2016, 4:25 pm
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Hi,

I have a custom board with altera Stratix 4 and 8E1111 PHY. i am trying to initiate the triple speed ethernet IP. a 25MHz crystal is connected with the PHY.
i have used the Simple Socket Server Software Example to initiate the IP.

i have tried to probe the tx_clk and rx_clk, clock signals from PHY. there is no clock coming from PHY.
is there any initiation needs to be performed to start the clock from PHY?

Thanks
Vinay
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Quartus Prime 16.0 stops compiling before fitter runs

May 12, 2016, 5:20 pm
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So, I made the choice (mistake?) of upgrading my Quartus Prime Pro version 15.1 to Quartus Prime Pro version 16.0.
I ran the IP updater on my project that I am upgrading from 15.1 to 16.0 and everything seemed to update ok.
The problem is that now, whenever I run the compilation, the compiler completes the first two steps in the flow (IP Generation and Analysis & Synthesis) but then stops. It never runs the Fitter. When I specifically tell it to run the fitter, it sits at 0% for a few minutes then stops without generating any messages.
Has anyone else made the leap to 16.0 yet?
Why won't it finish compiling?

g
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MAX 10M02 in quad flat pack

May 12, 2016, 9:03 pm
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Altera is catering to their large customers, with the MAX10 in the chip scale BGA packages. However, as a hobbyist it would be really nice if they would release the 10M02 in a small count 44 pin quad flat pack. Something that the hobbyist can solder and design on a 2 layer board.

Any thoughts?
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DE2 demonstration problems

May 12, 2016, 11:20 pm
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I just purchased a DE2-50 board.
I'm trying to make the DE2_NIOS_HOST_MOUSE_VGA demonstration to work on this board. I achieved to program the board with the right sof file but when i try to open and build the software with Nios II 13.0sp1 Software Build Tools for Eclipse nothing is possible.
I follow
7) Switch the workspace to the <install path>\DE2_NIOS_HOST_MOUSE_VGA folder.
8) Build the project. (Project menu -> Build All)
as said in the readme file but when i try to build the fucntion is greyed.
Any idea ?
Thanks
Eric
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How to close timing with Negative Setup Slack

May 13, 2016, 1:07 am
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Hi,

I am working on a hardware design working at a clock frequency of 200MHz(5 nsec). Setup violation of -0.265 ns is reported by quartus tool. The source clock and the destination clock are same, and all the inputs and outputs to and from the block are registered. The critical path delay looks to be from a ripple carry adder, and this is crucial for my design. How can I go about using this hardware reliably? How bad is a slack of -0.265 ns with a clock frequency of 5 nsec?.If I change the clock uncertainty, what are the implications?

Reference: FPGA - Stratix V 5SGXMA7K2F40C2

Regards
Jeebu
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Cyclone4 JTAG issues

May 13, 2016, 2:14 am
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1.) We are using cyclone4 EP4CE55F23I7N on our custom board.(three FPGA’s per board as shown in schematic attached).It may be mentioned here that all the boards were working previously, but during development the JTAG interface on some boards is not working, but the FPGA seems to be working fine via passive serial mode.(Also the same FPGA U2’s JTAG is going faulty in boards after some time. In one of the PCB the VCCIO and GND of FPGA U2 was showing shorted, on removing the BGA and checking it was found that the device itself got faulty, which was earlier working fine).
It is showing no device found when we try to connect JTAG via USB blaster.

On monitoring the difference between working and faulty board, it was found out that TMS or TCK pin on the FPGA side is remaining at logic LOW even when we try to connect JTAG via USB BLASTER.(even though it is pulled high as shown in schematic above.)
Also TMS or TCK pin of these faulty boards have very low resistance to ground as compared to working boards.
The working board’s JTAG interface goes faulty after some time during development.
Our question is-what is the maximum current requirement of the VCCA (JTAG and analog section supply of FPGA).And whether the USB blaster also draws power from our board regulator??
Also it was observed in one of the boards that the 2V5 regulator for JTAG supply has gone faulty.

Since we are using a single 2.5V regulator with 0.8A to 0.9A current supplying capacity for our all three FPGA’s JTAG portion(as shown in schematic attached)on board, kindly suggest that will this be sufficient if we use JTAG interface for full development and debugging functions like signal tap etc.??




Also we read one blog on altera forum wherein similar problems were faced in JTAG interface of the people using their custom development boards after working on the board for some time.(same is attached). Kindly suggest what can be the issue??
Attached Files
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Error reported by S-function 'mip_control' in Control Block

May 13, 2016, 3:28 am
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Hi,
on the road to learn dsp builder advance, I find an error in run simulation of demo_firi.
demo_firi is example of subchapter of manual "DSP builder advance blockset" : creating a new model from an existing dsp builder design example and changing the namespace.
After solved problems on signals block, i find error:

Error reported by S-function 'mip_control' in 'my_tutorial/Control':
Found bad parameter value for parameter busClockFreq. Expecting type Double but found value dspb_firi.ClockRate / 4.

View attachments.

I beg you to help me.
Attached Images
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Error 209015 programming in Quartus 15-1-2 (but not in 15-0-0)

May 13, 2016, 3:29 am
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Hi,
I am getting an error when programming my Arria10 (Reflex Alaric board):
Error (209015): Can't configure device. Expected JTAG ID code 0x02E050DD for device 1, but found JTAG ID code 0x00000000. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).

I have a simple work-around: if I use Quartus 15-0-0 programmer, it works fine, and I don't get the error. (I'm using Quartus 15-1-2 to generate the .sof file)

Has anyone else seen this problem ?

Regards,
Chris
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MAX10M08 Flash Accelerator

May 13, 2016, 3:57 am
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Hi,

I am working on a project using the MAX10M08 with Nios ii /f and Quartus Prime Lite 15.1.2.

Up to now i used the onchipmemory as instruction memory. But the goal is run from the onchipflash.
The Guide “Nios II Flash Accelerator Using Max 10” describes the configuration of the Nios Flash Accelerator and the matching settings for the onchipflash IP.
The cachelinesize is set to 64bit according to the guide, because the Flash Wrapped Read Burstsize of the M08 is 2 (cachelinesize => 2*32bit). “Read burst mode“ oft the onchipflash IP is set to Wrapping.

But there is a problem. With the settings mentioned above i can start a debuggingsession within eclipse, “nios2-download” verify of flash content is successful, but the debugger won’t jump to main() (harwarebreakpoints and databreakpoints are set to 4). If I click on “pause / halt processer” and again “run” the debuggingsession terminates.

Error: Processor failed to go into debug mode when requested.

So I used gdb with console, set a hardwarebreakpoint at the reset address. The processor jumps to the reset vector pointing to flash and stops. After a single step gdb hangs / the processor hangs.

I also tried setting the cachelinesize to 128bit and it works, but I don’t think that’s the correct setting for the flash accelerator with MAX10M08 and will cause problems / no increase in performance.

Is anyone successfully using the flash accelerator? I have attached my configurations and qsys design.


Thanks in advance!
Attached Images
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Cannot start Qsys from Quartus

May 13, 2016, 7:25 am
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I have installed Quartus 12.0 sp1 because I got a DE2i-150 board, which instructed me to do so. I also have 15.1 installed on the same machine. From 15.1 I can normally start Qsys, it just comes up. From 12.0, I cannot - when I click the Qsys icon or I want to create a new Qsys file (from the File menu) nothing happens, there are no errors and no messages. I have restarted the machine after installation and made sure that all of the environment variables (Windows 8.1) point to the 12.0 version of Quartus. Does anyone have an idea how to resolve this? Thanks!
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Nios 2 custom instruction.

May 13, 2016, 7:45 am
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Hello everyone, I am implementing edge detection on fpga using nios2 processor. I want to do custom instruction for sobel algorithm. Idea is that I will take pixel values (3*3 matrix at a time) as a input for custom instruction and it will give me final pixel value . But Question is that custom instruction provide only 2 inputs and i want to generate custom instruction which has 9 inputs. So can anyone guide me how to generate custom instruction in nios which has more than 2 inputs?
Thank you.
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USB Drvers not working with Quartus 16.0 in Windows 7

May 13, 2016, 8:19 am
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I recently installed Quartus 16.0 on my Windows 7 Computer and unistalled Quartus 15.1. When I went to run SignalTAP, I get:
No device selected
and
Invalid JTAG configuration
even after I have selected USB-Blaster


I have tried two different US- Blaster cables.
When I check the device driver status, I get:
This device is working properly.
When I check the Driver File Details I get:
C:\Windows\system32\drivers\usbblstr.sys
C:\Windows\system32\usbblstr32.dll
C:\Windows\system32\usbblstrlang.dll
C:\Windows\ststem32\usbblstrui.dll
C:\Windows\syswow64\usbblstr2.dll

I uninstalled the river and re-installed it by plugging in the USB Blaster and go the same result

Any suggestions?
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I Need Help With the DE2 RS232

May 13, 2016, 8:46 am
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Hello everyone , i need help :confused:!!
i'm using the rs232 of my DE2 board with an SOPC system.... I'm using assembly with my softcore processor , but i can't seem to read my data (i need to send and recieve one byte at a time), so i would appreciate if one of you guys can help, maybe by proposing the right instructions to use

thank you in advance :)
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dll dependent library not found while using the Mentor AXI bfm in modelsim later

May 13, 2016, 9:31 am
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Hi,
I use the quartus II example for mentor taxi bfm to study how to use it.(C:\altera\15.0\ip\altera\mentor_vip_ae\axi4\ex amples\ex1_back_to_back_sv)
And follow the guide of mentor_vip_axi34_ae_user.pdf. It is ok to map lib and vlog files. But while doing the vsim in final step:

vsim -t ps -L work -L work_lib -mvchome $env(QUARTUS_ROOTDIR)/../ip/altera/mentor_vip_ae/common -c top

We met the errors bellow: (modelsim is modelsim altera 10.3d. Quartus is 15.0) . I searched the forum and did not find the exact answer for this. Anyone used to meet and solve this? Thanks.

--------------------------------------------------------------------------------------------


# vsim
# Start time: 00:49:53 on May 13,2016
# Loading C:\Users\mou\AppData\Local\Temp\mou@WIN-728EN2N2I93_dpi_5696\win32pe_gcc-4.2.1\export_tramp.dll
# Loading sv_std.std
# Loading work.top
# Loading work.QUESTA_MVC
# Loading work.mgc_axi4_pkg
# Loading work.mgc_axi4_master_sv_unit
# Loading work.mgc_axi4_master
# Loading work.mgc_common_axi4_sv_unit
# Loading work.mgc_common_axi4
# Loading work.mgc_axi4_slave_sv_unit
# Loading work.mgc_axi4_slave
# Loading work.mgc_axi4_monitor_sv_unit
# Loading work.mgc_axi4_monitor
# Loading work.master_test_program_sv_unit
# Loading work.master_test_program
# Loading work.slave_test_program_sv_unit
# Loading work.slave_test_program
# Loading work.monitor_test_program_sv_unit
# Loading work.monitor_test_program
# Compiling C:\Users\mou\AppData\Local\Temp\mou@WIN-728EN2N2I93_dpi_5696\win32pe_gcc-4.2.1\exportwrapper.c
# Loading C:\Users\mou\AppData\Local\Temp\mou@WIN-728EN2N2I93_dpi_5696\win32pe_gcc-4.2.1\dpi_auto_compile.dll
# Loading C:\altera\15.0\quartus/../ip/altera/mentor_vip_ae/common/questa_mvc_core/win32_gcc-4.2.1/libaxi4_IN_SystemVerilog_MTI_full.dll
# ** Error: (vsim-3193) Load of "C:\altera\15.0\quartus/../ip/altera/mentor_vip_ae/common/questa_mvc_core/win32_gcc-4.2.1/libaxi4_IN_SystemVerilog_MTI_full.dll" failed: DLL dependent library not found.
#
# ** Error: (vsim-8649) Initialization function 'axi4_IN_SystemVerilog_load' not found.
#
# ** Error: (vsim-3748) Failed to load DPI object file "C:\altera\15.0\quartus/../ip/altera/mentor_vip_ae/common/questa_mvc_core/win32_gcc-4.2.1/libaxi4_IN_SystemVerilog_MTI_full.dll" while trying to resolve 'questa_mvc_sv_find'
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Nios II/e timing anomalies

May 13, 2016, 10:02 am
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I'm experiencing some rather strange timing anomalies when running my Nios II/e based system and I was hoping that someone could help me shed some light on the problem. In the below code example, I'm creating an array of structs of type foo_t, containing two member variables a and b of type int. Note that the third member variable c is commented out for now. I then iterate over the array, accessing each struct by setting the member variable a to zero. All three loop iterations are timed using the Altera performance counter and reported back at the end of the program. I compile the program with no code optimisation using Nios II 14.1 Software Build Tools for Eclipse/GCC. The modules used for the HW platform on which I'm running the program can be seen here. I have two interval timers present, but as you can see from the code below, they are never initialized.
Code:
#include <stdio.h>
#include "system.h"
#include "altera_avalon_performance_counter.h"

#define ITERATIONS 3

typedef struct foo
{
    int a;
    int b;
    //int c;
} foo_t;

foo_t foo_arr[ITERATIONS];

int main()
{
int i;

PERF_RESET(PERFORMANCE_COUNTER_0_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_0_BASE);

for(i = 0; i < ITERATIONS; i++)
{
PERF_BEGIN(PERFORMANCE_COUNTER_0_BASE, 1+i);
foo_arr[i].a = 0;
PERF_END(PERFORMANCE_COUNTER_0_BASE, 1+i);
}

PERF_STOP_MEASURING(PERFORMANCE_COUNTER_0_BASE);
perf_print_formatted_report((void *)PERFORMANCE_COUNTER_0_BASE, alt_get_cpu_freq(), 3, "Iteration 0", "Iteration 1", "Iteration 2");

return 0;
}

Ok, so we know that Nios II/e has no cache memories nor branch prediction and we would expect all three iterations of the loop to require the same number of cycles. This is confirmed when we look at the timing report. Let's refer to this as Case A.

Iteration 0: 124 clock cycles
Iteration 1: 124 clock cycles
Iteration 2: 124 clock cycles

Now comes the part that I'm struggling to understand: If we now add the third member variable c to the foo_t struct, but leave the rest of the code as it is, the loop iterations no longer executes in the same number of clock cycles. Let's refer to this as Case B.

Iteration 0: 155 clock cycles
Iteration 1: 199 clock cycles
Iteration 2: 236 clock cycles

Here is the disassembly of the row foo_arr.a = 0 in the two cases:

Case A:

000402c8: movhi r3,5
000402cc: addi r3,r3,12872
000402d0: ldw r2,-4(fp)
000402d4: slli r2,r2,3
000402d8: add r2,r3,r2
000402dc: stw zero,0(r2)

Case B:

000402cc: movhi r16,5
000402d0: addi r16,r16,12888
000402d4: ldw r2,-8(fp)
000402d8: mov r4,r2
000402dc: movi r5,12
000402e0: call 0x4038c <__mulsi3>
000402e4: add r2,r16,r2
000402e8: stw zero,0(r2)

In Case B, a call to the multiplication function __mulsi3 is is being made. Ok, we know that Nios II/e does not have hardware support for multiplication, fair enough. __mulsi3 is implemented in lib2-mul.c:
Code:
SItype
__mulsi3 (SItype a, SItype b)
{
  SItype res = 0;
  USItype cnt = a;

  while (cnt)
    {
      if (cnt & 1)
    res += b;     
      b <<= 1;
      cnt >>= 1;
    }

  return res;
}

So, in Case B we perform a multiplication. I would understand that this would add to the total execution time of each iteration compared to Case A, but I still expect each iteration to require the same number of clock cycles. At least Case B is deterministic in the sense that it keeps reporting these same numbers for each run.Could anyone please try to give me an explanation on what is happening here? If you require more information, just let me know!

/J
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TRDB-D5M image processing

May 13, 2016, 10:26 am
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We're students working with the DE2-115 board and attempting to interface the Terasic provided DE2-115_Camera example with the NIOS II.
We gray-scaled the video stream and are now trying to interface the example with the NIOS II for image processing.

In Qsys when trying to add a custom component (our SDRAM) we are receiving problems such as:
"DQM[4] must be a multiple of the symbol width 8."
"has write response but no write interface"

We're not sure if we selected the correct parameters for the SDRAM when creating the Qsys component.
Our DQM should be fine with not having a width of a multiple of 8 since it is just a data mask line.
We're beginners with using Qsys and are not entirely sure what mistakes we're making.

Could anybody help us with these errors or direct us to other resources?
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Free (starter) version of ModelSim-Altera can't be lauched

May 13, 2016, 11:05 am
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Dear Forum members,

I have encountered a problem with Quartus Prime and ModelSim-Altera. The tool properly analyzes and elaborates my model but refuses to perform an RTL simulation with the following error message:

Error: Error: Can't launch ModelSim-Altera Simulation software -- make sure the software is properly installed and the environment variable LM_LICENSE_FILE or MGLS_LICENSE_FILE points to the correct license file.
Error: Error: NativeLink simulation flow was NOT successful

The NativeLink log file is not very informative:

Info: Start Nativelink Simulation process
Info: NativeLink has detected VHDL design -- VHDL simulation models will be used

========= EDA Simulation Settings =====================

Sim Mode : RTL
Family : cyclonev
Quartus root : /home/*username*/altera_lite/16.0/quartus/linux64/
Quartus sim root : /home/*username*/altera_lite/16.0/quartus/eda/sim_lib
Simulation Tool : modelsim-altera
Simulation Language : vhdl
Version : 93
Simulation Mode : GUI
Sim Output File :
Sim SDF file :
Sim dir : simulation/modelsim

================================================== =====

Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script /home/*username*/altera_lite/16.0/quartus/common/tcl/internal/nativelink/modelsim.tcl
Error: Can't launch ModelSim-Altera Simulation software -- make sure the software is properly installed and the environment variable LM_LICENSE_FILE or MGLS_LICENSE_FILE points to the correct license file.
Error: NativeLink simulation flow was NOT successful



================The following additional information is provided to help identify the cause of error while running nativelink scripts=================
Nativelink TCL script failed with errorCode: issued_nl_message
Nativelink TCL script failed with errorInfo: Can't launch ModelSim-Altera Simulation software -- make sure the software is properly installed and the environment variable LM_LICENSE_FILE or MGLS_LICENSE_FILE points to the correct license file.
while executing
"error "$emsg" "" "issued_nl_message""
invoked from within
"if [ catch {exec $vsim_cmd -version} version_str] {
set emsg "Can't launch $tool Simulation software -- make sure the software is properly installed..."
(procedure "launch_sim" line 88)
invoked from within
"launch_sim launch_args_hash"
("eval" body line 1)
invoked from within
"eval launch_sim launch_args_hash"
invoked from within
"if [ info exists ::errorCode ] {
set savedCode $::errorCode
set savedInfo $::errorInfo
error $result $..."
invoked from within
"if [catch {eval launch_sim launch_args_hash} result ] {
set status 1
if [ info exists ::errorCode ] {
set save..."
(procedure "run_sim" line 74)
invoked from within
"run_sim run_sim_args_hash"
invoked from within
"if [ info exists ::errorCode ] {
set savedCode $::errorCode
set savedInfo $::errorInfo
error "$result" $savedInfo ..."
(procedure "run_eda_simulation_tool" line 334)
invoked from within
"run_eda_simulation_tool eda_opts_hash"

I have found the same or similar problems on the Altera forum and at various other locations of the web for various versions of Quartus II. However, those users either didn't receive proper answers or the answers didn't work for me (appending an "/" character at the end of the path in Tools/Options/EDA Tool Options, for example).

I'm using Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition on Linux Mint LDME, without any license (the free version).

What could I do to make it work?

Thank you for your help in advance,

bela
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usleep Compiled out?

May 13, 2016, 12:12 pm
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Hello,
I have a Max 10 based project that is running into an interesting/confusing bug.
My project is connected to an image sensor, and is using a Nios based I2C master to control the sensor.
It makes a series of I2C writes to the sensors, where the first write is a reset/don't run command, followed by a 5ms break, then the rest of the register writes for settings.

When I program my fpga, and then use the eclipse tool "Run as Nios Hardware" command, I can see these writes, spaced out by the 5ms pause, (and proper image data), on my logic probe.
When I elf2hex the code, check the hex into the Onchip Memory module in QSYS, regenerate QSYS, recompile Quartus, and use the programmer to push the .pof file, I see these I2C writes, with no 5ms, (and resultantly, no proper image data).

I have tried this process twice now, and cannot seem to get the 5ms pause I need.

So, my question is, is there a possibility the hex file is being compiled without the usleep command, or some other Quartus compile flag I am not aware of, that would be preventing my 5ms sleep pause?


Thank you for any advice (and let me know if you need more details).
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