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Quartus II Command Line Executables not working

May 13, 2016, 1:47 pm
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Hello all,

Newbie to Altera here. I am wanting to use the command line scripting capabilities of Quartus II to automate various tasks such as loading firmware and software onto cards. I'm starting out simple by loading just a .pof onto an FPGA. I was able to do so successfully through the Quartus II Programmer GUI. My issue is that the command line doesn't recognize any of the Quartus command line executables. I'm using the command line on Windows 7. I tried entering "quartus_sh", but the command line doesn't recognize it. All the documentation that I've been looking through talks about how to use the command line tools but nothing about how to set it up. So to sum up my questions regarding this issue,

1. Am I missing some installation? Maybe I need to reinstall the Quartus II Programmer?
2. Am I'm using the command line tools wrong? (maybe the command line has to work out of some specific directory?)

Thanks in advance,

Chris
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A question about parameterized structure between interface and module

May 14, 2016, 1:06 am
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Hello everyone!
I have a design that is using client/server architecture, one server module polling multiple client module periodically to check if the client module needs update, and if the client which is been polled needs update, then server retrieve some information and feedback datas depending on the retrieved information.
Normally I can define a packed structure type to transmit the information from client to server, to simplify the port codes of server module and client module, just like this:
Code:
typedef struct packed {
    logic sig1;
    logic[3:0] sig2;
} client_info_t;
module server(
    ...
    input client_info_t client_info,
    ...
);
...
endmodule
module client(
    ...
    output client_info_t client_info,
    ...
);
...
endmodule
But, when the server and client module are designed as parameterized module, and the bitwidth of structure's elements is depend on the instantiating parameter of client or server module, or both of them, the question is coming:
How can I pass the instantiating parameter from module to the structure?
The following example code can demonstrate more clearly what puzzles me:
Code:
typedef struct packed {
    logic sig1;
    logic[BITWIDTH_OF_SIG2-1:0] sig2;        // BITWIDTH_OF_SIG2 is the parameter that should be passed from client or server module.
} client_info_t;
module server #(
    parameter BITWIDTH_OF_SIG2 = 3        // BITWIDTH_OF_SIG2 should be passed to the structure which is the part of module port.
) (
  ...
  input client_info_t client_info,
  ...
);
...
endmodule
module client #(
    parameter BIT_WIDTH_OF_SIG2 = 3        // BITWIDTH_OF_SIG2 should be passed to the structure which is the part of module port.
) (
    ...
    output client_info_t client_info,
    ...
);
...
endmodule
Although I can split the structure and define multiple port connections for each element, but this method will significantly increase the complexity of module port', and that is not what I want. So, is there any better solution about it?
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Nios on DE0-Nano-SoC

May 14, 2016, 2:49 am
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Hello,
i have question about Nios on Cyclone V on development board DE0-Nano-SoC. I have design with some input/output pio, timer and nios processor, short program and i download bitstream and elf in command line - nios2-download -g test.elf. It goes ok, but when i try to run nios2-terminal, it failed with message No jtag uart was found.
How can i connect ? (i tried nios2-terminal --device 2 or nios-terminal --cable "De0 Soc Uart", but without success)

Thank you for some answer.

Honza Naceradsky
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cyclone4 JTAG issue

May 14, 2016, 3:36 am
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One of the FPGA's JTAG on our PCB having three cyclone4 FPGA's (EP4CE55F23I7N) is going faulty after some time.

I probed and checked the JTAG signal of the FPGA,whose JTAG is going faulty(U2) with the other stable JTAG FPGA's on board(U1,U3) and also with a DIFFERENT DESIGN PCB WHOSE JTAG is STABLE.



I observed no significant difference in the levels and behavior of the signals.


Also, while i was probing theU2 FPGA's JTAG signals, i found that the JTAG first became inconsistent in connecting. I started the JTAG debugger tool and it gave a message that the TDI pin appears to be shorted to ground.After some time the JTAG was completely down and did'nt connect. I measured the TDI pin's resistance wrt ground and found it to be 2 ohm(while in working FPGA it is in kilo ohms).



As this happened during probing, i am suspecting some loading on the JTAG pins of the FPGA going faulty. Then i measured the track lengths of the JTAG signals of this FPGA(TDI,TDO,TMS,TCK) on the PCB and found it to be approx 155 mm each.


Now can this track length create problems with JTAG consistency??

Or there is anything else we should suspect.
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Pb with shifting

May 14, 2016, 5:08 am
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Code:
architecture behave of convo is

signal rg: std_logic_vector(1 downto 0):="00";
signal c1: std_logic_vector(31 downto 0);
signal c2: std_logic_vector(31 downto 0);


begin


process(clk)
begin
if (clk 'event and clk='1') then
for i in 0 to 31 loop


c1(i)<=wr_data(i) xor rg(1);


rg(1)<=rg(0);        :confused:
rg(0)<=wr_data(i);  :confused:


end loop;
end if;
end process;


C1_out<=c1;
--C2_out<=c2;


end;
Hello mates, I am having problem with my code : the instructions" rg(1)<=rg(0); and rg(0)<=wr_data(i); " seems that they r not working
I start my waveform(with no error in synth) and the result show that it is keep doing c1(i)<=wr_data(i) xor rg(1); for the initial rg(1) !!!
What could be the problem ? is it code syntax or what ?!
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SoC EDS's barematel gcc compiler is not updated

May 14, 2016, 7:30 am
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I was trying to 'make' my preloader generated from bsp-editor but I had problem on that.
The problem starts when :
make[3]: **No rule to make target 'cygdrive/c/...../software/spl_bsp/uboot-socfpga/include/linux/compiler-gcc5.h' , needed by ....

So I checked the gcc version by:
$gcc --version
gcc (GCC) 4.9.2
Copyright (C) 2014 Free Software Foundation, Inc.

It is not up to date with the current version from website:
What's New in SoC EDS 16.0


  • Baremetal gcc updated to 5.2.0





I had Soc EDS 16.0 installed on my computer. Anyone has idea how to fix this? Thanks a lot :)







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Cyclone V - EMAC ARP receive error

May 14, 2016, 12:53 pm
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I have connected a Micrel KSZ8864 PHY (10/100MBit, MII Interface) to the EMAC0 on a MCV Coremodule (Cyclone V). The MII interface of the PHY is routed through the FPGA and the communication with the PHY is done over SPI (not MDIO). For the U-Boot bootloader I have adapted a driver from the Micrel website to communicate with the PHY.

If I send a ping, the transmit process works well but the response is not recognized from the EMAC. Anyway, if a TCP packet is send to the EMAC during ping, this packet is received and detected correct. If I switch back with U-Boot to the default configuration with the GMII Phy and use it with the MCV Development board all works well.

Any idea why the ARP response with the 100MBit Phy is not received ?

Thanks,

Klaus
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Fatal Error: Int Divide By Zero

May 15, 2016, 3:49 am
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Fatal Error: Int Divide By Zero
It's driving me crazy. I couldn't figure it out what is the problem. I mean, all versions of quartus 2 (ver 8,9,9.1,9.2,10.0,10.1... trust me I downloaded and tried all)

shows me this one: there is no exception.
---------------------------------------------------------------------------------------------------------------
*** Fatal Error: Int Divide By Zero
Module: quartus_map.exe
Stack Trace:
0x258e4: GEN_MACHINE_INFO::get_cache_size + 0x3b4 (CCL_GEN)
--------------------------------------------------------------------------------------
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab1 -c lab1
-----------------------------------------------------------------------------------------------------------------
End-trace

I have no idea what is wrong with mine... It is my laptop setting or something like that?


I would really appreciate it if you give me some solutions to make. Thank you. Hope you're having a great day.
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Cannot initialize a 2-D array of bytes from file directly (ram_init_file / $readmemh)

May 15, 2016, 8:12 am
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Hello forum Members,

I have been experimenting with file-based initialization of Verilog multidimensional arrays.

Until now i succeeded initializing with the help of flat temp. array
------------------------------------------------------------------------

Code:
reg [7:0] charMem[25][80];
reg [7:0] colMem[25][80];

reg [7:0] charMemTmp[2000];
reg [7:0] colMemTmp[2000];

initial
begin
 $readmemh("DE0_CV_SCREENCHAR.txt",charMemTmp);
 $readmemh("DE0_CV_SCREENCOL.txt" ,colMemTmp);
 $readmemh("DE0_CV_SCREENPAL.txt" ,palMem);
 end
and

Code:
always @(posedge CLOCK_50)
begin
 if (~RESET_N)
 begin
  integer row;
  integer kol;

  for (row=0;row<25;row++)
  begin
  for (kol=0;kol<80;kol++)
  begin
    charMem[row][kol]=charMemTmp[kol+row*80];
    colMem[row][kol]=colMemTmp[kol+row*80]; 
  end
  end
 end
end
=> This works fine, i use a flat helper array read in the data and copy everything to a 2-d array.


However if i try to read it directly:
-------------------------------------

Code:
reg [7:0] charMem[25][80];
reg [7:0] colMem[25][80];
initial
begin
 $readmemh("DE0_CV_SCREENCHAR.txt",charMem);
 $readmemh("DE0_CV_SCREENCOL.txt" ,colMem);
 $readmemh("DE0_CV_SCREENPAL.txt" ,palMem);
end
=> I get: "10853 verilog HDL error ... : argument 1 to $readmemh must be a memory identifier ???


I also tried reading from a .mif file (1d file 2000 x 1 byte Width=8 depth=2000):
-------------------------------------
Code:
(* ram_init_file = "DE0_CV_SCREENCHARMEM.mif" *)  reg [7:0] charMem[2000];
(* ram_init_file = "DE0_CV_SCREENCOLORMEM.mif" *) reg [7:0] colorMem[2000]
;
=> this works fine


Reading 2-d directly from .mif file is not ok:
---------------------------------------------------
Code:
(* ram_init_file = "DE0_CV_SCREENCHARMEM.mif" *)  reg [7:0] charMem[25][80];
(* ram_init_file = "DE0_CV_SCREENCOLORMEM.mif" *) reg [7:0] colorMem[25][80]
;
=> this works for the first array (got lucky ?) but for the second array it does not.


Does anybody know how to initialize the 2-d array from a file using ram_init_file or $readmemh ?

I a using Quartus 15.1 on Win7.


Thanks in advance,
Johi.

Update:
I have a hunch (from debgging the .mif files generated by quartus from the .txt initialization files that depth needs to be 25 and widt 640 = 8*80
I will try this and come with an update.
Johi.
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Arria II GX TTK configuration problem running at 6Gbps

May 15, 2016, 1:30 pm
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Hi all,
I am trying to get the TTK to work @ 6 Gbps with ARria-II GX and having difficulties. I was wondering of anyone has suggestions or a TTK project with 6 Gbps Arria II GX to share.

Altera has an example design for 2 Gbps for Arria II GX and that works.

Modifying to run design at 6 Gbps I assume is with the following steps, and I am unable to successfully complete it.
1. Test existing design as it is @ 2 Gbps. (Quartus 14.1, 15.1, 16.0 all works)
1. Take 2 Gbps design to use 8b/10b encoder (HW module) and test it. (Sometimes work. Synchronization issue. After startup it either works or not... Seemingly random)
2. Change datapath to 16 bit wide and test it. (Doesn't work. Observed problems with custom PHY megacore. Although I configure datapath to 8/16/32 etc. widths, I/Os seem to be still recognized as 8 bits. Quartus recognizes it and inserts its own adapters while compiling.)
3. Change clock rate to 6 Gbps. (Never got there).


Thank You,
Zeki
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Clock data recovery

May 15, 2016, 2:05 pm
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Hey, i am quite new to fpga stuff but in my current project i need to decode a 40MHz Manchester encoded signal. As far as I understood there are different ways to do this but one is to use a pll to recover the clock from the input stream.

Is this correct and if so can someone tell me how to configure the pll? (So far I only used the megafunctions to create a pll with static frequency)

I was already looking for some application notes but didn't find too much Information.
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Read a wav file in an SD card with DE1 SoC

May 15, 2016, 6:14 pm
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I am begginer in SoC devices, i have to implement a aplication that play a wav file from sd card memory in a DE1 SoC board, i try with the LXDE system but there is not audio output. I would like to ask you about how can access to sd file and implement the audio core. Thanks
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DE0-nano - interface OV7670 and VGA monitor

May 14, 2016, 11:57 am
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Hello
I'm having hard times finding how to interface 18 pin OV7670 with DE0-nano board, ive managed to print something (red square) on monitor, but i cant even move with camera. If You guys know anything about my issue please response :D

Imekxus

@edit
and yes, ive checked google, ive stuck for 2 days now, wasting a lot of time wouthout even making a little step ;/
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Using TCL (or other Script) file in Quartus to automate module/circuit creation

May 15, 2016, 9:29 pm
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I have various simple modules (Verilog) written and included in my Quartus project file.


Lets say each such module receives a 8 bit input, increments the value and outputs the new value.


Depending on my requirement I may want to use as many as n instances of such module. Is it possible to using scripts where in user may input the value of n.


My example is very simplistic to make the problem statement clearer. My end result is to have a Simple Wireless sensor network with n nodes. I may simulate the network characteristics using various values of user defined n. My hardware is Altera Cyclone4GX.

My question is, is it possible. If yes, Could anyone show me the direction please as reading the TCL reference manual didnt help me much.
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Is there a Synchronous CFI (Common Flash Interface) controller to NIOS II?

May 15, 2016, 10:01 pm
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I want to connect NOR Flash to NIOS II Soft processor in Qsys. i want to use synchronous interface to NOR flash.
Is there a Synchronous CFI (Common Flash Interface) controller to NIOS II?

Thanks in advance,

Sagar
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can you help me?

May 16, 2016, 3:31 am
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i wanna code in vhdl for RFID 125k based on FPGA
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loading RBF file to Atera Cyclone V through SPI port from Linux

May 16, 2016, 4:27 am
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I am using I.MX6 processor to configure (loading .rbf file) the altera cyclone V FPGA through the spi port, for that i am doing a while loop and for each iteration i am reading some bytes from the rbf file and sending the readed bytes through specific spi port from my processor the the spi port of the FPGA. Thei operation take a lot of time, so i am asking if there is a Linux driver that allow this operation. (all the drivers that i am foundig use PCi port or GPIOs as this one https://github.com/ntb-ch/fpga_loade.../fpga_loader.c )
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Need help with my final project design (Ethernet Transmitter)

May 16, 2016, 6:06 am
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Hi all,

My goal is to build Ethernet Transmitter based pipeline.

I already built few things and I have few questions:

1. I want to take my input (ethernet 2 / 802.3 frames) from a TEXT file, and I know that each frame has a different size, also, when I read from file to a Register, I need to mention his size (std logic vector(n-1 downto 0). How can I read input when I don't know the size of the std logic vector?
I thgouht to make an assumption and decide that all the packet will be the same size, but it doesn't sound that good..

2. I need to work with DM9000A in order to work with the ethernet controller, is there a good tutorial for it? (I don't know how to work with Nios 2)
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Array of integer to std_logic_vector !?

May 16, 2016, 8:04 am
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Hello guys !

Description : the input is an std_logic_vector ..... the outpout must be an std_logic_vector BUT,
I read every element of the input and check if it is '1' then write 1 to an array else write -1 .
the final array should be converted to an output which is an std_logic_vector !!!!


For example
INput : std_logic_vector (5 downto 0) :="010101";
====> array = { -1 1 -1 1 -1 1}
OUTput : std_logic_vector (5 downto 0);


What are the possible solution to go from array to my output?!!!
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CyClone IV PLL Dynamic Phase Shifting Probem

May 16, 2016, 8:25 am
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I am experimenting with dynamic phase shifting using a Cyclone IV, DE0-Nano board and Quartus 13.1. My reference input clock is 50Mhz and I have several output clocks all configured for 50Mhz as well. My problem is that when I apply the dynamic phase shift, all the outputs shift simultaneously by the same amount. I am unable to select a single output for shifting via the counter select (cntsel[2:0]) inputs. I'm probably making a simple mistake, but am out of ideas.
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