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Parallel thread execution based on thread id

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Hi,

I was looking to execute different instructions by threads depending on the thread in parallel.

Example, if there are 4 instructions, I1,I2,I3,I4 , and I want thread 1 should execute I1, thread 2 execute I2, and so on, in parallel - how could I do it with the help of this tool?


Thanks.

LPM Shift Reg ( Shifting Issues)

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Hi all,


I have read the megafuction for the LPM Shift Reg.

Is it possible to set the amount of shifts you want in the shift register?

I plan to implement a left shift by 6 on a shift register for my design.

Migrating from Quartus II 9.0 Web to Quartus Lite 16.0 with MAX II to MAX 10

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All, I have a major attempt. (at least I think so). I am jumping from Quartus II Web up to Quartus Lite 16, and I am wanting to modify my existing MAX II files and migrate them into a MAX 10 device.

I have installed the Quartus Lite 16, but have not ran it yet as I want to make sure it doesn't try to do something with my working/existing Quartus 9.0. What are some things to watch out for during this upgrade?

Can I load and recompile my existing .qpf, .bdf, .bsf, .sym ?????? files or should I just restart from scratch and re-enter my schematic into Quartus 16 setup for my new MAX 10 device?

Thanks in advance with this task I am about to step into.

Keith

Arria V SoC Transceivers

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I am trying to bring up a transceiver project on the Arria V SoC development board and have thus far had no luck. I've tried to use a transceiver toolkit example project with new device and pin assignments for my board and while the transceiver link appears in the toolkit, it has status N/A and is red. I have tried to start a new project using the Custom transceiver phy with the same setup as the example project and cannot even find the transceiver path in the toolkit - it is not automatically linked as all guides are saying it should be.

How do I access the transceivers from the Transceiver toolkit to verify they are working??

altremote_update in Cyclon III

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Hi all,
I am trying to implement the altremote_update megafunction in a cyclon III FPGA without success.
I followed the relative User Guide driving the altremote_update with a Finite State Machine and generating two configurations, one Factory and one Application (the configuration mode setting is to Remote).
These two configurations are combined together in a .jic files where I specified the start address 0x0 for the Factory and 0x100000 for the Application (exactly in the middle of my EPCS16).
In order to fit the two configurations in the EPCS16 device, I enabled the .sof file compression feature and after that I generated and downloaded successfully into the FPGA the file.
When the Factory configuration is running, I set the parameters enabling the Watchdog, the Cd_early, the OSC_int and the Boot Addr taking care for this last to write 22 bits instead of 24(so 0x040000 instead of 0x100000).
Before triggering the reconfiguration I checked the parameters in the input register performing a read action with read_source signal set to 0x3 and the values that I receive back are in line with the expected ones.
Now the problem: after the reconfiguration trigger, the configuration loaded is always the Factory and not the Application.
In order to find out the reason of that I read the status register with read_source signal set to 0x1 and the reconfiguration trigger condition field reports a CRC error as root cause of the Application configuration fail.
The boot Address is the expected one, as well as the Watchdog enable, the Watchdog Timeout and the Osc_int but Cd_early setting is wrong (it is set to zero while my expected value is one).

Just for testing purpose, I tried to set the boot address for the application configuration to 0x0 (the same boot address used for the factory) and in this case I had no CRC error after the reconfiguration trigger, but after a while I got the Watchdog timeout error. This is expected because in the Factory configuration there isn't a watchdog timer reset strategy implemented (as in the Application configuration).

My feeling is that I set a wrong boot address for the application configuration.

Could you please help me?

Thank you in advance.

Davide.

FPP Configuration Timing: Clock Stop = high

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We would like to configure a Cyclone V GX C5 using FPP via a TI DSP's EMIFA (External Memory Interface) bus (in Asynchronous mode). VC-52007 2015.12.21 Figure 7-3 mentions in note (5): If needed, pause DCLK by holding it low.

Question 1: Is this clock pause option also applicable to Figure 7-2, i.e. when the DCLK-to-DATA[] Ratio (r) = 1?

Question 2: Would it also be OK to pause DCLK by holding it high?

If so, we would want to connect the TI DSP EMIF's EMA_nWE (Write Enable) strobe to the Cyclone's DCLK pin, which would result in an unbalanced DCLK signal high for 20ns and low for 6.5ns, occasionally held high in the inactive state.

Any comments on the feasibility hereof, please?

Wit's end: Cyclone III PLLs lose lock when more than one FPGA connected?

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Please forgive me, I'm at wit's end here. Any suggestions welcome.

I've got a very dense Cyclone III design (~90% utilization) with a very large number of DDR I/Os (>250 pins), using all four PLLs (in order to spread out the power consumption by phase-shifting unrelated logic).

Surprisingly, it works great. No errors, no bit-flips, no PLL lock lost.

The cyclone and the peripherals it talks to are on a card; eight of these cards plug into a backplane which supplies power, 10mhz base clock, and JTAG. I can use any card in any slot and things work great. If I so much as plug in a second card (nevermind programming it!) all four PLLs on the first card immediately lose lock (output "locked" glitches low) and misbehavior begins. There are no high-speed signals between the cards and the backplane (fastest toggle is the 10mhz base clock).

This baffles me because the unprogrammed card draws hardly any power, and nothing on it is switching. I've probed the shared 10mhz clock, vccA, vccint, and vccio on a scope, and nothing budges by more than 5mV, which is less than 1%. In particular the clock waveform is the nice smooth curve you'd expect. Everything is decapped out the wazoo (excessively, perhaps... over 1200uF of bulk capacitance per FPGA on each of vccint+vccio, plus two dozen 1uF+0.1uF ceramics and a 47uF tantalum for good luck).

I'm at a loss here. I've gone through the list of reasons for PLL lock loss and none of them apply -- if any of them were the cause, then one card wouldn't work in isolation -- but it works great!

Very puzzled. Is there any other advice out there on troubleshooting PLL lock loss besides the checklist at this link?

https://www.altera.com/support/suppo...loss-lock.html

Edit: I should also add that it isn't the "plugging" action that's responsible -- if I power up the system with two cards physically installed, then attempt to program one of them, I get the same PLLs-frequently-losing-lock behavior. So any electrical noise caused by the physical action of inserting the second card into the slot can't explain the failures.

DE1-SOC working without DS5 tool

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Recently I got the DE1-SOC board. I could run the board and wrote codes for the FPGA and NIOS apps.
Now I want to use the ARM processor. I tried a lot but found that I needed DS5 altera edition tool.
My first question is, can I work on SOC arm baremetal app without using DS5? NIOS programming used the eclipse coming with the quartus without SocEDS.
I knew that the free license of the community edition of the DS5 is free but I cannot run the program from over there. So my second question is, is the community edition enough for working?
Thanks

Data error using TSE at 1Gbps with SERDES in Cyclone V

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I have instantiated the TSE using a 1000BaseX interface and the SERDES in the Cyclone V. the fabric interface is GMII. I get errors at the beginning of each received packet. When I send packets generated in the fabric and loopback the optical ethernet interface, the first receive byte of every packet is overwritten with 0x55. I built a 500MHz data collection element in the fabric (SignalTap does not work at 500MHz) to look for a potential timing issue, but the first byte is really 0x55 instead of the 0x01 I am sending. Packet contents are just a counter. The packet length is correct. I have attached 4 images of the logic capture output showing the start and end of the transmit and receive packets. The transmit data and transmit enable are the top two traces. The bottom 2 traces are the receive data and receive data valid.

Even more strange: When I connect an Ethernet test set to the optical port, the fabric receives six bytes of 0x55 prepended to the packet, and the remainder of the packet is complete. That is, the packet is extended by 6 octets at the start.

Anyone have an idea what could cause this? When the TSE is configured for 1000BaseX and GXB (SERDES) interface, there are not many options to toggle in the IP.

Thank you

Better than Altera tools?

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Hello, I wanted to know if anyone has tried the SoC development tools from Xilinx and if they are better than Altera's SoC development tools? Vivado is Xilinx FPGA development tool and SDSoC is the ARM development tools.

Thanks

MAX10 primitive TRI-state output buffer ERROR

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All,
I am converting a MAX-II design over to a MAX10.
I get the error 12168 I/O primitive ALT_OUTBUF_TRI is not supported for the selected family (MAX 10).

What/where can I find information about what primitive to use for a tri-state pin for the MAX10? I erased all the original ALT_OUTPUT_TRI devices and redrew new ones thinking it might needed to re-instate the symbol, but.... Also, it seems to me that the software shouldn't allow me to draw it in the first place if it isn't supported.

(original Quartus II 9.0 WEB with a MAX-II EPM1270T144C4)

now learning
Quartus 16.0 Lite
10M08SAE144C8G

Thanks,
Keith

Quartus 15.1 and Quartus 16.0 Not Responding

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Hi,

Whenever I'm compiling my design on Quartus 15.1 or Quartus 16.0, the Quartus becomes not responding and I've to end the quartus process. I'm using Altera Max10 family device 10M50DAF484C6GES and my computer has 8GB of RAM which I think is enough to run any device. I have compiled the design earlier and it worked. Also note that I've also cleared any metadata folders from my project. Can anyone please help me resolve this issue ?

Thanks,

Quartus Waveform simulator

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All,
I have upgraded to Quartus Prime 16 Lite and have tried to recompile an old existing (simple) circuit that I used in Quartus II Web 9.0. It seems to compile fine but where did the simple Waveform Simulator go??????????

I had to upgrade to try to move an existing MAX-II design into a MAX-10, and Quartus 14 and higher support the MAX-10. I have installed 14 but it works that same as 16, hoping it wasn't too much of a change from 9.0 with the simulator function, but.... it was.

It was a simple 1-button <click> that tied the current schematic to a waveform simulator.

Now it starts ModelSim Altera Starter program that isn't embedded in the Quartus window.
Where's my waveform??
What happened to my .VWF files?
Why doesn't it load these files?
Do I have to setup these original sim waveform files.?
What happened to the simple 1-button (maybe 2-button) <click> function?

Being frustrated here.

Keith

Debugging FPGA Timer on AXI bus generates RESET EXCEPTION

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I’m starting this thread because I haven’t been able to find anyone else who is having this problem. I’m working with two boards: the DE1-SOC eval board and a custom board that uses a Cyclone V 5CSEBA2 device. I’m working with one of the ARMs in the device and I’m trying to control/communicate devices implemented in the FPGA fabric that are slaves on the LW AXI bus. This is a bare metal project.
So far I have two custom modules each with a few control registers plus a system ID register. I have also created a timer slave for the LW AXI bus and I’m using it to generate interrupts at the rate I expect my data processing module to generate interrupts. I’m doing this so I can get the interrupts working without having to worry about the complexity of the data processing module. The interrupt handler accesses a few registers in the timer and sets a software flag (I’m not doing any print statements). When I step through the code with the DS-5 debugger everything works. However if I just let the program run without setting break point a reset exception is generated. As an experiment I’m also using one of the ARM timers to generate the interrupt but I still bang all the registers in my AXI bus modules during the ISR and it works fine – all the register are written with the correct values and the system doesn’t generate any exceptions. I’ve also experimented with just polling the AXI bus timer instead of using interrupts and I get the reset exception. This happens on both my eval board and my custom board. I originally tried this exercise using Altera’s Avalon timer and got the same reset exception behavior. I’m using the Altera-SoCFPGA-HardwareLib-Timer-CV-GNU-debug example program provided with the DS-5 tools as the go-by for setting up the GIC and for the interrupt handler.
I’ve verified that my AXI interface is not violating any specs (I’ve also used this interface module in several Zynq projects without any issues).
Any help would be appreciated.

Is the fftpts_in signal a counter

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I was reading through the FFT ip core guide (https://www.altera.com/content/dam/a.../ug/ug_fft.pdf) and looked at table 3-2. I could not determine if the signal was a counter of how many points have gone through the core or if the input remains constant, assuming that I want the same n-point FFT for the entire time.

Qualtus Prime 16 and DE4 with DDR2

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I use Terasic DE4-230 with Qualtus Prime 16.0

My DE4_Install/demonstrations/DE4_230/DE_DDR2_UniPHY/DE4_DDR2 fit failed with

error 169008 : Can't turn on open-drain option for differential I/O pin M1_DDR2_clk[1]

same error with M1_DDR2_clk_n[1], M1_DD2_dqs[1], ... M1_DDR2_dqsn[7]

and error 171000 Can't fit design in device.

same problem with DE4_GOLDEN_TOP.


and DE4 System builder Generate with DDR2 SODIMM_1 or _2 shows Dialog bellow

---------------------------
Information
---------------------------
===== DDR2 System Builder warning =====
Please add the DDR2 Controller IP to your Quartus project, follow by
the steps below to prevent any errors from occurring during compilation.

1). Create correct pin assignment for DDR2.
2). Setup correct parameters in DDR2 controller dialog.
3). Execute TCL files, generated by DDR2 IP, under your Quartus project.


---------------------------
OK
---------------------------

where can I found "correct pin assignment for DDR2" ?

MAX10 watchdog use // which version Quartus?

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I want to use for new project first time MAX10 FPGA so some of my questions may look "primitive" ...

I read that Quartus Prime is needed - today's version is 16.0 but it only offers to install Aria10, I can not see MAX10 support. As Aria10 support needs tens of GB to be installed I decided to go back to version 14.1 where
MAX10 support first appears. It is only about 300MB package support to be installed for 14.1 . But it says it is not (?) Quartus Prime 16.0 but Quartus II 14.1

There is inside MAX10 also watchdog that must be disabled (if not used) by first time erasing whole chip. I read a lot of docus but I can not find any information how to kick this watchdog from FPGA. What I only found is that IP for
remote update includes inside already support to handle watchdog during upgrade. Another info I found is that MAX10 is AVALON BUS ready. It seems that watchdog is implemented in AVALON MM bus. (memory mapped)
I do not know yet how to work with this AVALON BUS but it is not an issue now.

There is no support (any IP block) in Quartus II 14.1 to handle watchdog. At least I can not find it. I have not installed Quartus Prime 16.0 yet as I am even not sure MAX10 support is there as it is not offered for download, just for Aria10.

What I am overlooking? How to handle watchdog for MAX10 from FPGA? What software (IP) I need for this?

thank you

MAX-10 Input clock information

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Hi Folks,


I am using MAX-10 FPGA (P/N: 10M02SCU169C8G) in my design.
Application of the FPGA is to manage board controls and power sequencing.


Here clock input information is limited in guideline.
I have attached the snapshot of the design connection guideline for reference.



Please suggest what is the input frequency required for the FPGA and which pin need to be used for clock inputs?


Thanks
VT
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What are difference between NIOS II processor And DSP processor

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hi friends can any one brief the difference between NIOS II and any other DSP processor

Asynchronous FIFO control problem in Quartus ii

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I have a project in Quartus ii. The data captured by an ADC is sent into a filter to filter its high frequencies components of received signal. Then the filtered data is transformed by a FFT module. But the data has period T. ADC won't collect data for a short time at the start of period. The point of FFT is 8192.The number of collected data lesses then 8192, so I have to add some zero at the end of the collected data. The FFT IP core works in burst mode, so i need a asynchronous fifo to buffer the data,named LPF_FIFO. But the rdclk and wrclk of LPF_FIFO is the same.
For example, the number of collected by an ADC is 6500. The asynchronous fifo,LPF_FIFO, is followed by a filter, which buffers the filtered data. Firstly, The 6500 filtered data was written into LPF_FIFO, then I read the 6500 data from LPF_FIFO. i may read only 1000 data ,then the next 6500 data of next period has came. I use a counter to count the number of data read from the LPF_FIFO . when the value of the counter is 6500,i stop read.
this method works in modelsim.But when i program the code into a board,i found the code won't work correctly sometimes in signaltap ii.
the control of LPF_FIFO may failed.
someone can help about how control asynchronous fifo in this condition . The fifo is read when it is written.
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