I am developing a project using the Stratix V GS DSP development kit. I need to deliver a clock to the high speed transceivers on the HSMC ports, however due to the design of the dev kit, all but one of the dedicated reference clock pins are not accessible to external reference clocks (don't know why it was designed that way!). In my current design I have been using one of the dedicated PLL clock inputs to drive an FPLL by the transceivers, the output of which can in turn drive the CMU PLLs in the transceiver bank. The trouble with this approach is there is theoretically quite a lot of jitter as a result - an LVDS input, the global clock network, two PLLs, and then the transceiver clock networks.
On the board there are a pair of SMA connectors (CLKIN) which upon examining the schematic feed through a low jitter clock multiplexer and in to the dedicated reference clocks of the transceiver bank. However I am struggling to understand the termination scheme used. Attached is an image from the schematic.
term.jpg
Each SMA (which I presume is 50 Ohm?) is terminated with a 100 Ohm resistor to ground (as opposed to differential between the SMAs!). Then both are AC coupled using 100nF capacitors and then terminated again using a 124 Ohm resistor to GND and an 84.5 Ohm resistor to 3.3V.
By my calculation, the bias termination after the AC coupling (124 || 84.5) equates to an effective 50 Ohm termination which on its own would make sense. However if we add in the effect of the DC coupled 100 Ohm termination, that equates to an overall input impedance of 33 Ohm!
I don't understand why a pair of 50 Ohm SMA connectors which are supposedly differentially routed would have not only a single-ended termination each rather than differential, but also why this termination would be effectively 33 Ohm which will cause a massive impedance mismatch.
Is there something I'm missing?