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MAX3000 End of LIFE

July 11, 2016, 3:37 am
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I had designed some years ago two boards (digital input and digital output) each with a PLD type EPM3032ATI44.
Now having to design a new board mid-DI and mid-DO, the easiest choice would be to put back a PLD EPM3032ATI44, but on the site I find no information relative to its expected life. :confused::confused::confused:


Giovanni Sica
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Converting example from using TCP/IP to UDP

July 11, 2016, 3:48 am
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I adapted the example "Nios II Ethernet Simple Socket Server
on MAX 10 FPGA Development Kit" to send data from a MAX 10 board
to a PC with Matlab. The datarate I get is about 5 Mbyte/s
with TCP/IP.

Is is simple to change the code to use the faster UDP in stead
of TCP/IP? This was suggested by reading that TCP/IP uses
the send command, while UDP uses sendto. I hope for a
simple command substitution :).

Jos

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altpll "loop filter resistance" parameter: resistance to filtercap or to charge pump?

July 11, 2016, 4:46 am
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Hi, the altpll reconfiguration interface has a parameter called "loop filter resistance".

Is this the resistance imposed between the charge pump and the VCO control node, or is it the resistance between the VCO control node and the filter capacitor (i.e. the capacitor whose capacitance is one of the other parameters)?

Put another way: is this R1 or R2 in the figure below ("from PLL" means "from charge pump")?

If it matters, this is for a Cyclone III.

Thanks.
Attached Images
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MAX 10 LVDS and DDR

July 11, 2016, 9:55 am
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I haven't used LVDS before, and I want to interface to an 12-bit 125-MSPS ADC running 6-bit LVDS with DDR. Does the MAX 10 LVDS interface support this? If not, can I still use the MAX 10 LVDS interface, but with some additional HDL for DDR?
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tools to understand Altera OpenCL scheduling

July 11, 2016, 3:34 pm
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Hi,

Is there any tool or method to know the scheduling of threads done during the execution of a kernel?

Thanks.
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Reference design: VGA Controller and Nios II availability.

July 11, 2016, 5:13 pm
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Long time no post. Would just like to request where I can download the reference design found here:

https://www.altera.com/products/refe...iosii-vga.html

It does not contain a download link and I have searched the website, and forum, but to no avail. It is an older reference design but would help me a great deal as I would like to see how it implemented the DMA in the VGA controller.

Thanks!
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LVDS critical warning

July 11, 2016, 5:19 pm
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hello

I got many warnings which are ...
"ID:12887 Too many 2.5-V SE IO in bank <name> with LVDS RX pin <name>. Reduce the number of 2.5-V I/Os used and re-run the analysis again. ...."

and I am told its solution that "Reduce the number of SE IOs".

I have some questions about this.

1. what is SE IOs
actually I'm just told SE.
what is it?

2.what happens?
since those are warnings, I got sof file.
what will be happened if I use this?

3.any solution.
there is not plenty of space for removing pins
what can I do then?
should I change FPGA?

thanks in advance.
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Error (10028): Can't resolve multiple constant drivers for net at

July 11, 2016, 6:09 pm
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All, Here is one of my Verilog trial-learning code:

================================================== ============
Code:
// Verilog learning example
module SRAM_Read_Write_Sync ( nrst, Writeclk, Readclk, EQ, write_addr, read_addr);

    input nrst, Writeclk, Readclk;
    output EQ, write_addr, read_addr;

    // Declare the address counters as 9-bit counters
    reg [8:0] write_addr;
    reg [8:0] read_addr;
    reg EQ;
   
    // reset address to 0 if NRST goes LO
    always @ (negedge nrst)
    begin
        write_addr = 0;
        read_addr = 0;
    end
   
    // increment Write address
    always @ (posedge Writeclk)
    begin
        write_addr = write_addr + 1;
    end

    // increment Read address
    always @ (posedge Readclk)
    begin
        read_addr = read_addr + 1;
        if (read_addr == write_addr)
            EQ = 1'b1;
        else
            EQ = 1'b0;
    end

endmodule
================================================== ================
All, (the text in RED) when I try to use the negative edge of my nrst as a reset for my address counters I get the
Error (10028): Can't resolve multiple constant drivers for net "read_addr[3]" at SRAM_Read_Write_Sync.v(26)
If I remove the RED code it compiles fine.

How should I implement a nrst signal that take precedence over any other signals that reset the address counters?

Thanks,
Keith
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NIOS soft reset

July 11, 2016, 6:40 pm
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Hi,

I am currently working on a Cyclone V :5CEFA4U19C7. It has a Nios II processor in it. I want to know if i will be able to do a soft reset for that processor. If so , kindly guide me through the procedure.

Thanks,
Sid
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Problem : USB Blaster Driver Cable DE0

July 11, 2016, 11:35 pm
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Hello,
I have bought a Altera University program terasic DE0 FPGA Cyclone III, but the OS on my computer is Windows 10 and the driver for the USB_Blaster can't be functional with this OS. Where can I found the good driver for my device ? Actually I'm trying to upgrade the Quartus II 9.0 to Quartus II 13.1, maybe the drivers ar good in this versions ?

Thank you for your answer if you can help me
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Problem in receiving data path TSE

July 12, 2016, 1:08 am
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Hi,



The altera based designed IO FPGA supports three Triple Speed Ethernet ports (10/100/1000 Mbps). Two of the Triple Speed Ethernet port use SGMII interfaces(Marvel Phy) and one uses the GMII interface(Broadcom Phy). Master interface for PHY device management is done with management data I/O (MDIO) interface for all the ports. I/O FPGA Ethernet functions have a set of registers for initialization and configuration in the PCIe space. To address the Ethernet function, it is mapped to the PCIe memory-mapped address space of the Processor SoC(Bay trail –E38XXXX). TSE Ethernet MAC and external PHY setup and register configuration will be done in the Linux kernel space(yocto-linux-3.14). A set of MSI-X/MSI interrupts and its handlers will be associated with this function. Ethernet communications is provided using a Socket interface and specifically the Berkeley socket API. The Ethernet application will use the Socket APIs which are exposed in user space. A net driver shall be register and a device node will be created by the kernel driver for each Ethernet port interface in the Linux subsystem “/dev/iofpga/ethx”.When i am testing the data transfer using iperf tool, only few kbytes of data received and after that Ethernet stopped receiving the data and not able to generate the interrupts. Please suggest for the solutions to make receiver section working fine. There is also packet differences in MAC received(more) and interrupt generated. Interrupt is generating per packet. We also allocated 64 descriptor for receiving the data but driver is not moving to next descriptor. keep on fetching the data from first descriptor itself.

Driver code is designed in base with altera tse_main.c & altera sgdma.c.

Please find the below log when I am receiving the packets.

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.060805] desc base address =0x72e5f000 sourse addres = 0x0

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.060805] destination address =0x126840

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.060805] next desc address =0x72e5f020

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.060805] pktlength =1060

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.060805] desc base address =0x72e5f000 sourse addres = 0x0

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138471] destination address =0x50040

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138471] next desc address =0x72e5f020

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138471] pktlength =1060

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138664]

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138664] desc base address =0x72e5f000 sourse addres = 0x0

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] destination address =0x54840

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] next desc address =0x72e5f020

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] pktlength =1060

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] desc base address =0x72e5f000 sourse addres = 0x0

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] destination address =0x55040

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] next desc address =0x72e5f020

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] pktlength =1060

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] desc base address =0x72e5f000 sourse addres = 0x0

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] destination address =0x56040

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] next desc address =0x72e5f020

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] pktlength =1060

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] desc base address =0x72e5f000 sourse addres = 0x0

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] destination address =0x53040

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] next desc address =0x72e5f020

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] pktlength =1060

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] desc base address =0x72e5f000 sourse addres = 0x0

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] destination address =0x57840

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] next desc address =0x72e5f020

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.138680] pktlength =1060

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139486]

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139486] desc base address =0x72e5f000 sourse addres = 0x0

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139504] destination address =0x53840

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139504] next desc address =0x72e5f020

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139504] pktlength =1060

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139887]

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139887] desc base address =0x72e5f000 sourse addres = 0x0

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] destination address =0x51040

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] next desc address =0x72e5f020

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] pktlength =1060

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] desc base address =0x72e5f000 sourse addres = 0x0

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] destination address =0x54040

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] next desc address =0x72e5f020

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] pktlength =1060

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] desc base address =0x72e5f000 sourse addres = 0x0

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] destination address =0x52040

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] next desc address =0x72e5f020

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] pktlength =1060

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] desc base address =0x72e5f000 sourse addres = 0x0

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] destination address =0x51840

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] next desc address =0x72e5f020

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] pktlength =1060

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] desc base address =0x72e5f000 sourse addres = 0x0

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] destination address =0x57040

Jun 25 11:40:06 intel-corei7-64 user.warn kernel: [ 550.139905] next desc address =0x72e5f020






Thanks in advance

Regards,
Balasbramani C

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FPP Configuration Timing: Data stability requirement when DCLK-to-DATA[] ratio > 1

July 12, 2016, 2:20 am
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VC-52007 2016.06.10 Figure 7-3 shows the FPP Configuration timing for a Cyclone V when DCLK-to-DATA[] Ratio (r) is > 1.

Question: Is it really a requirement that the data pins remain remain absolutely stable for the tDH period indicated (datasheet specifies tDH(min) = (N-1)/fDCLK)? It is conceivable that the data really is clocked into the device on DCLK period 1 and that the additional r-1 padded clocks are only required for internal decompression / decrypting stages, irrespective of the data. Would it be allowable to implement r>1 using the r=1 timing shown in Figure 7-2 but (indentically) repeating DATA[] r times? Assuming that DATA[] is only clocked into the device on the rising edge of DCLK, this should be OK, even if the FPGA inspects the data on any rising DCLK edge between 1..r.

Any opinions would be appreciated.
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Custom component with interrupt

July 12, 2016, 6:07 am
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I'm working on a custom Qsys component. It does everything it's supposed to do, but it takes a long time (reading flash memory) so I need to make it non-blocking.

I added an interrupt sender to the component, and made it so that when the process is done it raises the IRQ line for 16 clock cycles. I assigned this interrupt sender a number (20) in Qsys and generated the system. I modified my driver so that it registers the interrupt on startup.

The problem is that when I run the code, every time the process is done the debugger forces a break with NIOS2_BREAK() in alt_instruction_exception_entry. There is a rather long comment in that function, and near the bottom is says the following:

Code:
  * The problem could also be hardware related:  *  - If your hardware is broken and is generating spurious interrupts
  *    (a peripheral which negates its interrupt output before its
  *    interrupt handler has been executed will cause spurious interrupts)
Do I need to add some kind of interrupt ACK into my code/component? What is that standard way this is done?
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accelerate cyclone V

July 12, 2016, 8:21 am
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Hi All,

I am using cyclone V SOC kit from Terasic.

Currentlly, I am using AXI bridge to communicate between FPGA and HPS; but I found this bridge seems to funcation with low latency. I made hps to fpga bridge connection for Light weight hps to FPGA communication.

Now I want to improve throughput and letency of communication between HPS and FPGA. any one can please suggest me to do so??

P.S : I go through exaple of Datamover; so I have another question that Is it necessary to use NIOSII Qsys componebt; if yes then could anyone explain How Nios II help to improve communication between h2f and f2h?

Thanks in advance.
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accelerate cyclone V

July 12, 2016, 8:28 am
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Hi All,

I am using cyclone V SOC kit from Terasic.

Currentlly, I am using AXI bridge to communicate between FPGA and HPS; but I found this bridge seems to funcation with low latency. I made hps to fpga bridge connection for Light weight hps to FPGA communication.

Now I want to improve throughput and letency of communication between HPS and FPGA. any one can please suggest me to do so??

P.S : I go through exaple of Datamover; so I have another question that Is it necessary to use NIOSII Qsys componebt; if yes then could anyone explain How Nios II help to improve communication between h2f and f2h?

Thanks in advance.
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problems with elf2flash --boot

July 13, 2016, 1:27 pm
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elf2flash is not inserting the boot record as it should. Is there a way to get the source for this to see why it is failing? --verbose only provided a start and stop time stamp which isn't very useful.


elf2flash is a step in "make_flash_image_script.sh" which is part of the advanced boot copier:
https://www.altera.com/en_US/pdfs/li...e/an/an458.pdf


This is the step that is failing:
elf2flash --verbose --base=$flash_base --end=$flash_end --boot=$fake_copier --input=$tmp0_outfile_elf --output=$tmp1_outfile_srec --reset=$flash_base ;
It is behaving as if didn't pass the argument --boot=$fake_copier


This same elf2flash and make_flash_image_script.sh is used on many of our projects and I would like to understand why its failing.


QSYS:
epcq controller avl_mem: 0x0200 0000 -> 0x02FF FFFF
boot rom onchip memory: 0x0003 0000 -> 0x0003 C34F
run code onchip memory: 0x0104 0000 -> 0x0107 BFFF


elf2flash:
flash_base: 0x0
flash_end: 0x1FF FFFF
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VHDL: Transport delay fails to work properly (in WVF simulation)

July 13, 2016, 2:50 pm
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I currently have some VHDL code which was written with the intended purpose of simulating waveform "A", and, via transport delay, simulating waveform "SIG" 25ns after the simulation of "A". However, the timing delay has stayed at 10ns, seemingly unable to change.

My end goal is to, in a separate set of code, delay a signal by a given amount of time, in order to allow a delay for the arrival of another signal. This code is a rough mockup to help in practicing what I hope to achieve and giving me a rough idea of what this should look like without having to use any hardware.

An image of the simulation which results from running this code is attached to the thread.

Code:
-- top level entity

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;




ENTITY Turn_Detector_On IS
PORT (
A :in STD_LOGIC;
SIG :out STD_LOGIC) ; -- SIG, the waveform we'd like delayed, is an output
END Turn_Detector_On ;




ARCHITECTURE behaviour OF Turn_Detector_On IS


-- declare signal Tell
SIGNAL Tell: STD_LOGIC;




BEGIN


PROCESS(A)
BEGIN


if A='1'THEN
Tell <= '0' after 25 ns; -- delay tell by 25ns


ELSE
Tell <= '1' after 25 ns;


End IF;


SIG  <= Tell; -- finally assign SIG the value of tell, in order to achieve delay




END PROCESS;
END behaviour ;
Any help is greatly appreciated!
Attached Images
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EDA simulation tool settings questions

July 13, 2016, 6:22 pm
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Hi:

I'm using the Quartus II 15.0 Web Edition, and when I tried to specify the option for generating output files for use with other EDA tools, my option of the tool setting only includes Active-HDL, Riviera-PRO, Modelsim, Modelsim-Altera, Questasim, custom, but I want to select the VCS. I found the Internet that the VCS should be one of the option. So should I download something else that can make me have VCS option?

Thanks so much.
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LVDS & SerDes MegaCore generation and connections

July 13, 2016, 7:21 pm
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Dear Sir,

I'm currently using DE4 board to try a Gigabit Ethernet with SGMII design.
I'm trying to generate LVDS blocks with SerDes for an SGMII application.
There are three modes, DPA, non-DPA, and soft-CDR described in the
Stratix IV handbook. For SGMII application, I am supposed to use soft-
CDR mode. I, however, can't see any selection for the soft-CDR. There
only one option similar to what we need, shown in the MegaFunction for
soft-CDR.jpg. Is it the option for SGMII? If it is, why the output clock
is still 'rx_outclock', but not 'rx_divfwdclk'?
In addtion, about the connection for the LVDS, for example tx_out_p needs
to be connected to 'ETH_TX_p0. That is PIN_T30 for the DE4 board.
How do I connect ETH_TX_n0? Will it be connected automatically?
Thanks.


Peter Chang
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sof and pof

July 13, 2016, 7:51 pm
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Dear Sir,

I have one question for the programming file generation.
After finishing the Assembler, I am supposed to have a
.sof file in the working folder. Why do I have not?
Will Quation II generate sof and pof at the same time?
Supposed, according to the experience I have several
years ago. I am currently using a QII v9.1sp2 with Web
edition license. The attached file shows that the
compilation is finished. Although it has some timing
violations for the Recovery, it doesn't matter, I think.

Thanks.


Peter Chang
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