Quantcast
Channel: Altera Forums
Viewing all 19390 articles
Browse latest View live
↧

ASMI IP Simulation

July 14, 2016, 12:26 am
$
0
0
Hi I am trying to simulate the ASMI IP with Modelsim-Altera. I am a complete n00b and the instructions to simulate IP Cores are not very clear to me.

I can compile the design and make it work on the FPGA. But when I try it on Modelsim the IP does nothing.

I have included the .qip and .sip files. My flow to the simulation works as it follows:

  1. I click on Analysis and Synthesis.
  2. I go to Tools>Run Simulation Tools>RTL Simulation
  3. When Modelsim pops up I type on the console :
    Code:
    vsim work.topfilename
  4. I create stimulus (manually, as there are not many signals).


That's all

THANK YOU!!
↧
Search

Synchronizing a state machine

July 14, 2016, 1:32 am
$
0
0
Hi,
I've got a state machine in a component and there's something I don't understand correctly. Here's the code of the component:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity filter is
  generic(
    img_width : integer := 4;
    blk_width : integer := 2;
    img_length : integer := 4;
    blk_length : integer := 2;
    data_size : integer := 12;      -- pixel size
    address_size1 : integer := 4;  -- row*column size
    address_size2 : integer := 2;  -- row size
    address_size3 : integer := 2    -- column size
    );
  port(
    clock: in std_logic;
    a_reset_n: in std_logic;                                                                        -- asynchronous reset low level
    enable_main_program: in std_logic;                                                        -- this enable gives a possibility to the main programm to inhibit all the modules if there is an error
    enable_pixel_in: in std_logic;                                                              -- enable the processing of the current pixel
    pixel_in: in std_logic_vector(data_size-1 downto 0);                    -- current pixel
    enable_pixel_out: out std_logic;                                                        -- enable the exit of the computed pixel
    pixel_out : out std_logic_vector(data_size-1 downto 0) := (others => '0')      -- computed pixel
    );
end filter;

architecture rtl of filter is

  component ram_mem is
    generic (
      data_size : integer := data_size;
      address_size : integer := address_size2
      );
    port(
      clock: in std_logic;
      a_reset_n: in std_logic;
      enable_read: in std_logic;
      enable_write: in std_logic;
      address: in std_logic_vector(address_size-1 downto 0);
      data_in: in std_logic_vector(data_size-1 downto 0);
      data_out: out std_logic_vector(data_size-1 downto 0) := (others => '0')
      );
  end component ram_mem ;

  type machine is (s0, s1, s2, s3);                    -- 4 states because a new pixel is available each 4 cycles
  signal state : machine;
 
  signal reset : std_logic;

  type enbl is array (2 downto 0) of std_logic;  -- memory(i) enable
  signal s_enable_w : enbl;
  signal s_enable_r : enbl;

  signal s_address : std_logic_vector(address_size2-1 downto 0):=(others => '0');

  type s_out is array (0 to 2) of std_logic_vector(data_size-1 downto 0);
  signal s_data_out : s_out := (others => (others => '0'));
 
  signal cntr_img_col : integer range 0 to 3 := 0;
  signal cntr_img_row : integer range 0 to 3 := 0;
  signal cntr_wmem : integer range 0 to 2 := 0;        -- actual write memory
 
  type blk_col is array (1 downto 0) of integer;
  type blk_all is array (1 downto 0) of blk_col;
  signal cur_blk : blk_all := (others => (others => 0)); -- current block

  signal sum : integer range 0 to (2**data_size)*4-1;  -- actual block sum
  signal p_enable_pixel_out : std_logic;
  signal first_img : std_logic := '1';
 
begin

  memory : for i in 0 to 2 generate
    mem : ram_mem
      generic map(
        data_size    => data_size,
        address_size  => address_size2)
      port map (
        clock => clock,
        a_reset_n => reset,
        enable_read => s_enable_r(i),
        enable_write => s_enable_w(i),
        address => s_address,
        data_in => pixel_in,
        data_out => s_data_out(i)
        );
  end generate memory;
 
  reset <= a_reset_n and enable_main_program;
 
  process (clock, reset)
  begin
    if (reset='0') then
      state <= s0;
      cntr_img_col <= 0;
      cntr_img_row <= 0;
      cntr_wmem <= 0;
      s_enable_r <= (others => '0');
      s_enable_w <= (others => '0');
      sum <= 0;
      cur_blk <= (others => (others => 0));
      enable_pixel_out <= '0';
      p_enable_pixel_out <= '0';
      first_img <= '1';

    elsif rising_edge(clock) then
      case state is
        when s0 =>
          if(enable_pixel_in = '1') then -- a pixel is coming
            s_address <= std_logic_vector(to_unsigned(cntr_img_col,address_size2));
            s_enable_w(cntr_wmem) <= '1';
            if first_img = '0' or cntr_img_row > 1 then
              for i in 0 to 2 loop
                if i=cntr_wmem then
                  s_enable_r(i) <= '0';
                else
                  s_enable_r(i) <= '1';
                end if;
              end loop;
            end if;
            enable_pixel_out <= '0';
            state <= s1;
          end if;
         
        when s1 =>
          s_enable_w <= (others => '0');
          state <= s2;
             
        when s2 =>
          s_enable_r <= (others => '0');
          if cntr_img_col = img_width-1 then
            cntr_img_col <= 0;
            if cntr_img_row = img_length-1 then
              cntr_img_row <= 0;
            else
              cntr_img_row <= cntr_img_row+1;
            end if;
            if cntr_wmem = 2 then
              cntr_wmem <= 0;
            else
              cntr_wmem <= cntr_wmem+1;
            end if;
          else
            cntr_img_col <= cntr_img_col+1;
          end if;

          cur_blk(0)(0) <= cur_blk(1)(0);
          cur_blk(0)(1) <= cur_blk(1)(1);
          if cntr_wmem=0 then
            cur_blk(1)(0) <= to_integer(unsigned(s_data_out(1)));
            cur_blk(1)(1) <= to_integer(unsigned(s_data_out(2)));
            sum <= sum+to_integer(unsigned(s_data_out(1)))+to_integer(unsigned(s_data_out(2)))-cur_blk(0)(0)-cur_blk(0)(1);
          elsif cntr_wmem=1 then
            cur_blk(1)(0) <= to_integer(unsigned(s_data_out(2)));
            cur_blk(1)(1) <= to_integer(unsigned(s_data_out(0)));
            sum <= sum+to_integer(unsigned(s_data_out(2)))+to_integer(unsigned(s_data_out(0)))-cur_blk(0)(0)-cur_blk(0)(1);
          else
            cur_blk(1)(0) <= to_integer(unsigned(s_data_out(0)));
            cur_blk(1)(1) <= to_integer(unsigned(s_data_out(1)));
            sum <= sum+to_integer(unsigned(s_data_out(0)))+to_integer(unsigned(s_data_out(1)))-cur_blk(0)(0)-cur_blk(0)(1);
          end if;

        state <= s3;
         
        when s3 =>
          pixel_out <= std_logic_vector(to_unsigned(sum/4, data_size));
          if cntr_img_col > 0 and cntr_img_row /= 1 and (first_img = '0' or cntr_img_row > 1) then
            p_enable_pixel_out <= '1';
          else
            p_enable_pixel_out <= '0';             
          end if;
          if p_enable_pixel_out = '1' then
            enable_pixel_out <= '1';
          end if;
          if cntr_img_row = img_length-1 and cntr_img_col = img_width-1 then
            first_img <= '0';
          end if;
          state <= s0;       
      end case;
    end if;
  end process;
end rtl;
and here's my testbench:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_filter is
end tb_filter;

architecture test of tb_filter is
    component filter is
  generic(
    img_width : integer := 4;
    blk_width : integer := 2;
    img_length : integer := 4;
    blk_length : integer := 2;
    data_size : integer := 12; 
    address_size1 : integer := 4;
    address_size2 : integer := 2;
    address_size3 : integer := 2
    );
  port(
    clock: in std_logic;
    a_reset_n: in std_logic;                                                                       
    enable_main_program: in std_logic;                                                   
    enable_pixel_in: in std_logic;                                                             
    pixel_in: in std_logic_vector(data_size-1 downto 0);   
    enable_pixel_out: out std_logic;               
    pixel_out : out std_logic_vector(data_size-1 downto 0);
    pixel_out_x : out std_logic_vector(address_size2-1 downto 0);
    pixel_out_y : out std_logic_vector(address_size3-1 downto 0)
    );
    end component filter;

    signal s_clock: std_logic := '1';
    signal s_a_reset_n: std_logic := '0';
    signal s_enable_in: std_logic := '0';
    signal s_enable_main_program : std_logic := '0';
    signal s_pixel_in : std_logic_vector(11 downto 0) := (others => '0');
    signal s_pixel_out : std_logic_vector(11 downto 0) := (others => '0');
    signal s_enable_pixel_out : std_logic;
    signal s_pixel_out_x : std_logic_vector(1 downto 0);
    signal s_pixel_out_y : std_logic_vector(1 downto 0);

begin
 
    comp : filter
  generic map(
    img_width => 4,
    blk_width => 2,
    img_length => 4,
    blk_length => 2,
    data_size => 12,      -- pixel size
    address_size1 => 4,  -- row*column size
    address_size2 => 2,  -- row size
    address_size3 => 2    -- column size
  )
    port map(   
    clock => s_clock,
    a_reset_n => s_a_reset_n,
    enable_main_program => s_enable_main_program,
    enable_pixel_in => s_enable_in,
    pixel_in => s_pixel_in,
    enable_pixel_out => s_enable_pixel_out,
    pixel_out => s_pixel_out,
    pixel_out_x => s_pixel_out_x,
    pixel_out_y => s_pixel_out_y
  );
 
  clock : process
  begin
    wait for 1 ns;
    s_clock <= not s_clock;
  end process;
 
  reset : process
  begin
    wait for 2 ns;
    s_a_reset_n <= '1';
    wait;
  end process;
 
  start : process
  begin
    wait for 6 ns;
    s_enable_main_program <='1';
    s_enable_in <= '1';
    wait;
  end process;
 
  test_vectors : process
  begin
    wait for 6 ns;
    for i in 0 to 15 loop
      s_pixel_in <= std_logic_vector(to_unsigned(i+1, 12));
      wait for 8 ns;
    end loop;
    wait;
  end process;
 
end test;
I'd like everything of the s2 state to be done during s1. So I simply copied everything from line 130 to 161 between 126 and 127 but the simulation result is not what I expect: cur_blk isn't correct. Do I have a problem with th RAMs management?
↧
↧

timequest cy7c68013

July 14, 2016, 4:14 am
$
0
0

the signal ports IFCLK, SLRD,FLAGS,DATA and SLOE are all from FPGA to Peripheral, in other words, they are all output for FPGA. In the timequest, what can I do to constraint the SLOE ? The setup time and hold up time of SLOE to clock isn’t directly given. the signal ports IFCLK, SLRD,FLAGS,DATA and SLOE are all from FPGA to Peripheral, in other words, they are all output for FPGA. In the timequest, what can I do to constraint the SLOE ? The setup time and hold up time of SLOE to clock isn’t directly given.
Attached Images
↧

EPCS16 Programming through Cyclone3 Device using JTAG

July 14, 2016, 4:26 am
$
0
0
Hello!

I am trying to program an EPCS16 device through a Cyclone 3 device. There are many such daughter boards which are connected to a single JTAG via a host Cyclon 2 device. IN short my configuration is like:

Host Cyclone2 --> Daughter-1 Cyclone3 --> EPCS16
|--> Daughter-2 Cyclone3 --> EPCS16
.
.
|--> Daughter-N Cyclone3 --> EPCS16

Host only multiplex JTAG signals for all daughter Cyclone3 devices.

My USB Blaster can detect daughter Cyclone3 and EPCS16 devices through host Cyclone2 and I can program them using (jam) file, but can't program using (jic) file. But if I just bypass host Cyclone2 and connect the USB blaster directly with Cyclone3, I can program using (jic) file and also can verify. Now I want to program the EPCS16 devices with (jic) files through host Cyclone2, becasue (jam) files do not give me the option for verify.

Kindly guide me, what possible problem can be there. How may I; either program (jic) file through host Cyclone2 OR verify after programming (jam) file.

Thanks.
↧

Using EPCS128 Flash in user mode, conflict pins.

July 14, 2016, 5:34 am
$
0
0
Hello everyone,

I am using the DE1-SOC board which includes a 5CSEMA5F31C6 cyclone 5 FPGA chip and a EPCS128 Flash. So I am trying to use the flash in user mode and communicate with it through serial SPI. I have assigned the pins (DCLK, AS_DATA0,......,NCSO) using the assignment editor to the right connection as drawn within the schematic diagrams provided with the development board, but the problem is the quartus 2 give me an error saying that there is a conflict in connections and here is the full text of the error when assigning the clock for SPI communication:

Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 I/O pad(s))
Error (175019): Illegal constraint of I/O pad to the location PIN_U7
Info (14596): Information about the failing component(s):
Info (175028): The I/O pad name(s): DCLK
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (169094): Can't place pin DCLK at location U7 (PAD_50) because that location is a dedicated programming pin location (1 location affected)
Info (175029): PIN_U7

I know that these pins are used for configuration at the power-up of the FPGA as it called (reserved for programming pins), but there must be a way to have them available and could access them through the same pins after programming. I have looked so hard for this problem and I didn't find anything, so how could this be solved?

Thanks,
↧
↧

Failed to enumerate any USB device through OTG in ALtera Cyclone5 SoC board

July 14, 2016, 6:26 am
$
0
0
Hi,

I am working on Altera Cyclone5 SoC board with Linux Kernel "Linux cyclone5 4.1.17-ltsi-altera". I want to enumerate USB device through OTG Interface.

I have checked and updated respective Altera Cyclone5 DTS file to add support of USB as OTG.

Quote:
usb1: usb@ffb40000 {
/*compatible = "snps,dwc2";*/
compatible = "snps,dwc-otg-15.1", "snps,dwc-otg", "snps,dwc2";
/* reg = <0xffb40000 0xffff>; */
reg = <0xffb40000 0x00040000>;
interrupts = <0 128 4>;
clocks = <&usb_mp_clk>;
clock-names = "otg";
dev-nperio-tx-fifo-size = <4096>; /* embeddedsw.dts.params.dev-nperio-tx-fifo-size type NUMBER */
dev-perio-tx-fifo-size = "<512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>"; /* embeddedsw.dts.params.dev-perio-tx-fifo-size type STRING */
dev-rx-fifo-size = <512>; /* embeddedsw.dts.params.dev-rx-fifo-size type NUMBER */
dev-tx-fifo-size = "<512 512 512 512 512 512 512 512 512 512 512 512 512 512 512>"; /* embeddedsw.dts.params.dev-tx-fifo-size type STRING */
dma-mask = <268435455>; /* embeddedsw.dts.params.dma-mask type NUMBER */
enable-dynamic-fifo = <1>; /* embeddedsw.dts.params.enable-dynamic-fifo type NUMBER */
host-nperio-tx-fifo-size = <2560>; /* embeddedsw.dts.params.host-nperio-tx-fifo-size type NUMBER */
host-perio-tx-fifo-size = <2560>; /* embeddedsw.dts.params.host-perio-tx-fifo-size type NUMBER */
/* host-rx-fifo-size = <2560>; embeddedsw.dts.params.host-rx-fifo-size type NUMBER */
host-rx-fifo-size = <512>; /* embeddedsw.dts.params.host-rx-fifo-size type NUMBER */
phys = <&usbphy0>;
phy-names = "usb2-phy";
ulpi-ddr = <0>; /* embeddedsw.dts.params.ulpi-ddr type NUMBER */
voltage-switch = <0>; /* embeddedsw.dts.params.voltage-switch type NUMBER */
status = "disabled";
};

Followig are some kernel logs regarding USB device and OTG Controller Support

Quote:
root@cyclone5:~# dmesg | grep usb
[ 0.203225] usbcore: registered new interface driver usbfs
[ 0.203285] usbcore: registered new interface driver hub
[ 0.203344] usbcore: registered new device driver usb
[ 0.203477] soc:usbphy@0 supply vcc not found, using dummy regulator
[ 1.014284] ffb40000.usb supply vusb_d not found, using dummy regulator
[ 1.020924] ffb40000.usb supply vusb_a not found, using dummy regulator
[ 1.061106] dwc2 ffb40000.usb: EPs: 16, dedicated fifos, 8064 entries in SPRAM
[ 1.921191] dwc2 ffb40000.usb: DWC OTG Controller
[ 1.925900] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1
[ 1.932957] dwc2 ffb40000.usb: irq 47, io mem 0x00000000
[ 1.938396] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[ 1.945168] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 1.952367] usb usb1: Product: DWC OTG Controller
[ 1.957050] usb usb1: Manufacturer: Linux 4.1.17-ltsi-altera dwc2_hsotg
[ 1.963643] usb usb1: SerialNumber: ffb40000.usb
[ 1.987992] usbcore: registered new interface driver usb-storage
[ 2.103199] usbcore: registered new interface driver usbhid
[ 2.108747] usbhid: USB HID core driver



root@cyclone5:~# dmesg | grep otg
[ 1.957050] usb usb1: Manufacturer: Linux 4.1.17-ltsi-altera dwc2_hsotg
I am not able to enumerate any USB device through OTG cable. I am not getting interrupt after connecting or disconnecting any USB device.

So, is there any kernel configuration or device tree configuration missing to work OTG support on this board?

Please let me know if anyone has any idea ro clue to solve this issue.

Regards,
Ritesh Prajapati
↧

print result of nios ii custum instruction on model sim?

July 14, 2016, 6:41 am
$
0
0
Hello
I add sqrt as custom instructio to nios ii and generate built system in sopc and all things ok.
I write simple code in nios2 ide and simulate it with modelsim but not any result show .
print NaN or 0.0000!!!
How can i solve this problem?
quartus 9.0 and modelsim 6.4a and niosii9 ide used.
Thank you
↧

Hierarchical reference to custom type

July 14, 2016, 8:26 am
$
0
0
I have a state machine defined with the following lines in one of my source files:
type SM_STATES is (idle, state1, state2, state3, state4);
signal current_state : SM_STATES;

In my testbench, I want to wait until this state machine has reached a certain state before allowing the test sequence to continue. I've tried various combinations of the following line of code, but can't get it to compile.
wait until <<signal .tb_top.u_top.u_state_machine.current_state : SM_STATES>> = state1;


I'm pretty sure I could move the type declaration to a package and then instantiate the package in my testbench, but that seems to be more of a workaround than true hierarchical reference. Does anyone know the correct syntax to check using hierarchical reference that the current state is state1?

Thanks - Much appreciated!
↧
Search

Reducing Interconnect (IC) delay with evenly distributed pipeline stages

July 14, 2016, 1:20 pm
$
0
0
Hi,

I am getting setup violations because of large interconnect delay. I've added several pipeline stages to reduce the interconnect delay but Quartus is not doing a very good job of spreading the pipeline registers out. It is clustering some of the pipeline registers whereas I would expect them to be evenly distributed. Here are some examples of the pipeline register locations:

Example 1:
x146 y1 n17 (source)
x146 y1 n13 (intermediate register)
x144 y1 n35 (intermediate register)
x144 y1 n11 (intermediate register)
x63 y1 n28 (intermediate register)
x49 y0 n115 (destination)

Example 2:
x139 y7 n37 (source)
x66 y4 n45 (intermediate register)
x66 y4 n2 (intermediate register)
x65 y4 n56 (intermediate register)
x65 y4 n14 (intermediate register)
x38 y0 n43 (destination)

Is there a trick to get Quartus to spread out the pipeline registers in a more intelligent manner? I'm aware of manual location assignments as an option but when there are hundreds of such registers, manual placement is not very appealing.

Thanks,
Philippe

P.S.
Here's how I implemented the pipeline stages. I used the syn_preserve attribute to prevent Quartus from inferring an lpm_shiftreg.

reg source;
reg [3:0] pipeline /* synthesis syn_preserve = 1 */;
reg destination;

always @ (posedge clk) begin
pipeline <= {pipeline[2:0],source};
destination <= pipeline[3];
end
↧
↧

Error message for a LVDS at receiver side

July 14, 2016, 11:36 pm
$
0
0
Dear Sir,

I got one error message as below. It is for an IP from MegaWizard.
The IP is an LVDS with a SerDes. I don't know what the compensated input mean?
And, it seems that the LVDS has been set to a non-DPA mode. As far as I know,
the mode I need is soft-CDR for a SGMII interface. A little confused. There is
no option for the mode of soft-CDR.


Error: Input clock pin of fast PLL altlvds_rx_top:altlvds_rx_top|altlvds_rx:altlvds_r x_component|altlvds_rx_top_lvds_rx:auto_generated| pll, which drives at least one non-DPA-mode SERDES, must be driven by a compensated input


Regards,


Peter Chang
↧

Quetion for the LVDS at transmitter side

July 15, 2016, 3:37 am
$
0
0
Dear Sir,

I have a question about the option as the attached file, when
using MegaWizard to create a LVDS for tx. What is the option
for? Thanks.
It will cause an error in my design as below.

Error: Output port "DATAOUT" of DDIO_OUT WYSIWYG "altlvds_tx_top:altlvds_tx_top|altlvds_tx:altlvds_ tx_component|altlvds_tx_top_lvds_tx:auto_generated |altlvds_tx_top_ddio_out:ddio_out|ddio_outa_0" has invalid signal-splitter fan-outs.

Regards,


Peter Chang
↧

Network unreachable with Ubuntu in DE1-SoC even when the Ethernet cable is connected

July 15, 2016, 10:41 am
$
0
0
I am using Altera DE1-SoC for booting Ubuntu and I am able to boot it and root into it. But when I try to do apt-get update or apt-get install function-name, I am not able to connect to network and it's unreachable always, even when I try to connect through Ethernet. I'm not sure whether my Ethernet cable is getting recognized, but I could see a orange light coming on the port.

This is the error that I get, when I try to connect to the network. I am helpless in this issue and any inputs will be greatly appreciated.
Cannot initiate the connection to ports.ubuntu.com:80 (91.189.88.151). - connect (101: Network is unreachable)


Thanks,
Swaminath
Attached Images
↧

Constraining Derived External Clocks

July 15, 2016, 11:43 am
$
0
0
I have an external reference clock coming into the fabric through the PLL (lets call it clk1 at the output of the PLL)
I then divide this clock and send it out to the pins to an external (board) clock network to multiple devices including myself.
Lastly I take the divided clock as an input through another set of pins into another PLL (lets call it clk2 at the output of the 2nd PLL)
The PLLs are just used to maintain phase alignment to the reference clocks.

To simplify lets assume the division is by 2.

Can we tell timequest that the clk1 and clk2 are related?
How can I model the skew and other board/device effects on clk2 so that timing path between clk1 and clk2 is captured accurately.

Gracias,

Cecil
↧
↧

System Console under Linux (Quartus Prime Programmer and Tools package)

July 15, 2016, 3:04 pm
$
0
0
Hello, I need to launch System Console under Linux , so I've installed a "Quartus Prime Programmer and Tools" package (QuartusProgrammerSetup-16.0.0.211-linux.run)

However, there is no system-console binary. Installation wizard offers to launch it and fails. I've checked installed files and indeed it is not there.

Do you know if it is supported under Linux ? And how can I install it?

Thanks,
Roman
↧

Legacy EPCS Flash Controller

July 16, 2016, 10:35 am
$
0
0
Hello,

I am using quartus 14.1. I have a NIOS based system having a legacy EPCS controller interfaced to Spansion device.
With Legacy EPCS controller IP, I could flash FPGA + NIOS image using .jic file and get the build to work.

However, when I program the flash using .pof file, I could see only FPGA is up, whereas NIOS application does not work.

Then I changed the controller to Altera Serial Flash controller. With this, I could get both FPGA and NIOS work.

I am very curious to understand the difference between these two IPs?
Why .pof works with a build having Altera Serial Flash controller, but not with Legacy EPCS controller.

Help is appreciated!

Thanks
↧
Search

Unable to build "*.elf" file in NIOS II Eclipse.

July 17, 2016, 9:23 am
$
0
0
Hi All,

I am novice in NIOS II Eclipse environment.

To learn I am using the existing project and after compiling the nios project in Quartus.

In order to generate the "*.elf" file, I created new project by pointing to "*nios_cpu.sopcinfo" file and added existing source file to the project.

To build the project I am clicking on "Build all" but NIOS II Eclipse environment is throwing error (Attached snapshot).

Console Message

Info: Linking TEST2.elf
nios2-elf-g++ -T'../TEST2_bsp//linker.x' -msys-crt0='../TEST2_bsp//obj/HAL/src/crt0.o' -msys-lib=hal_bsp -L../TEST2_bsp/ -Wl,-Map=TEST2.map -O0 -g -Wall -mno-hw-div -mhw-mul -mno-hw-mulx -o TEST2.elf obj/default/DBC5CEFA7_appl.o obj/default/aoeappl.o obj/default/bootmode.o obj/default/coeappl.o obj/default/db_nioshw.o obj/default/ecataoe.o obj/default/ecatappl.o obj/default/ecatcoe.o obj/default/ecatfoe.o obj/default/ecatslv.o obj/default/foeappl.o obj/default/mailbox.o obj/default/objdef.o obj/default/sdoserv.o -lm
c:/altera/14.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/4.8.3/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: TEST2.elf section `.text' will not fit in region `onchip_memory'
c:/altera/14.1/nios2eds/bin/gnu/h-x86_64-mingw32/bin/../lib/gcc/nios2-elf/4.8.3/../../../../../H-x86_64-mingw32/nios2-elf/bin/ld.exe: region `onchip_memory' overflowed by 93988 bytes
collect2.exe: error: ld returned 1 exit status
make: *** [TEST2.elf] Error 1

Please help me to resolve the issue.

Waiting for your valuable reply.

Thanks in advance. For your valuable time
NRM.
Attached Images
↧

10M50DA clock frequency PLL in EPE

July 17, 2016, 12:15 pm
$
0
0
Hi ALTERA-forum,

I am new to the FPGA design and now want to start with the EPE. Now I have two problems. One with the frequencies and another with the dissipation.


1. I want to use the 10M16DA F484 because of the DDR3 interface support.
Now I want to calculate the estimated power dissipation. Probably later I will switch to a higher FPGA like the 10M50DA F484. To calculate the worst case power dissipation, I decided to use the EPE and the 10M50DA model.
At this point it is not known what the FPGA will do in the future so no design is ready at this point.
So using the Quartus for all the data is no solution.
Nevertheless I am a bit confused with the EPE and the maximum Clock and PLL frequency.
So I looked up alot datasheets when I was reading the handbook/guide for the EPE.
I stopped when I was looking for the max frequencies. For the PLL it is given in the sheet for the clock and PLL. It is 1300MHz like the EPE said.
But for the clock the maximum frequency is not given in the sheets. Only the EPE is given out a warning that the max frequency is 600MHz. So how is the frequency calculated or where can I find this hint/data in the datasheets? I looked up every sheet which is recommended to the EPE or the datasheet of the MAX10 but I cant find this value.
Please can anyone help me?

2. I called the ALTERA support and get the EPE filled up with some data which are a bit irreal (the support said it). But its ok because I wanted it so for the worst case. For example it is really unrealistic that all LEs are toggling at the same time.
So I looked up his data and filled in my own. At the end my electrical Power was round about 7W.
Is this possible? I know that there are 30% margin for the load current, but I dont know if 7W are to less. I calculated the power using LVCMOS at 3.3V, because I know that at least 140 pins are use as bidirectional LVCMOS signals.
So what is the most realistic electrical power the 10M50DA can consume? Are there any data or experiences in this point?


Best wishes and thank you for the help.


PS: Sorry if my English isnt that good. If there any questions in understanding my "Wirrwarr" please ask and I will try to do my best again.:)
↧
↧

"elftoflash" reporting error while programming the NIOS CPU on Cyclone V device

July 18, 2016, 12:05 am
$
0
0
Hi friends,

I am novice in NOIS II CPU,

I am using an existing example design and trying to learn the NIOS II CPU. After successful generation of the ".elf" file, to flash NIOS II COU on to cyclone V device I am using available GUI flash programmer.

But in the process,flash programmer is reporting error "Boot copier file name required", I am not getting where to specify the filename of boot copier.

Console message :

Info: Jul 18, 2016 12:23:16 PM - (INFO) elf2flash: args = --input=C:/Project/On_Going_Chapters/ETHERCAT/DEVBOARD/NEW_NIOS/DBC5_ECAT/DBC5CEFA7_EtherCAT/software/NIOS_V2/NIOS_V2.elf --output=C:/Project/On_Going_Chapters/ETHERCAT/DEVBOARD/NEW_NIOS/DBC5_ECAT/DBC5CEFA7_EtherCAT/flash/NIOS_V2_db_epcq_0_data.flash --base=0x2000000 --end=0x4000000 --reset=0x2800000 --verbose
Info: Jul 18, 2016 12:23:16 PM - (FINE) elf2flash: Starting
Info: Jul 18, 2016 12:23:16 PM - (SEVERE) elf2flash: Boot copier file name required
Info: Jul 18, 2016 12:23:16 PM - (SEVERE) elf2flash: Error generating Flash file, exiting
Error: Error code: 5 for command: elf2flash --input="C:/Project/On_Going_Chapters/ETHERCAT/DEVBOARD/NEW_NIOS/DBC5_ECAT/DBC5CEFA7_EtherCAT/software/NIOS_V2/NIOS_V2.elf" --output="C:/Project/On_Going_Chapters/ETHERCAT/DEVBOARD/NEW_NIOS/DBC5_ECAT/DBC5CEFA7_EtherCAT/flash/NIOS_V2_db_epcq_0_data.flash" --base=0x2000000 --end=0x4000000 --reset=0x2800000 --verbose


Please help me to resolve the issue.

And also please provide me any user guide reference on NIOS II CPU for understanding the error reported by the tool.


Thanks in advance for your valuable time.

Regards
NRM
↧

Error: Error code: 8 for command: nios2-flash-programmer while flashing "*.elf" file.

July 18, 2016, 5:15 am
$
0
0
Hi Friends,

I am a Novice in NIOSII CPU,

I am using the existing demo project and trying to flash "*.elf" file to Cyclone V device. In the process flash programmer is repeatedly reporting the error code 8, I have no idea howto resolve the issue , please guide me to overcome the issue,Below is the text reported by the flash programmer :

**********************************
Info: Jul 18, 2016 5:04:53 PM - (INFO) elf2flash: args = --input=C:/Project/On_Going_Chapters/ETHERCAT/DEVBOARD/NEW_NIOS/DBC5_ECAT/DBC5CEFA7_EtherCAT/software/NIOS_V3/NIOS_V3.elf --output=C:/Project/On_Going_Chapters/ETHERCAT/DEVBOARD/NEW_NIOS/DBC5_ECAT/DBC5CEFA7_EtherCAT/software/NIOS_V2_bsp/flash/NIOS_V3_db_epcq_0_data.flash --base=0x2000000 --end=0x4000000 --reset=0x2800000 --verbose
Info: Jul 18, 2016 5:04:54 PM - (FINE) elf2flash: Starting
Info: Jul 18, 2016 5:04:54 PM - (FINE) elf2flash: Done
Info: Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Info: Resetting and pausing target processor: OK
Info: Reading System ID at address 0x04004520: verified
Info: No CFI table found at address 0x02000000
Info: Original contents (after writing 0xF0 and 0xFF00FF to address 0x02000000):
Info: 0: F0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
Info: 10: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
Info: 20: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
Info: 30: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
Info: 40: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
Info: Contents after writing 0x980098 to address 0x020000AA:
Info: Same after writing 0x980098 to address 0x02000154:
Info: Same after writing 0x00980098 to address 0x020002A8:
Info: Same after writing 0x980098 to address 0x02000055:
Info: Same after writing 0x980098 to address 0x020000AA:
Info: Same after writing 0x00980098 to address 0x02000154:
Info: Same after writing 0x980098 to address 0x02000154:
Info: Same after writing 0x980098 to address 0x020002A8:
Info: Same after writing 0x00980098 to address 0x02000550:
Info: 0: F0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
Info: 10: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
Info: 20: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
Info: 30: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
Info: 40: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
Info: Leaving target processor paused
Error: Error code: 8 for command: nios2-flash-programmer "C:/Project/On_Going_Chapters/ETHERCAT/DEVBOARD/NEW_NIOS/DBC5_ECAT/DBC5CEFA7_EtherCAT/software/NIOS_V2_bsp/flash/NIOS_V3_db_epcq_0_data.flash" --base=0x2000000 --sidp=0x4004520 --id=0xDBC5CE --timestamp=1468776040 --device=1 --instance=0 '--cable=USB-Blaster on localhost [USB-0]' --program --verbose
**********************************

And please provide me link, where I can get all the error list reported in NIOS II IDE.

Thanks in advance for your valuable time.

Regards
NRM
↧

Can I probe an altlvds_tx output or altlvds_rx input in stratix iv on DE4?

July 18, 2016, 6:19 am
$
0
0
Can I probe an altlvds_tx output or altlvds_rx input in stratix iv on DE4?
↧
Viewing all 19390 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>