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Question Regarding to the MAX V eval board.

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I am new user try to run my simple test on Altera Max V eval kit. I wrote a simple code want to verify a simple function:

in file counter.v
Code:

module counter( CLOCK_10KHZ, counter_out, RESET);


input CLOCK_10KHZ;
input RESET;
output [15:0] counter_out;
reg [15:0] counter_out;


always @(posedge CLOCK_10KHZ) begin
    if (!RESET)    begin        //Reset button is not pushed
        counter_out <= #1 ~(counter_out + 1); //increment counter, neg light up the LED, and pos turn off
    end
    else begin
        counter_out <= #1 ~16'b0;
    end
end


endmodule


When I push the reset button, the LED goes off, that proved clock trigger signal is correct, however, after I release the PB1, all LEDs still on and didn't change status(It suppose to light up and turn off while counter increasing).
Platform: Windows 7,64bit, Quartus Prime Lite Edition 16.0. MAX V Eval Board

Could anyone take a look what might be wrong with my program?
Thank you!
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Max 10 Invalid internal configuration mode for design with memory init Q16.0

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I started a new project in Quartus 16.0, I have a Qsys Nios II core with some peripherals attached. No matter what I do I get an error when I compile the processor with flash Error (14703): Invalid internal configuration mode for design with memory initialization

I've have the configuration mode in device an pin options set to "Single Uncompressed Image 256Kbits UFM", And in the Qsys project, the onchip_flash is set to single uncompressed image (see png attached)



These settings should match up but it continues to tell me there is an error. I've even tried to compile under the 10M16SA version of the chip and different projects configuration settings, nothing seems to work.
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NIOS II soft reset

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Hi i am new to the NIOS II features. I am working on a cyclone V (5CEFA4U19C7) which has a Nios II processor in it. I want to do a soft reset which is, resetting the NIOS without power cycling it. I did the watchdog timer , but I have a doubt in it as to whether the resetrequest signal should be tied to the reset input of the timer block(a pic is attached). Also how do I test the soft reset, coz the document says that the system will reset when the software stops executing normally, how to get this feature to work so that i can test whether the soft reset is working or not.

Please guide me through this problem.

Thanks,
Sid
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I got this warning messages. Is is OK?

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Hello,

I don't have good english skills.

but I want to know this mesaages as bellow.


Warning (13012): Latch N_XDIO_OE_CPU$latch has unsafe behavior
Warning (13013): Ports D and ENA on the latch are fed by the same signal N_XZCS0


Warning (10631): VHDL Process Statement warning at CPLD_120mm_CPU.vhd(55): inferring latch(es) for signal or variable "N_CPLD_TEST", which holds its previous value in one or more paths through the process

I am using EPM1270T144I5N device.

I am using well the device. but I got that warning messages. So I am worried because of the messages.

If I have to solve that messages, What I have to do? please help me.

I will wait for reply.

thank you for reading.

PowerPlay estimation and asynchronous faster-than-clock signal: no clock domain found

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Hi all,

I am a newbie and I have a simple task at hand.

I am working on a simple controller project on a Max3000A series device with an input signal that is faster than the system clock. This signal and the system clock are externally generated using external oscillators and are then fed into the device through a general I/O pin and a dedicated GCLK pin, respectively. The essence of this signal is to be ANDed with another signal internally generated in the device before being ported out of the device as an output pin. It is not intended to pass through any register in the device, only a single AND gate. I believe that makes its operation asynchronous. It is necessary for me to do this so I can obtain the 5kHz signal I need to drive the kind of buzzer I intend to.

In the power estimation process with PowerPlay Power Analyzer, I get the report that relative toggle rate could not be calculated because no clock domain was found for some nodes in my design and this results in a low confidence level for the estimated power. I think it is because of this 'asynchronous' signal, I am not sure (especially because I don't understand the term 'clock domain', which I will like somebody to help explain to me and, moreso, because I probably haven't represented this signal well in the testbench since it is not supposed to be bounded by the clock).

I need to know how to get a 'high-confidence' power estimation with the PowerPlay Power Analyzer in a scenario like this. And please remember to explain 'clock domain' too. Thanks.

Akanimo.

Fitter I/O Rule Results in all pin

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Hello
I create another project and i can’t find Fitter I/O Rules Results from customize columns for to add in All pin list.
In my pervious project it exists. See the attached file
Do you have a idea?
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Quartus Prime not allowing apparently correct I/O assignment

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Hi, I'm using Quartus Prime 15.1 and trying to program the DECA evaluation board. I've used a file provided by them to do the pin assignments. I am completely sure that I have used the correct one. When I compile, the Analysis and Synthesis runs just fine. However, the fitter keeps giving the following errors:

Error (169235): I/O bank 8 cannot select VCCIO of 1.2V which is required for pin LED[0] with I/O standard 1.2
Error (169193): VCCIO 1.2V is not compatible with the VCCIO requirement of the I/O bank 8 imposed by the selected configuration scheme


It shows the same thing for LED[1] which I am also using, which connects to a green LED on the board. One possible lead: the device that I select is 10M50DAF484C6GES, but I keep getting the following message: Info (253020): Default device 10M08DAF484C8G is automatically selected for the device family MAX 10. This message displays as soon as the device is selected when creating a new project.

Can anyone explain why this might be happening? Thanks!

Edit: never mind about that default device message, that comes when I select the MAX 10 family prior to selecting the specific device

VHDL problem

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Hi everyone,
I'm a new user of FPGA.
I have 2 LEDs and a clock of 32KHz.
So I wanna light up LED1
then light off LED 1 and light up LED2.
Im trying to do something in VHDL, but it seems it's nonsense what I've done



LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_SIGNED;
use IEEE.STD_LOGIC_UNSIGNED;
use IEEE.STD_LOGIC_ARITH.ALL;


ENTITY TP4LED IS
PORT (
clock : IN std_logic;
s1: OUT std_logic;
s2: OUT std_logic
);
END TP4LED;


ARCHITECTURE behavior OF TP4LED IS -- fonctionnement d'une bascule D


signal count : integer(10 downto 0);
BEGIN


PROCESS (clock) -- liste de sensibilité


BEGIN
count <= '0';
s1<='1';
s2<='0';
if(clock'event and clock='1')then
count <= count + 1;
if (count = '9') then
s1<='0';
s2<='1';
count<=0;
end if;
end if;
END PROCESS;
END behavior;

In addition, I have this mistake that I don't know how to resolve it
Error (10380): VHDL error at TP4LED.vhd(24): integer type is used but not declared as an array type


I know it might be an easy question. Could anyone help me please
thank you very much
Bo

Max10 On-Chip-Flash/Dual Configuration Unconstrained Clocks

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Hi,

I'm using altera_dual_boot and altera_onchip_flash in a MAX10M08DAF256C8G with Quartus Prime Lite 15.1.0.
In TimeQuest I get the followed messages:

Node: ...|altera_onchip_flash_onchip_flash|altera_onchip _flash_avmm_data_controller:avmm_data_controller|r ead_state.READ_STATE_SETUP was determined to be a clock but was found without an associated clock assignment.
Register ...|altera_onchip_flash_onchip_flash|altera_onchip _flash_block:altera_onchip_flash_block|ufm_block~X E_YE_TO_SE_FF is being clocked by ...|altera_onchip_flash:onchip_flash|altera_onchip _flash_avmm_data_controller:avmm_data_controller|r ead_state.READ_STATE_SETUP

Node: ...|altera_dual_boot:dual_boot|alt_dual_boot_avmm: alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boo t|ru_clk was determined to be a clock but was found without an associated clock assignment.
Register ...|altera_dual_boot:dual_boot|alt_dual_boot_avmm: alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boo t|ru_regout is being clocked by ...|altera_dual_boot:dual_boot|alt_dual_boot_avmm: alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boo t|ru_clk

Are there any solutions to constrain the signals and avoid this messages?

Thanks and best regards
Guenter

Stratix 5 and PCIe reference design - How to change a target device ?

How to determine values of M, N, C, charge pump and loop filter for PLL reconfig?

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The cyclone IV PLL takes in a 144 bit stream for PLL reconfig. This contains 18 bits for each C4, C3, C2, C1, C0, M and N and 9 bits each for charge pump and loop filter. This information is contained in table 5-7 on pg 5-37 of the cyclone iv handbook.

For a given input frequency and desired output frequency from the PLL. How does one determine the value of all these things I mentioned above?
Is there a unique set of values to get a specific output frequency-phase relationship to an input frequency or can multiple values of this 144 bit (made up of 9 fields in total) word achieve the same result?

DRAM problem U-Boot & customization

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Hi everybody,
I hope you're well.

I've been working several days with meta-layer, because I'm working in a custom Altera SoCFPGA board trying to put linux, and I have two questions.
Well my problem by now is when I try to boot with the compiled image from Yocto using bitbake, it stops in DRAM initialization step like in the photo.



Maybe I'm not compiling the right U-Boot? Should I configure any hardware?
I mean... in the U-Boot header I read "U-Boot 2016.05" but the actual branch in
https://github.com/altera-opensource/u-boot-socfpga is based in 2013.01.01 like the preloader. And it looks like a misconfiguration of hardware, so for example I don't have any I2C peripheral and it is trying to configure it until times out.

But in the recipe of altera layer in Yocto. meta-altera/recipes-bsp/u-boot/u-boot-socfpga_2016.05.bb it looks like it's based in a newer version.


Paths in bblayers.conf are set, and in local.conf file I've changed the MACHINE and added the followings lines:
MACHINE = "cyclone5"
PREFERRED_PROVIDER_virtual/kernel = "linux-altera"
PREFERRED_VERSION_linux-altera = "4.6%"
GCCVERSION = "linaro-5.2"
SDKGCCVERSION = "linaro-5.2"
DEFAULTTUNE = "cortexa9hf-neon"
BB_NUMBER_THREADS ?= "8"
PARALLEL_MAKE ?= "-j 8"

Thank you in advance =)
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Stratix 5 and PCIe Reference Design. How to change the target device ?

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Hi everyone,

I'm using a DE5-NET-450 development board from Terasic (http://www.terasic.com.tw/cgi-bin/pa...English&No=526) with a 5SGXEA7N2F45C2 FPGA and Quartus Prime 15.1.0.

I'm trying to run the PCIe reference design (Revision 5) proposed by Altera (http://www.alterawiki.com/wiki/Refer...MA_-_Stratix_V).

My problem is that the device used to develop this reference design is a 5SGXEA7K2F40C2 FPGA. I changed the target device in Quartus Prime and QSys, and I lost the pin assignment, which is understable as the devices are differents.

Thanks to the DE5-Net User Manual, I tried to reassign the required pins, but I struggle to fill them all. I founded to assign the PCIE_TX and PCIE_RX pins but I'm missing a lot of the others (See the list below).

Is it possible to easily change the target device of a reference design? Am I missing something obvious?

It looks like this issue is not a complicated one, but I can't figurate out how to solve it. If anyone has tips, I would appreciate some help to make this design run on my board.

Thank you,

Cc44600

P.S. List of the missing pins
set_location_assignment PIN_xx -to "refclk1_ql0_p(n)"
set_location_assignment PIN_xx -to refclk1_ql0_p
set_location_assignment PIN_xx -to "refclk4_ql2_p(n)"
set_location_assignment PIN_xx -to refclk4_ql2_p
set_location_assignment PIN_xx -to "refclk5_ql2_p(n)"
set_location_assignment PIN_xx -to refclk5_ql2_p
set_location_assignment PIN_xx -to "refclk0_qr0_p(n)"
set_location_assignment PIN_xx -to refclk0_qr0_p
set_location_assignment PIN_xx -to "refclk1_qr0_p(n)"
set_location_assignment PIN_xx -to refclk1_qr0_p
set_location_assignment PIN_xx -to "refclk2_qr1_p(n)"
set_location_assignment PIN_xx -to refclk2_qr1_p
set_location_assignment PIN_xx -to "refclk4_qr2_p(n)"
set_location_assignment PIN_xx -to refclk4_qr2_p
set_location_assignment PIN_xx -to "refclk5_qr2_p(n)"
set_location_assignment PIN_xx -to refclk5_qr2_p

set_location_assignment PIN_xx -to reconfig_xcvr_clk
set_location_assignment PIN_xx -to perstn
set_location_assignment PIN_xx -to local_rstn
set_location_assignment PIN_xx -to req_compliance_pb
set_location_assignment PIN_xx -to set_compliance_mode

set_location_assignment PIN_xx -to hsma_clk_out_p2

Cyclone 5 PLLs

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Is there a programatic way to re-configure the on chip PLLs? I don't mean loading a new .mif file, but rather having the embedded OS calculate the constants required to re-load the PLL for a different frequency?

I would like to have the embedded OS be able to generate a wider range of frequencies off of the base clock.

Thanks,
Jon Herr

asmi_parallel mixed simulation

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Trying to simulate the asmi_parallel IP in Modelsim. My code is VHDL, IP is Verilog. First attempt resulted in "Unresolved defparam reference to .." error occurring 13 times. Added altera_mf_ver and lpm_ver libraries to VSIM command line generated by Quartus Prime 16.0. This eliminated 12 of the errors. Two related errors remain: "Unresolved defparam reference to 'sd4' in sd4.enable_sim" and sd4.lpm_type. I am unable to find missing library if that is problem. Appears to be related to cyclonev_asmiblock. Any insight to solution greatly appreciated.

MAX-II Input pins never detect a LO

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All, I tried to post this in the Quartus II and Tools discussion but I have never received a response.

My Setup:
Quartus II 9.0
MAX-II PLD
Schematic entry

http://www.alteraforum.com/forum/showthread.php?t=53340

Also, now I have tied a few pins together. Such as: input pins 27,28,29,30 and output pins 108, 107, 106, 105 respectively. So pin 108 should follow pin 27...etc..... but..... it doesn't.
NO matter how I have programmed the input. TTL... CMOS... Schmitt... with pullups.... without pullups...... all 6-different ways.

I have tried several different pins and have tried 2 different PLDs.
I have tried putting latches on the inputs and clock them with a 30MHz clock to see if I can capture the pin input.... but ..... no avail.
Some of my other input pins seem to work, and I have tried to set up these pins exactly as the ones that work, but NO JOY.

For the most part the other functions of my design are working as expected, just this 4-bit address comparator to the CHIP_ID address section doesn't seem to be wanting to work.
The only way it works is if all 4-bit inputs are HI and or floating, so only address oxF (15) will work.

Am I not setting up my "Assignments" correctly or......

Thanks,
Keith

Error 12006: undefined entity

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Hi Everybody,

I got this error
Error (12006): Node instance "instrumentation_fabric" instantiates undefined entity "alt_sld_fab". Make sure that the required user library paths are specified correctly. If the project contains EDIF Input Files (.edf), make sure that you specified the EDA synthesis tool settings correctly. Otherwise, define the specified entity or change the calling entity. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/suppo...se/search.html and search for this specific error message number.

I checked all reasons from the beginning:
1. Make sure that the required user library paths are specified correctly. --> Ok
2.If the project contains EDIF Input Files (.edf), make sure that you specified the EDA synthesis tool settings correctly.


Do I correctly set up?
3.Otherwise, define the specified entity or change the calling entity.
I really do not know how to check it??

Would you mind to help me with the second and third reason?
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using h2f_axi_master

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Hi,
I used h2f_lw_axi_master to transfer data between hps to fpga. in this state maximum rate to on/off one IO pin was 3MHz. to increase rate, I used h2f_axi_master. in this state the rate increased to 6MHz, I think this rate of transforming data is very low. How can i use h2f_axi_master with maximum performance?
best regards

Problem with ALTCLKCTRL module and outputs from two different PLLs in Cyclone III

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Hello!
I'v got a Cyclone III device EP3C16U256. And i have got a two external clock signals 10 MHz and 30 MHz (they are connected to dedicated clock pins on different sides of FPGA). I want to make 120 MHz clock from 10 MHz clock and 120 MHz clock from 30 MHz clock. And i want to dynamicaly switch between them (120 MHz from 10 MHz and 120 MHz from 30 MHz).

I wrote this code:
Code:

...
/*** PLL from 30 MHz to 120 MHz ***/   
omsp_pll omsp_pll_inst (
    .inclk0                    ( mclk ),
    .c0                        ( internal_ss_clk )
);




/*** PLL from 10 MHz to 120 MHz ***/
sync_pll    sync_pll_inst
(
    .inclk0                    ( sync_clk ),
    .c0                        ( sync_ss_clk ),
    .locked                    ( sync_pll_locked_sig )
);




/*** ALTCLKCTRL module ***/
clk_mux    clk_mux_inst
(
    .clkselect                ( ss_clk_select_sig ),
    .inclk0x                ( internal_ss_clk ),   
    .inclk1x                ( sync_ss_clk ),   
    .outclk                ( ss_clk_sig )
);
...

And i have an error in Quartus (Quartus II 64-Bit Version 13.1.0 ):
Quote:

Error (15669): inclk port of Clock Control Block "clk_mux:clk_mux_inst|clk_mux_altclkctrl_uhi:clk_m ux_altclkctrl_uhi_component|clkctrl1" must be driven by 1 PLLs but is driven by 2 PLLs
Info (15670): Clock Control Block is driven by PLL "omsp_pll: omsp_pll_inst|altpll:altpll_component|omsp_pll_alt pll:auto_generated|pll1"
Info (15670): Clock Control Block is driven by PLL "sync_pll:sync_pll_inst|altpll:altpll_component|sy nc_pll_altpll:auto_generated|pll1"

How can i solve this problem?

Using SPI and I2C on MAX10

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Hi Community,

I have a question about using SPI and I2C with the MAX10.
There are no dedicated pins for SPI and I2C on the MAX10 pin description.
Does that mean I can decide which pins I want to use for this?

It will be a simple answered question for you but I'm not sure about this.

Thanks in advance
Jérôme
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