Hi
Can any one knows whether we can have altera's free PWM Ipcore, If yes can you provide the source
Can any one knows whether we can have altera's free PWM Ipcore, If yes can you provide the source
↧
PWM IPcore
↧
How to reset a ram?
Hi,
in my vhdl design I got a ram signal R then I try to test it against A with "if A > R then..." but R starts with a 'X' value so the test is not working. What could I do to solve that problem?
Thanks.
in my vhdl design I got a ram signal R then I try to test it against A with "if A > R then..." but R starts with a 'X' value so the test is not working. What could I do to solve that problem?
Thanks.
↧
↧
List of OpenCL supporting boards
I apologize for this basic question. But, I couldn't find a way to get the list of boards that supports OpenCL. In particular, our group bought a board before I joined and no one has any documents on the purchase. The board is DK-DEV-5SGXEA7N (https://www.altera.com/products/boar...v-gx-host.html).
Can any one tell me how do I verify whether it supports OpenCL? How do I look for a board support package? I found a place for BSPs in wiki (http://www.alterawiki.com/wiki/Category:OpenCL). But, it does not have anything for Startix V.
Thanks
Can any one tell me how do I verify whether it supports OpenCL? How do I look for a board support package? I found a place for BSPs in wiki (http://www.alterawiki.com/wiki/Category:OpenCL). But, it does not have anything for Startix V.
Thanks
↧
Downloading ELF process failed while using the external memory present in the board
Hi,
I'm using the BeMicro Kit and I'm using the external 8MB RAM present in the board. I've added the SDRAM controller in the Qsys along with the NIOS II/e processor and it compiled successfully. When I'm compiling the software in the Eclipse it throws an error " Downloading ELF Process Failed". I tried using the NIOS II command shell to download the elf file but it also gives an error " Verify failed between address 0X0 and 0XFFFF ". I have also attached the error message of the NIOS II command shell and the Qsys screenshot. Can anyone please suggest me where am I going wrong ?
Note: I've already set the "Reset Vector and Exception Vector to sram"
Thanks,
Swarnava Pramanik
I'm using the BeMicro Kit and I'm using the external 8MB RAM present in the board. I've added the SDRAM controller in the Qsys along with the NIOS II/e processor and it compiled successfully. When I'm compiling the software in the Eclipse it throws an error " Downloading ELF Process Failed". I tried using the NIOS II command shell to download the elf file but it also gives an error " Verify failed between address 0X0 and 0XFFFF ". I have also attached the error message of the NIOS II command shell and the Qsys screenshot. Can anyone please suggest me where am I going wrong ?
Note: I've already set the "Reset Vector and Exception Vector to sram"
Thanks,
Swarnava Pramanik
↧
Arria 10 Dev Kit -- PCIe enumeration
Does an image exist for the Arria 10 GX FPGA Development Kit that is capable of enumerating over PCIe when installed in a PC :
1.) arria10GX_10ax115sf45_fpga_v15.1.2\examples\transc eiver\PRD\qts_pcie\qts_pcie\qts_pcie.sof
2.) arria10GX_10ax115sf45_fpga_v15.1.2\examples\board_ test_system\image\PRD\bts_pcie.sof
?
1.) arria10GX_10ax115sf45_fpga_v15.1.2\examples\transc eiver\PRD\qts_pcie\qts_pcie\qts_pcie.sof
2.) arria10GX_10ax115sf45_fpga_v15.1.2\examples\board_ test_system\image\PRD\bts_pcie.sof
?
↧
↧
Cyclone IV epe spreadsheet not able to open
Hi,
I have downloaded the EPE for cyclone IV but when i tried to open excel sheet it is throwing an error " file is corrupted and not able to open"
but i am able to open other family spreadsheet. is it problem with latest version?
I have downloaded the EPE for cyclone IV but when i tried to open excel sheet it is throwing an error " file is corrupted and not able to open"
but i am able to open other family spreadsheet. is it problem with latest version?
↧
** Error: (vsim-3170) Could not find in altera quartus Lite 16.0 edition
Hi,
I am using altera quartus lite 16.0 version. During simulation in the wave editor i am getting this Error message " ** Error: (vsim-3170) Could not find 'C:/altera_lite/16.0/quartus/bin64/new/simulation/qsim/work.fulladdt_b_vlg_vec_tst'.#
# Error loading design
Error loading design"
Can anyone help regarding this issue?
Thanks,
Nabila
I am using altera quartus lite 16.0 version. During simulation in the wave editor i am getting this Error message " ** Error: (vsim-3170) Could not find 'C:/altera_lite/16.0/quartus/bin64/new/simulation/qsim/work.fulladdt_b_vlg_vec_tst'.#
# Error loading design
Error loading design"
Can anyone help regarding this issue?
Thanks,
Nabila
↧
Cyclone IV PLL min input frequency
Hi,
What is minimum input clock for Cyclone IV E PLL? Data sheet states that minimum Fin=5MHz, but PLL locks even to 500KHz input clock freqency. Can someone explain this to me?
Thanks
What is minimum input clock for Cyclone IV E PLL? Data sheet states that minimum Fin=5MHz, but PLL locks even to 500KHz input clock freqency. Can someone explain this to me?
Thanks
↧
Ethernet connection on DE2-115 with the Standard Edition of Quartus 15.1
Hello,
In my project I am trying to make work the Ethenet connection of our DE2-115 board.
The FPGA associated to it is a Cyclone IV and our version of Quartus is Quartus Prime 15.1.
For the moment, I can not make work both the Web server exemple explained with the User Manual of the DE2-115
and the Using Triple-Speed Ethernet on DE2-115 Boards tutorial.
So I have these followed question:
Is it able to use the Ethernet connection with a Cyclone IV FPGA?
Is it possible to use the Ethenet connection with a Standard Edition of Quartus 15.1?
Help are welcome.
BR
Didier
In my project I am trying to make work the Ethenet connection of our DE2-115 board.
The FPGA associated to it is a Cyclone IV and our version of Quartus is Quartus Prime 15.1.
For the moment, I can not make work both the Web server exemple explained with the User Manual of the DE2-115
and the Using Triple-Speed Ethernet on DE2-115 Boards tutorial.
So I have these followed question:
Is it able to use the Ethernet connection with a Cyclone IV FPGA?
Is it possible to use the Ethenet connection with a Standard Edition of Quartus 15.1?
Help are welcome.
BR
Didier
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↧
calculate needed set clock uncertainty from ppm
hi,
So have a 125mhz with ppm of 300, my calcualtions are:
300ppm is 0.03% of 8 ns -> 2.4ps ~3ps
so i had put on the SDC:
set_clock_uncertainty -rise_from [get_clocks {clk125}] -rise_to [get_clocks {clk125}] -setup 0.003
set_clock_uncertainty -rise_from [get_clocks {clk125}] -fall_to [get_clocks {clk125}] -setup 0.003
set_clock_uncertainty -fall_from [get_clocks {clk125}] -rise_to [get_clocks {clk125}] -setup 0.003
set_clock_uncertainty -fall_from [get_clocks {clk125}] -fall_to [get_clocks {clk125}] -setup 0.003
set_clock_uncertainty -rise_from [get_clocks {clk125}] -rise_to [get_clocks {clk125}] -hold 0.003
set_clock_uncertainty -rise_from [get_clocks {clk125}] -fall_to [get_clocks {clk125}] -hold 0.003
set_clock_uncertainty -fall_from [get_clocks {clk125}] -rise_to [get_clocks {clk125}] -hold 0.003
set_clock_uncertainty -fall_from [get_clocks {clk125}] -fall_to [get_clocks {clk125}] -hold 0.003
is that looks right?
or i should double the value?
So have a 125mhz with ppm of 300, my calcualtions are:
300ppm is 0.03% of 8 ns -> 2.4ps ~3ps
so i had put on the SDC:
set_clock_uncertainty -rise_from [get_clocks {clk125}] -rise_to [get_clocks {clk125}] -setup 0.003
set_clock_uncertainty -rise_from [get_clocks {clk125}] -fall_to [get_clocks {clk125}] -setup 0.003
set_clock_uncertainty -fall_from [get_clocks {clk125}] -rise_to [get_clocks {clk125}] -setup 0.003
set_clock_uncertainty -fall_from [get_clocks {clk125}] -fall_to [get_clocks {clk125}] -setup 0.003
set_clock_uncertainty -rise_from [get_clocks {clk125}] -rise_to [get_clocks {clk125}] -hold 0.003
set_clock_uncertainty -rise_from [get_clocks {clk125}] -fall_to [get_clocks {clk125}] -hold 0.003
set_clock_uncertainty -fall_from [get_clocks {clk125}] -rise_to [get_clocks {clk125}] -hold 0.003
set_clock_uncertainty -fall_from [get_clocks {clk125}] -fall_to [get_clocks {clk125}] -hold 0.003
is that looks right?
or i should double the value?
↧
Sdio host controller implementation with verilog
Hi Team,
Can you provide the TECHNICAL SPECIFICATION and RTL or CODE for the implementation of SDIO Host Controller module?
Many many thanks,
Gyan
Can you provide the TECHNICAL SPECIFICATION and RTL or CODE for the implementation of SDIO Host Controller module?
Many many thanks,
Gyan
↧
Using JESD204B?
Hello, quick question about JESD204B. Does it require that you use a NIOS II processor?
Thanks,
Joe
Thanks,
Joe
↧
Tcl Script name File .qip not found
Hello
I have a warning Tcl Script name File .qip not found.
How suppress this message?
Thank you.
I have a warning Tcl Script name File .qip not found.
How suppress this message?
Thank you.
↧
↧
Arria V, ARM Cortex-A9 clock speed (the -3 version)
I have an industrial application that is forcing me to use the -3 core speed.
With that said I am trying to decrease the overall core speed of the ARM cores.
I see they are at 1GHz (as a -3 selection) and am looking to try and decrease them to around 500MHz to save power.
Is this possible?
I have been searching for various multiplier, clock speed sections and have come up short in manuals, forums, etc.
The goal is to get this Arria V to be as power lean as possible.
Thank you.
With that said I am trying to decrease the overall core speed of the ARM cores.
I see they are at 1GHz (as a -3 selection) and am looking to try and decrease them to around 500MHz to save power.
Is this possible?
I have been searching for various multiplier, clock speed sections and have come up short in manuals, forums, etc.
The goal is to get this Arria V to be as power lean as possible.
Thank you.
↧
Conversion error (integer to std_logic_vector) "Undefined symbol 'to_signed'"
Hello everyone!
I'm just starting into VHDL programming and I've been asked to make a 0 to 999 counter (as BCD incrementor Suggested Experiment 3.9.3 in FPGA Prototyping by VHDL Examples by Pong P.Chu ), since I'm not such a good programmer I decided to do it first from 0 to 9, so I wanted to try it with this code here:
I understand that it can be done with a delay but since this excercise is supposed to be done with things we hhave seen in class and until this chapter we hadn't seen delays/clocks this is why I came up with the pushbutton idea, the problem I'm having is that when I try to compile it, Xilinx ISE (I'm using Xilinx ISE for programming and the Basys2 board) gives me this errors:
I don't understand why is this, I already tried with "conv_signed" but it is the same result, can someone help me and let me know where am I wrong? Thanks
I'm just starting into VHDL programming and I've been asked to make a 0 to 999 counter (as BCD incrementor Suggested Experiment 3.9.3 in FPGA Prototyping by VHDL Examples by Pong P.Chu ), since I'm not such a good programmer I decided to do it first from 0 to 9, so I wanted to try it with this code here:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity BCD_Increm is
Port ( i : in STD_LOGIC; -- using it as a pushbutton to increment the counting
unit : out STD_LOGIC_VECTOR(3 DOWNTO 0));
end BCD_Increm;
architecture BCD_arch of BCD_Incr is
signal un : integer;
signal u : std_logic_vector(3 downto 0);
signal usi : signed (3 downto 0);
begin
un<='0'; -- starts with 'units' in 0's
unit <= u;
process(i,un)
begin
if (i=1) then -- check if pushbutton is 'on'
if (un <= 9) then -- check if units is less than or equal to 9
un <= un + 1; -- if so, then add 1 to units
usi <= to_signed(un,4); -- convert to signed
u <= std_logic_vector(usi(3 downto 0)); --convert to std_logic_vector
else
un <= 0; -- if units is greater than 9 then units are 0
usi <= to_signed(un,4); -- convert to signed
u <= std_logic_vector(usi(3 downto 0)); -- convert to std_logic_vector
end if;
else
un <= un; --if pushbutton is not 'on' then keep the same value for units
usi <= to_signed(un,4); -- convert to signed
u <= std_logic_vector(usi(3 downto 0)); --convert to std_logic_vector
end if;
end process;
end BCD_arch;Quote:
Code:
Line 47. Undefined symbol 'to_signed'.
Line 47. to_signed: Undefined symbol (last report in this block)
Line 48. usi: Undefined symbol (last report in this block)↧
Modelsim Error in Startup Script
Hi everyone,
I am new to using Quartus and ModelSim and am receiving and error message when I try to launch ModelSim. I enter vsim in my command terminal and receive the message in the attachment. Any help with resolving this issue is greatly appreciated.
I am new to using Quartus and ModelSim and am receiving and error message when I try to launch ModelSim. I enter vsim in my command terminal and receive the message in the attachment. Any help with resolving this issue is greatly appreciated.
↧
Code size for Small Hello World
Hi,
I am trying out the NIOS II running on MAX 10 FPGA. I found that by compiling the small hello world template project which just output the string "Hello from NIOS II" using the alt_putstr function, the code size is 3888 byte!
I remember the small hello world used to be very small in size. Not sure why is it becoming so large now.
I appreciate if anybody can help to shed some light and advise for me.
Thanks.
I am trying out the NIOS II running on MAX 10 FPGA. I found that by compiling the small hello world template project which just output the string "Hello from NIOS II" using the alt_putstr function, the code size is 3888 byte!
I remember the small hello world used to be very small in size. Not sure why is it becoming so large now.
I appreciate if anybody can help to shed some light and advise for me.
Thanks.
↧
↧
Arrow Sockit: /lib/libc.so.6: version `GLIBC_2.17' not found
Hi,
I just started experimenting with the Arrow SocKit board that has Cyclone V SoC + FPGA.
I was provided with a BSP and Linux image by terasic.
My development platform is windows and have installed Altera Design Suite 16, AOCL SDK 16.
After programming the device, when I try to execute the kernel, I am having these errors:
************************************************** *************
root@socfpga:~/testProgram# ./kernel
./kernel: /lib/libc.so.6: version `GLIBC_2.17' not found (required by ./kernel)
************************************************** *************
The version that is installed in linux is:
************************************************** *************
root@socfpga:~# /lib/libc.so.6
GNU C Library (Ubuntu EGLIBC 2.15-0ubuntu10) stable release version 2.15, by Roland McGrath et al.
Copyright (C) 2012 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.
Compiled by GNU CC version 4.6.3.
Compiled on a Linux 3.2.14 system on 2012-04-19.
Available extensions:
crypt add-on version 2.1 by Michael Glad and others
GNU Libidn by Simon Josefsson
Native POSIX Threads Library by Ulrich Drepper et al
Support for some architectures added on, not maintained in glibc core.
BIND-8.2.3-T5B
libc ABIs: UNIQUE
************************************************** *************
How can I move from "Ubuntu EGLIBC 2.15" to "GLIBC_2.17".
There was one thread in this forum where they moved to Angstrong filesystem (https://rocketboards.org/foswiki/view/Documentation/AngstromOnSoCFPGA_1)
I dont want to move to that filesystem. I want to be able to use the BSP + Linux that terasic provided.
Thanks in advance.
Waj (Newbie to SocKit)
I just started experimenting with the Arrow SocKit board that has Cyclone V SoC + FPGA.
I was provided with a BSP and Linux image by terasic.
My development platform is windows and have installed Altera Design Suite 16, AOCL SDK 16.
After programming the device, when I try to execute the kernel, I am having these errors:
************************************************** *************
root@socfpga:~/testProgram# ./kernel
./kernel: /lib/libc.so.6: version `GLIBC_2.17' not found (required by ./kernel)
************************************************** *************
The version that is installed in linux is:
************************************************** *************
root@socfpga:~# /lib/libc.so.6
GNU C Library (Ubuntu EGLIBC 2.15-0ubuntu10) stable release version 2.15, by Roland McGrath et al.
Copyright (C) 2012 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.
Compiled by GNU CC version 4.6.3.
Compiled on a Linux 3.2.14 system on 2012-04-19.
Available extensions:
crypt add-on version 2.1 by Michael Glad and others
GNU Libidn by Simon Josefsson
Native POSIX Threads Library by Ulrich Drepper et al
Support for some architectures added on, not maintained in glibc core.
BIND-8.2.3-T5B
libc ABIs: UNIQUE
************************************************** *************
How can I move from "Ubuntu EGLIBC 2.15" to "GLIBC_2.17".
There was one thread in this forum where they moved to Angstrong filesystem (https://rocketboards.org/foswiki/view/Documentation/AngstromOnSoCFPGA_1)
I dont want to move to that filesystem. I want to be able to use the BSP + Linux that terasic provided.
Thanks in advance.
Waj (Newbie to SocKit)
↧
Si5338 in Cyclone V GX Starter Kit
Hello,
I have been trying to figure out how to program the Si5338C that is used as a clock generator for the Cyclone V GX starter kit. Basically I need two different clocks with frequencies of 125 MHz and 125.01 MHz. I am using quartus prime and have been looking in the megafunctions provided by altera but until now I can not find any solution. Silicon Lab has a software called clock builder desktop but works only on evaluation board sold by them. Can someone point me how to configure the Si5338 directly on the Cyclone V GX starter Kit ? Thanks alot in advance.
Jallix
PS: I am quite a beginner in FPGA development.
I have been trying to figure out how to program the Si5338C that is used as a clock generator for the Cyclone V GX starter kit. Basically I need two different clocks with frequencies of 125 MHz and 125.01 MHz. I am using quartus prime and have been looking in the megafunctions provided by altera but until now I can not find any solution. Silicon Lab has a software called clock builder desktop but works only on evaluation board sold by them. Can someone point me how to configure the Si5338 directly on the Cyclone V GX starter Kit ? Thanks alot in advance.
Jallix
PS: I am quite a beginner in FPGA development.
↧
sdo_from the_epcs_controller Assignment
I am currently trying to upgrade a design (well more redo) from Quartus 13 to 16.
I doing so i have tried using the altera_epcq_controller in place of the Legacy Flash controller in order to access the EPC16 in order to get the code for the NIOS cpu.
Unlike the old core the 4 pins required tin interface are not exported to the top level as per the Documentation.
When i add the 4 assignment as per docs
data0_to_the_epcs_controller = DATA0
sdo_from the_epcs_controller = DATA1,ASDO
dclk_from_epcs_controller = DCLK
sce_from_the_epcs_controller = FLASH_nCE
when compiling the project i get the following error
Critical Warning (136021): Ignored assignment LOCATION which contains an invalid node name "sdo_from the_epcs_controller"
The other 3 Nodes are found and map to the correct pins.
Any one know what the name of the node is or if it even required i have to assume this is the same as the node epcs_flash_controller_0_external_sdo in the legacy core.
Any help would be great
Cheers
I doing so i have tried using the altera_epcq_controller in place of the Legacy Flash controller in order to access the EPC16 in order to get the code for the NIOS cpu.
Unlike the old core the 4 pins required tin interface are not exported to the top level as per the Documentation.
When i add the 4 assignment as per docs
data0_to_the_epcs_controller = DATA0
sdo_from the_epcs_controller = DATA1,ASDO
dclk_from_epcs_controller = DCLK
sce_from_the_epcs_controller = FLASH_nCE
when compiling the project i get the following error
Critical Warning (136021): Ignored assignment LOCATION which contains an invalid node name "sdo_from the_epcs_controller"
The other 3 Nodes are found and map to the correct pins.
Any one know what the name of the node is or if it even required i have to assume this is the same as the node epcs_flash_controller_0_external_sdo in the legacy core.
Any help would be great
Cheers
↧