Hello,

I am unable to actvate the 88e1111 on my DE2-115. (Nios is running, config with cpu, on chip mem, 2xscattergather DMA, and 1 TSE, as in the docmentation of various tutorials, RGMII is set via jumper and selected in QSYS)

I narrowed down my problem to a very simple program (based on the examples and the Altera Triple-Speed ethernet docs).

First observation is that even the link LED on my switch does not come up. (cable and switch were tested with a PC). The speed leds on the DE2-115 indication the PHY baud rate and other leds near the chip stay dark.

The data sheet of the 88e1111 cannot be found, this not helping.
questions:

1) What are the minimum requirements to get the link up ? Is this done by the PHY by itself (i assume) ? Does it suffice to initialize the MAC adresses, the MDIO space 0, and the right value in register 16 of the PHY.

2) I can read and write the scratch register and read the TSE version. But if i use the following code to reset the PHY, nios hangs:

Code:

alt_printf(" Software reset of PHY chip and wait ... \n");



   *(tse + 0x80) = *(tse + 0x80) | 0x8000;

 while ( *(tse + 0x80) & 0x8000  );

  alt_printf(" Software reset of PHY chip ok ! \n");

I included a print of my qsys configuration, a copy of the instantiation and my C program as a .doc.

Many thanks in advance.
Johi.

Attached Images

qsys.jpg (18.0 KB)

Attached Files

Hw_netw_ana_project_DE115.v (7.7 KB)
hello_world.doc (3.7 KB)

↧

Cyclone V and simulation of ASMI Parallel

September 16, 2016, 4:23 pm

≫ Next: Board Extension for DE1-SoC

≪ Previous: Unable to acitvate 88e1111 on DEII-115

Hello everyone,

I am trying to simulate ASMI Parallel IP with no obvious success. I really need this block to get access to the external FLASH device. To get familiar with this IP, I decided to use its simplest (IMO) function: "bulk_erase". It would be very easy to validate in hardware and should be simple to implement and simulate. So, I went though the process of creating ASMI Parallel using QSYS and then added the .qsys file to my test project. It compiles fine, but for some reason the Model-Sim gives me all these errors:

# Loading EPCQ_CONTROLLER.EPCQ_CONTROLLER_asmi_parallel_0
# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(321): Unresolved defparam reference to 'addbyte_cntr' in addbyte_cntr.width.
# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v
# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(322): Unresolved defparam reference to 'addbyte_cntr' in addbyte_cntr.lpm_type.
# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v
# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(342): Unresolved defparam reference to 'gen_cntr' in gen_cntr.width.
# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v
# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(343): Unresolved defparam reference to 'gen_cntr' in gen_cntr.lpm_type.
# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v
# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(363): Unresolved defparam reference to 'stage_cntr' in stage_cntr.width.
# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v
# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(364): Unresolved defparam reference to 'stage_cntr' in stage_cntr.lpm_type.
# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v
# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(384): Unresolved defparam reference to 'wrstage_cntr' in wrstage_cntr.width.
# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v
# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(385): Unresolved defparam reference to 'wrstage_cntr' in wrstage_cntr.lpm_type.
# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v
# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(416): Unresolved defparam reference to 'sd4' in sd4.enable_sim.
# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v
# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(417): Unresolved defparam reference to 'sd4' in sd4.lpm_type.
# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v
# Error loading design

I know people has done this before, but I was not able to find any examples on-line on how to do that. The attached is a test project with a state machine and a test bench. I would really appreciate if someone would help me to figure this out and get going with the project.

Thanks,
Yev

Attached Files

RU.qar (79.2 KB)

↧

Board Extension for DE1-SoC

September 17, 2016, 8:36 am

≫ Next: Can an FPGA reset itself?

≪ Previous: Cyclone V and simulation of ASMI Parallel

Hello,

I'm looking for a solution how to connect to make "available" the DE1-SoC board for sensor boards with limited number of contacts, e.g. from here:
http://store.digilentinc.com/pmod-ex...s/pmod-boards/

On DE1-SoC there are two 40-pins headers (please see the snapshot below).
It would be nice to have some extension board that wires one (or better two) 40-pins header(s) to several standard headers (e.g. Pmod from Digilent, that have 6 or 12 pins).
Is someone aware of such extension boards ?

Thanks in advance.

Pavel

Attached Images

DE1-SoC.JPG (243.1 KB)

↧

Can an FPGA reset itself?

September 18, 2016, 3:23 am

≫ Next: verilog task passing values

≪ Previous: Board Extension for DE1-SoC

Hello forum members,

I'm using a Cyclone IV board and would like to drive the configuration from a microcontroller attached to some pins on its expansion header, as follows:

* on power-up, the FPGA configs itself using the EPCS flash chip
* that config simply wires the EPCS chip through to pins on the expansion header
* the microcontroller can now read and modify the flash chip, i.e. upload a new bitstream
* the puzzle: how to make the FPGA reset and reload from flash again, triggered by the microcontroller
* the challenge is to do this without modifying the board, i.e. no re-wiring of the config button

Preferably, reloading should use a different start address in flash, so that the next full power cycle starts the whole process again. If that's not possible, I could include logic in the application bitstream to wire through as above on startup, and then continue with startup after one second (in case no new bitstream is sent).

My reason for this is to be able to hand out a pre-configured board, which allows occasional reconfiguration without needing a USB blaster on-site.

Is it possible? I'm still exploring and looking through the documentation and resources on the web, so any pointers would be most welcome.

Cheers,
-jcw

PS. I did find http://www.alteraforum.com/forum/sho...eset+itself%3F - but it does not seem to lead to an answer.

↧

verilog task passing values

September 18, 2016, 7:20 am

≫ Next: Changing VCCIO voltage during device operation (Cyclone)

≪ Previous: Can an FPGA reset itself?

In verilog ,I have doubt while passing different values of one argument to task

eg:-
module sample_ref(input wire clkA, rstA ,SA, output wire d);

initial
begin
repeat(6)
@(posedge clkA) #1;
operation(rstA,SA);
end

task operation(input wire rst, s);
begin
if(rst)
$display("@%0t test1",$time);
else if(s)
$display("@%0t test2",$time);
end
endtask
endmodule

// here when I try to pass values of variable SA to s inside the task at different times(not at initial time), it didn't enter in to the task. Please explain these..

↧

Changing VCCIO voltage during device operation (Cyclone)

September 18, 2016, 11:12 am

≫ Next: Illegal I/O standard

≪ Previous: verilog task passing values

Hello,
Is it possible to regulate the VCCIO voltage in order to achieve different voltage standards during FPGA (Cyclone I) operation?
And the second question: Can I turn off VCCIO in some IO banks, then reconfigure the device and power VCCIO again on these banks? (VCCINT and VCCIO of configuration pins will be supplied permanently)

↧

Illegal I/O standard

September 18, 2016, 11:52 pm

≫ Next: max speed for banks (MAX10)

≪ Previous: Changing VCCIO voltage during device operation (Cyclone)

Hi,

When I compile my design I end up in the following error:
Error (169092): Illegal I/O standard 3.3 V Schmitt Trigger for pin <SCL> -- I/O standard not supported by output pins in target device

I do understand that the corresponding pin of the SCL node does not support Schmitt trigger I/O. My question is how do I identify which all pins are Schmitt trigger enabled or if any of the pins support Schmitt trigger. I am using a MAX10 FPGA (10M02).

Thanks in advance. :)

↧

max speed for banks (MAX10)

September 19, 2016, 12:42 am

≫ Next: EQFP144 footprint

≪ Previous: Illegal I/O standard

Hi Community,

i looked up different datasheets but didn't found the information about the speed for the single banks.
It is written in quartus that the banks 1 & 8 have lower speed than the rest of them.
But what is the difference in speed?
Where can I find this information?

I'll only use the FPGA for LVCMOS logic.
Where can I find the option to pick the I/O standard LVCMOS 2.5V in the Pin Planner. It only shows the 3V and 3.3V option. Do I have to use 2.5V default?
LVDS won't be used and the imigration of a DDR3 interface is planned for the far future, but not needed at this time.

So, could you please tell me where to find the speed information?
Or what is the low speed rate and what the high speed rate?
What is the amount of difference?

Thanks in advance.
Jérôme

↧

EQFP144 footprint

September 19, 2016, 1:22 am

≫ Next: ALTDDIO_OUT error 15874

≪ Previous: max speed for banks (MAX10)

Hi Guys,

Can you share me the EQFP144's PCB footprint for Allegro? It sees Altera didn't include into their device family footprints package.

↧

ALTDDIO_OUT error 15874

September 19, 2016, 1:42 am

≫ Next: Two Modelsim windows

≪ Previous: EQFP144 footprint

Hi, I don`t know if this is the right forum for creating this thread.

I have a problem when I use the ALTDDIO_OUT IP component in Quartus II, for a Cyclone V device. I want to use the same output pin for two input pins. I have a selector that tells you if you want to route one input pin or another to that output pin.

In my case, I have two input ports: gb_A_tx_data and br1A_Rx_data. One of these inputs -gb_A_tx_data- comes from the ALTDDIO_OUT module, from its dataout output signal, like this

ddr_pin_out_gb_A : DDR_PIN_OUT
port map (
aclr => reset,
datain_h => ddr_out_gb_A_high,
datain_l => ddr_out_gb_A_low,
outclock => clk125,
dataout => gb_A_tx_data
); .

To select which port is going to the output port, I have done this:

gb_A_tx_d <= gb_A_tx_data when fpga_mode /= "00" else br1A_Rx_data;

The purpose of my device is to select which signal I want to connect to the output pin gb_A_tx_d. When I make that case, I receive this error:

Error (15874): Output port DATAOUT of DDIO_OUT primitive "Port_Arbiter:inst7|DDR_PIN_OUT:ddr_pin_out_gb_A|a ltddio_out:ALTDDIO_OUT_component|ddio_out_hgj:auto _generated|ddio_outa[4]" must drive input port I of I/O OBUF primitive or input port DATAIN of DELAY_CHAIN primitive.
Error (15874): Output port DATAOUT of DDIO_OUT primitive "Port_Arbiter:inst7|DDR_PIN_OUT:ddr_pin_out_gb_A|a ltddio_out:ALTDDIO_OUT_component|ddio_out_hgj:auto _generated|ddio_outa[3]" must drive input port I of I/O OBUF primitive or input port DATAIN of DELAY_CHAIN primitive.
Error (15874): Output port DATAOUT of DDIO_OUT primitive "Port_Arbiter:inst7|DDR_PIN_OUT:ddr_pin_out_gb_A|a ltddio_out:ALTDDIO_OUT_component|ddio_out_hgj:auto _generated|ddio_outa[2]" must drive input port I of I/O OBUF primitive or input port DATAIN of DELAY_CHAIN primitive.
Error (15874): Output port DATAOUT of DDIO_OUT primitive "Port_Arbiter:inst7|DDR_PIN_OUT:ddr_pin_out_gb_A|a ltddio_out:ALTDDIO_OUT_component|ddio_out_hgj:auto _generated|ddio_outa[1]" must drive input port I of I/O OBUF primitive or input port DATAIN of DELAY_CHAIN primitive.

If I don`t make the case and I connect directly the dataout to the output pin, I don`t receive the error. I mean, if I make gb_A_tx_d <= gb_A_tx_data I don't have any problem.

I understand that the ALTDDIO_OUT must be connected to the output pin directly. But, how can I get my purpose? Is that possible?

↧

Two Modelsim windows

September 19, 2016, 2:20 am

≫ Next: using io as clk inputs

≪ Previous: ALTDDIO_OUT error 15874

Hi,
I'm using Modelsim for my VHDL simulations and I'd like to compare two different designs. Is there a way to have two different simulation windows?

↧

using io as clk inputs

September 19, 2016, 6:31 am

≫ Next: Help with firts NIOS code

≪ Previous: Two Modelsim windows

Hi Community,

is it possible to use the io s as pixelclk input?
I dont read anything that it isnt possible.

Regards
Jérôme

↧

Help with firts NIOS code

September 19, 2016, 11:09 am

≫ Next: How create an alias name for an output from derive_pll_clocks in sdc file?

≪ Previous: using io as clk inputs

Hello, please with my first nios code.

#include "alt_types.h"
#include "sys/alt_irq.h"
#include "system.h"
#include <stdio.h>
#include <unistd.h>

int main(void){
int a = 1000;

alt_printf("Probehl RESET, uz zase ziju!\n");
while (1){
alt_printf("AHOJ\n");
usleep(500000);
alt_printf("Tady NIOS II!\n");
usleep(500000);
alt_printf("%i\n", a);

}
return 0;
}

variable a not print to jtaguart...why?

Thanks

↧

How create an alias name for an output from derive_pll_clocks in sdc file?

September 19, 2016, 2:14 pm

≫ Next: Flash

≪ Previous: Help with firts NIOS code

In the sdc file I include

derive_pll_clocks

This generates some clock names which are very long and difficult to read. As this will be used in may subsequent expressions for constraining I want a short-hand version.
What is the best way to create a short named alias for such derived clock? Would it work using something like?

set shortClock Inst|.....|divclk

Example:
derive_pll_clocks #This generates clock named like this...
Inst_clock_in|clock_gen_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk

set MyShortHandClock Inst_clock_in|clock_gen_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk

Edit: using set command above has definitely the drawback that the short-hand clock name is not appearing in the timing_analyzer reports. So still looking for better ways.

↧

Flash

September 20, 2016, 1:27 am

≫ Next: Scatter Gather DMA C code from altera wiki ?

≪ Previous: How create an alias name for an output from derive_pll_clocks in sdc file?

My question is about Flash
I need to understand the operation mode of Flash like Serial and Quad-Serial; What is the difference between them?
and Can the same part work on the 2 modes?

↧

Scatter Gather DMA C code from altera wiki ?

September 20, 2016, 1:55 am

≫ Next: maximum IOs per bank

≪ Previous: Flash

Hello

I used the sg dma example design from
"http://www.alterawiki.com/wiki/File:Sg-dma.zip"

I run that on cycloneV

the qsys connection are as the following

the design is waiting for and "blocked:" here
while(tx_done == 0) {}

what can I check to debug that ?

Thanks!

↧

maximum IOs per bank

September 20, 2016, 1:56 am

≫ Next: MAX7000A config size

≪ Previous: Scatter Gather DMA C code from altera wiki ?

Hi Community,

referred to the m10_sidg.pdf p.7 table 2. I will use a deserializer (MAX9276) and the outputs of this IC are using the LVCMOS standard.
I looked up the DS of the IC with the electrical characteristics and under my given input signals (RX TX), there is an output current of 3mA.
Does this mean I can only use 65% of each bank, because it is not recommended to use more than 65% of each bank using the I/O Standard?

Regards
Jérôme

↧

MAX7000A config size

September 20, 2016, 2:04 am

≫ Next: Is Quartus Prime 16.0 available for 32 bit Windows?

≪ Previous: maximum IOs per bank

I need to touch an existing products and I should determine the size of the configuration EEPROM (of EPM7032) what I could not find in documentation. Could someone help me how/where can I find CPLD's configuration memory size?

thanks,
gabor

↧